AD6643-250EBZ

AD6643_17 AD | Alldatasheet

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FEATURES

11-bit, 250 MSPS output data rate per channel Performance with NSR enabled SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS Performance with NSR disabled SNR: 66.2 dBFS up to 90 MHz at 250 MSPS SFDR: 85 dBc up to 185 MHz at 250 MSPS Total power consumption: 706 mW at 200 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) Differential analog inputs with 400 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes

APPLICATIONS

Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, L TE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios GENERAL DESCRIPTION The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. FUNCTIONAL BLOCK DIAGRAM VIN+A D0± D10± VIN–A PIPELINE ADC NOISE SHAPING REQUANTIZER VIN+B VIN–B NOTES 1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A AND CHANNEL B LVDS OUTPUT DATA. PIPELINE ADC SERIAL PORT REFERENCE 14 11 NOISE SHAPING REQUANTIZER AD6643 DATA MULTIPLEXER AND LVDS DRIVERS 14 11 CLOCK DIVIDER VCM DCO± OEB SCLK SDIO CSB CLK+ AVDD AGND DRVDD CLK– SYNC PDWN 09638-001 Figure 1. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR per- formance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. (continued on Page 3)

AD6643* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD6643 Evaluation Board
• AD9643 Evaluation Board DOCUMENTATION Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of Switched- Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-851: A WiMax Double Downconversion IF Sampling Receiver Design
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD6643: Dual IF Receiver Datasheet User Guides
• UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters TOOLS AND SIMULATIONS
• Visual Analog
• AD6643 IBIS Model
• AD6643 LFCSP Analog Input S-Parameter DESIGN RESOURCES
• AD6643 Material Declaration
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• Symbols and Footprints DISCUSSIONS View all AD6643 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. C | Page 3 of 40 When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required. After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels. The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo- nent cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing. The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Two ADCs are contained in a small, space-saving, 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package. 2. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. 3. LVDS digital output interface configured for low cost FPGA families. 4. Operation from a single 1.8 V supply. 5. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 6. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

Rev. C | Page 4 of 40 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 1. AD6643-200 AD6643-250 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 11 11 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±10 ±10 mV Gain Error Full +2/−6 −5/+3 % FSR Differential Nonlinearity (DNL)1 Full ±0.1 ±0.25 ±0.1 ±0.4 LSB Integral Nonlinearity (INL)1 Full ±0.2 ±0.25 ±0.2 ±0.4 LSB MATCHING CHARACTERISTIC Offset Error 25°C ±13 ±13 mV Gain Error 25°C −2/+3.5 −2.5/+3.5 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±87 ±87 ppm/°C INPUT REFERRED NOISE VREF = 1.75 V 25°C 0.614 0.614 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 pF Input Resistance3 Full 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 V POWER SUPPLIES Supply Voltage Supply Current IAVDD1 Full 238 260 256 275 mA IDRVDD1 (NSR Disabled) Full 154 215 180 215 mA IDRVDD1 (NSR Enabled—22% Mode) Full 172 206 mA IDRVDD1 (NSR Enabled—33% Mode) Full 186 218 mA POWER CONSUMPTION Sine Wave Input1 (DRVDD = 1.8 V, NSR Disabled) Full 706 855 785 873 mW Sine Wave Input1 (DRVDD = 1.8 V, NSR Enabled—22% Mode) Full 738 832 mW Sine Wave Input1 (DRVDD = 1.8 V, NSR Enabled—33% Mode) Full 765 853 mW Standby Power4 Full 90 90 mW Power-Down Power Full 10 10 mW 1 Measured using a 10 MHz, 0 dBFS sine wave, and 100 Ω termination on each LVDS output pair. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured using a dc input and the CLK± pins inactive (set to AVDD or AGND).

Rev. C | Page 5 of 40 ADC AC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 2. AD6643-200 AD6643-250 Parameter1 Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) NSR Disabled fIN = 30 MHz 25°C 66.6 66.4 dBFS fIN = 90 MHz 25°C 66.5 66.2 dBFS Full 66.2 dBFS fIN = 140 MHz 25°C 66.4 66.1 dBFS fIN = 185 MHz 25°C 66.2 65.9 dBFS Full 65.3 dBFS fIN = 220 MHz 25°C 66.0 65.6 dBFS NSR Enabled 22% BW Mode fIN = 30 MHz 25°C 76.1 74.8 dBFS fIN = 90 MHz 25°C 76.1 74.5 dBFS Full 74.5 dBFS fIN = 140 MHz 25°C 75.5 74.2 dBFS fIN = 185 MHz 25°C 74.7 73.7 dBFS Full 72.6 dBFS fIN = 220 MHz 25°C 74.2 73.4 dBFS 33% BW Mode fIN = 30 MHz 25°C 76.1 72.3 dBFS fIN = 90 MHz 25°C 73.6 72.0 dBFS Full 72.0 dBFS fIN = 140 MHz 25°C 73.1 71.7 dBFS fIN = 185 MHz 25°C 72.6 71.2 dBFS Full 70.1 dBFS fIN = 220 MHz 25°C 72.1 70.9 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 30 MHz 25°C 65.6 65.4 dBFS fIN = 90 MHz 25°C 65.5 65.2 dBFS Full 65.1 dBFS fIN = 140 MHz 25°C 65.3 65.1 dBFS fIN = 185 MHz 25°C 65.1 64.9 dBFS Full 64.3 dBFS fIN = 220 MHz 25°C 64.9 64.6 dBFS WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −92 −90 dBc fIN = 90 MHz 25°C −91 −88 dBc Full −80 dBc fIN = 140 MHz 25°C −88 −86 dBc fIN = 185 MHz 25°C −88 −85 dBc Full −80 dBc fIN = 220 MHz 25°C −84 −85 dBc

Rev. C | Page 6 of 40 AD6643-200 AD6643-250 Parameter1 Temperature Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 92 90 dBc fIN = 90 MHz 25°C 91 88 dBc Full 80 dBc fIN = 140 MHz 25°C 88 86 dBc fIN = 185 MHz 25°C 88 85 dBc Full 79 dBc fIN = 220 MHz 25°C 84 85 dBc WORST OTHER HARMONIC OR SPUR fIN = 30 MHz 25°C −94 −94 dBc fIN = 90 MHz 25°C −94 −93 dBc Full −80 dBc fIN = 140 MHz 25°C −95 −92 dBc fIN = 185 MHz 25°C −94 −92 dBc Full −80 dBc fIN = 220 MHz 25°C −93 −88 dBc TWO TONE SFDR fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) 25°C 88 88 dBc CROSSTALK2 Full 95 95 dB FULL POWER BANDWIDTH3 25°C 1000 1000 MHz 1 For a complete set of definitions, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. 3 Full power bandwidth is the bandwidth for the ADC inputs at which the spectral power of the fundamental frequency is reduced by 3 dB. DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250 AVDD = 1.8 V , DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V Input Current Level High Full 10 22 µA Low Full −22 −10 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V Input Voltage Level High Full 1.2 AVDD V Low Full AGND 0.6 V

Rev. C | Page 7 of 40 Parameter Temperature Min Typ Max Unit Input Current Level High Full −5 +5 µA Low Full −100 +100 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ LOGIC INPUT (CSB)1 Input Voltage Level High Full 1.22 2.1 V Low Full 0 0.6 V Input Current Level High Full −5 +5 µA Low Full −80 −45 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK)2 Input Voltage Level High Full 1.22 2.1 V Low Full 0 0.6 V Input Current Level High Full 45 70 µA Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO)1 Input Voltage Level High Full 1.22 2.1 V Low Full 0 0.6 V Input Current Level High Full 45 70 µA Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUTS (OEB, PDWN)2 Input Voltage Level High Full 1.22 2.1 V Low Full 0 0.6 V Input Current Level High Full 45 70 µA Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD) ANSI Mode Full 250 350 450 mV Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS) ANSI Mode Full 1.15 1.25 1.35 V Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull up. 2 Pull down.

Rev. C | Page 8 of 40 SWITCHING SPECIFICATIONS Table 4. AD6643-200 AD6643-250 Parameter Symbol Temperature Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate1 Full 40 200 40 250 MSPS CLK Period—Divide-by-1 Mode2 tCLK Full 4.0 4 ns CLK Pulse Width High2 tCH Divide-by-2 Through Divide-by-8 Modes, DCS Enabled Full 0.8 0.8 ns DATA OUTPUT PARAMETERS (DATA, OR) 1.0 LVDS Mode 0.1 Data Propagation Delay2 tPD Full 6.0 6.0 ns DCO Propagation Delay2 tDCO Full 6.7 6.7 ns Pipeline Delay (Latency) Full 10 10 Cycles3 NSR Enabled Full 13 13 Cycles3 Aperture Delay4 tA Full 1.0 1.0 ns Aperture Uncertainty (Jitter)4 tJ Full 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 μs Wake-Up Time (from Power-Down) Full 250 250 μs OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 See Figure 2 for timing diagram. 3 Cycles refers to ADC input sample rate cycles. 4 Not shown in timing diagrams. TIMING SPECIFICATIONS—AD6643-200/AD6643-250 Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS See Figure 3 for timing details tSSYNC SYNC to the rising edge of CLK setup time 0.3 ns tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS See Figure 59 for SPI timing diagram tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 59) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 59) 10 ns

maximizing the thermal capability of the package. Table 7. Thermal Resistance 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 4 to 9, 11 to 14, 55, 56, 58 DNC Do Not Connect. Do not connect to these pins.

0 AGND,

must be connected to ground for proper operation. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 3 SYNC Input Digital Synchronization Pin. Slave mode only. 15 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 16 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 18 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 17 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 21 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 20 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 23 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 22 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 27 D4+ Output Channel A/Channel B LVDS Output Data 4—True.

Rev. C | Page 12 of 40 Pin No. Mnemonic Type Description 26 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 30 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 29 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 32 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 31 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 34 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 33 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 36 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 35 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 39 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 38 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 41 D10+ (MSB) Output Channel A/Channel B LVDS Output Data 10—True. 40 D10− (MSB) Output Channel A/Channel B LVDS Output Data 10—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. 44 SDIO Input/Output SPI Serial Data I/O. A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. 46 CSB Input Chip Select Bar (Active Low). CSB gates the read and write cycles. Output Enable Bar and Power-Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14).

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE

GROUND FOR PROPER OPERATION. Figure 5. Pin Configuration (Top View), LFCSP Channel Multiplexed (Even/Odd) LVDS Table 9. Pin Function Descriptions for the Channel Multiplexed (Even/Odd) LVDS Mode 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). AVDD Supply Analog Power Supply (1.8 V Nominal). DNC Do Not Connect. Do not connect to these pins.

0 AGND, Exposed

ground for proper operation. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 3 SYNC Input Digital Synchronization Pin. Slave mode only. is valid on the rising edge of the DCO. edge of the data clock output (DCO) from this output is always a Logic 0. the data clock output (DCO) from this output is always a Logic 0.

Rev. C | Page 14 of 40 Pin No. Mnemonic Type Description 13 B D1−/D2− Output Channel B LVDS Output Data 1/Data 2—Complement. 14 B D1+/D2+ Output Channel B LVDS Output Data 1/Data 2—True. 15 B D3−/D4− Output Channel B LVDS Output Data 3/Data 4—Complement. 16 B D3+/D4+ Output Channel B LVDS Output Data 3/Data 4—True. 17 B D5−/D6− Output Channel B LVDS Output Data 5/Data 6—Complement. 18 B D5+/D6+ Output Channel B LVDS Output Data 5/Data 6—True. 20 B D7−/D8− Output Channel B LVDS Output Data 7/Data 8—Complement. 21 B D7+/D8+ Output Channel B LVDS Output Data 7/Data 8—True. 22 B D9−/D10− (MSB) Output Channel B LVDS Output Data 9/Data 10—Complement. 23 B D9+/D10+ (MSB) Output Channel B LVDS Output Data 9/Data 10—True. 29 A 0/D0− (LSB) Output Channel B LVDS Output 0/Data 1—Complement. The first output bit from this output is always a Logic 0. 30 A 0/D0+ (LSB) Output Channel B LVDS Output 0/Data 1—True. The first output bit from this output is always a Logic 0. 31 A D1−/D2− Output Channel A LVDS Output Data 1/Data 0—Complement. 32 A D1+/D2+ Output Channel A LVDS Output Data 1/Data 0—True. 33 A D3−/D4− Output Channel A LVDS Output Data 3/Data 2—Complement. 34 A D3+/D4+ Output Channel A LVDS Output Data 3/Data 2—True. 35 A D5−/D6− Output Channel A LVDS Output Data 5/Data 4—Complement. 36 A D5+/D6+ Output Channel A LVDS Output Data 5/Data 4—True. 38 A D7−/D8− Output Channel A LVDS Output Data 7/Data 6—Complement. 39 A D7+/D8+ Output Channel A LVDS Output Data 7/Data 6—True. 40 A D9−/D10− (MSB) Output Channel A LVDS Output Data 9/Data 8—Complement. 41 A D9+/D10+ (MSB) Output Channel A LVDS Output Data 9/Data 8—True. 43 ORA+ Output Channel A LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 42 ORA− Output Channel A LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock (SCKL). The serial shift clock input, which is used to synchronize serial interface reads and writes. 44 SDIO Input/Output SPI Serial Data Input/Output (SDIO). A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. 46 CSB Input SPI Chip Select Bar (Active Low). An active low control that gates the read and write cycles. Output Enable Bar and Power-Down 47 OEB Input Output Enable Bar Input (Active Low). 48 PDWN Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14).

Figure 12. AD6643-200 Single Tone SNR/SFDR vs. Input Amplitude (AIN), fIN =

90.1 MHz

Figure 13. AD6643-200 Single Tone SNR/SFDR vs. Input Frequency (fIN) Figure 14. AD6643-200 Two Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 15. AD6643-200 Two Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 16. AD6643-200 Two Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 17. AD6643-200 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz

preceding samples. Sampling occurs on the rising edge of the clock. distortion (DPD) observation paths in telecommunication systems. but occurs at the expense of increased ADC noise and distortion. timing between multiple devices. using a 3-wire SPI-compatible serial interface. the sample capacitors and settling within 1/2 of a clock cycle. are dependent on the application. Figure 41. Switched Capacitor Input driving VIN+ and VIN− and differentially balance the inputs. The analog inputs of the AD6643 are not internally dc biased. is recommended for optimum performance.

proportionally shorter wake-up times. LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. should not exceed that supply voltage. after the rising edge of the clock signal. transients can degrade converter dynamic performance. clock rates below 40 MSPS, dynamic performance can degrade. graphical timing diagram of the AD6643 output modes. Table 11. Output Data Format

Rev. C | Page 28 of 40 CHANNEL/CHIP SYNCHRONIZATION The AD6643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, synchronize the SYNC input signal to the input clock signal. Drive the SYNC input using a single-ended CMOS type signal.

active low control that enables or disables the read and write cycles. Table 12. Serial Port Interface Pins synchronize serial interface reads and writes. turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. by the W0 bit and the W1 bit. change direction from an input to an output. at the appropriate point in the serial frame. to High Speed ADCs via SPI, available at www.analog.com. troller-Based Serial Port Interface (SPI) Boot Circuit. tioning at the converter inputs during critical sampling periods. functions supported on the AD6643.

Table 13. Features Accessible Using the SPI Figure 59. Serial Port Interface Timing Diagram

Rev. C | Page 31 of 40 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x20); and the digital feature control registers (Address 0x3A to Address 0x3E). The memory map register table (see Table 14) documents the default hexadecimal value for each hexadecimal address listed. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x05. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x20. The remaining registers, from Register 0x3A to Register 0x3E, are documented in the Memory Map Register Description section. Open Locations All address and bit locations that are not included in Table 14 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6643 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 14. Logic Levels An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Transfer Register Map Address 0x08 to Address 0x20, and Address 0x3A to Address 0x3E are shadowed. Writes to these addresses do not affect device operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Channel Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are desig- nated in Table 14 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 14 affect the entire device or the channel features where independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.

All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers

0 LSB

Rev. C | Page 33 of 40 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x0D Test mode (local) User test mode control 0 = continuous/ repeat pattern 1 = single pattern then zeros Open Reset PN long gen Reset PN short gen Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x00 When this register is set, the test data is placed on the output pins in place of normal data 0x10 Offset adjust (local) Open Open Offset adjust in LSBs from +31 to −32 (twos complement format) 0x00 0x14 Output mode Open Open Open Output disable (local) Open Output invert (local) 1 = normal (default) 0 = inverted Output format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved (local) 0x05 Configures the outputs and the format of the data 0x15 Output adjust (global) Open Open Open Open LVDS output drive current adjust 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved 0x01 0x16 Clock phase control (global) Invert DCO clock Open Odd/Even mode output enable 0 = disabled 1 = enabled Open Open Open Open Open 0x00 0x17 DCO output delay (global) Enable DCO clock delay Open Open DCO clock delay [delay = (3100 ps × register value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps 11110 = 3100 ps 11111 = 3200 ps 0x00 0x18 Input span select (global) Open Open Open Full-scale input voltage selection 01111 = 2.087 V p-p 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p 10000 = 1.383 V p-p 0x00 Full-scale input adjustment in

0.022 V steps

(global) User Test Pattern 1[7:0] 0x00 0x1A User Test Pattern 1 MSB (global) User Test Pattern 1[15:8] 0x00

Rev. C | Page 34 of 40 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x1B User Test Pattern 2 LSB (global) User Test Pattern 2[7:0] 0x00 0x1C User Test Pattern 2 MSB (global) User Test Pattern 2[15:8] 0x00 0x1D User Test Pattern 3 LSB (global) User Test Pattern 3[7:0] 0x00 0x1E User Test Pattern 3 MSB (global) User Test Pattern 3[15:8] 0x00 0x1F User Test Pattern 4 LSB (global) User Test Pattern 4[7:0] 0x00 0x20 User Test Pattern 4 MSB (global) User Test Pattern 4[15:8] 0x00 Digital Feature Control Registers 0x3A Sync control (global) Open Open Open Open Open Open Clock divider sync enable 0 = off 1 = on Master sync enable 0 = off 1 = on 0x00 Control register to synchronize the clock divider 0x3C NSR control (local) Open Open Open Open NSR mode 000 = 22% BW mode 001 = 33% BW mode NSR enable 0 = off 1 = on 0x00 Noise shaping requantizer (NSR) controls 0x3E NSR tuning word (local) Open Open NSR tuning word See the Noise Shaping Requantizer (NSR) section Equations for the tuning word are dependent on the NSR mode 0x1C NSR frequency tuning word 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.

Rev. C | Page 35 of 40 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x20, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, available at www.analog.com. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable buffer bit (Address 0x3A, Bit0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Buffer Enable Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used this bit should remain low to conserve power. NSR Control (Register 0x3C) Bits[7:4]—Reserved Bits[3:1]—NSR Mode Bits[3:1] determine the bandwidth mode of the NSR. When Bits[3:1] are set to 000, the NSR is configured for a 22% BW mode that provides enhanced SNR performance over 22% of the sample rate. When Bits[3:1] are set to 001, the NSR is con- figured for a 33% BW mode that provides enhanced SNR performance over 33% of the sample rate. Bit 0—NSR Enable The NSR is enabled when Bit 0 is high and disabled when Bit 0 is low. NSR Tuning Word (Register 0x3E) Bits[7:6]—Reserved Bits[5:0]—NSR Tu ni ng Word The NSR tuning word sets the band edges of the NSR band. In 22% BW mode, there are 57 possible tuning words; in 33% BW mode, there are 34 possible tuning words. For either mode, each step represents 0.5% of the ADC sample rate. For the equations that are used to calculate the tuning word based on the BW mode of operation, see the Noise Shaping Requantizer (NSR) section.

Rev. C | Page 36 of 40 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6643, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD6643, it is recommended that two separate 1.8 V supplies be used: one supply for analog (AVDD) and a separate supply for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the device using minimal trace length. A single PCB ground plane should be sufficient when using the AD6643. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD6643 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconduc- tive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, overlay a silkscreen to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). VCM Decouple the VCM pin to ground with a 0.1 μF capacitor, as shown in Figure 43. For optimal channel-to-channel isolation, a 33 Ω resistor should be included between the AD6643 VCM pin and the Channel A analog input network connection and between the AD6643 VCM pin and the Channel B analog input network connection. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter per- formance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6643 to keep these signals from transitioning at the converter inputs during critical sampling periods.

0.25 MIN

0.20 REF

7.50 REF

0.05 MAX

0.02 NOM

0.60 MAX

Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. C | Page 38 of 40 NOTES

Rev. C | Page 39 of 40 NOTES

Rev. C | Page 40 of 40 NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09638-0-11/12(C)