AD6640

AD6640 12 Bit, 65 MSPS IF Sampling A/D Converter Data Sheet, (Rev A)

Document overview

• Manufacturer or author: Analog Devices
• PDF pages: 24

Technical content

a 12-Bit, 65 MSPS IF Sampling A/D Converter

FEATURES

65 MSPS Minimum Sample Rate

80 dB Spurious-Free Dynamic Range IF Sampling to 70 MHz 710 mW Power Dissipation Single 5 V Supply On-Chip T/H and Reference Twos Complement Output Format

3.3 V or 5 V CMOS Compatible Output Levels

APPLICATIONS

Cellular/PCS Base Stations Multichannel, Multimode Receivers GPS Anti-Jamming Receivers Communications Receivers Phased Array Receivers FUNCTIONAL BLOCK DIAGRAM ADCATH3 DACADC TH2BUF TH1 MSB LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIGITAL ERROR CORRECTION LOGIC GND AIN AIN VREF ENCODE ENCODE 2.4V REFERENCE INTERNAL TIMING AVCC DVCC AD6640 GENERAL DESCRIPTION The AD6640 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on-chip to provide a complete conversion solution. The AD6640 runs on a single 5 V supply and provides CMOS compatible digital outputs at 65 MSPS. Specifically designed to address the needs of multichannel, multimode receivers, the AD6640 maintains 80 dB spurious- free dynamic range (SFDR) over a bandwidth of 25 MHz. Noise performance is also exceptional: typical signal-to-noise ratio is 68 dB. The AD6640 is built on Analog Devices’ high speed complemen- tary bipolar process (XFCB) and uses an innovative multipass architecture. Units are packaged in a 44-lead plastic quad flatpack (LQFP) specified from –40 °C to +85°C. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate is 65 MSPS. 2. Fully differential analog input stage specified for frequencies up to 70 MHz; enables IF sampling. 3. Low power dissipation: 710 mW off a single 5 V supply. 4. Digital outputs may be run on 3.3 V supply for easy interface to digital ASICs. 5. Complete solution: reference and track-and-hold. 6. Packaged in small, surface-mount 44-lead plastic LQFP. AD6640 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

Parameter Temp Level Min Typ Max Unit RESOLUTION 12 Bits ACCURACY No Missing Codes +25 °CI GUARANTEED Offset Error Full VI –10 +3.5 +10 mV Gain Error Full VI –10 +4.0 +10 % FS Differential Nonlinearity (DNL) 1 +25°CI –1.0 ± 0.5 +1.5 LSB Integral Nonlinearity (INL) 1 Full V ± 1.25 LSB TEMPERATURE DRIFT Offset Error Full V 50 ppm/ °C Gain Error Full V 100 ppm/ °C POWER SUPPLY REJECTION RATIO (PSRR) Full V ± 0.5 mV/V REFERENCE OUT (V REF)2 Full V 2.4 V ANALOG INPUTS (AIN, AIN)3 Analog Input Common-Mode Range 4 Full V V REF ± 0.05 V Differential Input Voltage Range Full V 2.0 V p-p Differential Input Resistance Full IV 0.7 0.9 1.1 k Ω Differential Input Capacitance +25 °CV 1.5 pF POWER SUPPLY Supply Voltage AVCC Full VI 4.75 5.0 5.25 V DVCC Full VI 3.0 3.3 5.25 V Supply Current IAVCC (AVCC = 5.0 V) Full VI 135 160 mA IDVCC (DVCC = 3.3 V) Full VI 10 20 mA POWER CONSUMPTION Full VI 710 865 mW NOTES 1ENCODE = 20 MSPS 2If VREF is used to provide a dc offset to other circuits, it should first be buffered. 3The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels V REF ± 0.5 V. The input signals should be 180 degrees out of phase to produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details. 4Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 17 for more detail). Specifications subject to change without notice . DIGITAL SPECIFICATIONS Test AD6640AST Parameter Temp Level Min Typ Max Unit LOGIC INPUTS (ENCODE, ENCODE)1 ENCODE Input Common-Mode Range 2 Full IV 0.2 2.2 V Differential Input Voltage Full IV 0.4 V p-p Single-Ended ENCODE 10 V p-p Logic Compatibility 3 TTL/CMOS Logic “1” Voltage Full VI 2.0 5.0 V Logic “0” Voltage Full VI 0 0.8 V Logic “1” Current (V INH = 5 V) Full VI +500 +650 +800 µA Logic “0” Current (V INL = 0 V) Full VI –400 –320 –200 µA Input Capacitance +25 °CV 2.5 pF LOGIC OUTPUTS ( D11–D0)4 Logic Compatibility CMOS Logic “1” Voltage (DV CC = 3.3 V) Full VI 2.8 DV CC – 0.2 V Logic “0” Voltage (DV CC = 3.3 V) Full VI 0.2 0.5 V Logic “1” Voltage (DV CC = 5.0 V) Full IV 4.5 DV CC – 0.3 V Logic “0” Voltage (DV CC = 5.0 V) Full IV 0.35 0.5 V Output Coding Twos Complement NOTES 1Best dynamic performance is obtained by driving ENCODE and ENCODE differentially. See Encoding the AD6640 section for more details. Performance versus ENCODE/ENCODE power is shown in TPC 12. 2For dc-coupled applications, the ENCODE input common-mode range specifies the common-mode range the ENCODE inputs can tolerate when driven differentially by the minimum differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value ensures that the input voltage on either encode pin does not go below 0 V. The maximum value ensures that the input voltage on either EN CODE pin does not go below 2.0 V or above 3ENCODE or ENCODE may be driven alone if desired, but performance will likely be degraded. Logic compatibility specifications are provided to sh ow that TTL or CMOS clock sources will work. When driving only one ENCODE input, bypass the complementary input to GND with 0.01 µF. 4Digital output load is one LCX gate. Specifications subject to change without notice. REV. A (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40 /H11543C, TMAX = +85/H11543C, unless otherwise noted.) –2– AD6640–SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40 /H11543C, TMAX = +85/H11543C, unless otherwise noted.)

Parameter (Conditions) Temp Level Min Typ Max Unit Maximum Conversion Rate Full VI 65 MSPS Minimum Conversion Rate 2 Full IV 6.5 MSPS Aperture Delay (tA) +25°CV 400 ps Aperture Uncertainty (Jitter) +25 °CV 0.3 ps rms ENCODE Pulsewidth High 3 +25°CI V 6.5 ns ENCODE Pulsewidth Low +25 °CI V 6.5 ns NOTES 1All switching specifications tested by driving ENCODE and ENCODE differentially. 2A plot of Performance versus ENCODE is shown in TPC 10. 3A plot of Performance versus Duty Cycle (ENCODE = 65 MSPS) is shown in TPC 11. 4Outputs driving one LCX gate. Delay is measured from differential crossing of ENCODE and ENCODE to the time when all output data bits are within valid logic levels. Specifications subject to change without notice. Test AD6640AST Parameter (Conditions) Temp Level Min Typ Max Unit SNR Analog Input 2.2 MHz +25 °CV 6 8 d B @ –1 dBFS 15.5 MHz +25 °CI 6 4 6 7 .7 dB 31.0 MHz +25 °CV 6 7 .5 dB

69.0 MHz +25 °CV 6 6 d B

Analog Input 2.2 MHz +25 °CV 6 8 d B @ –1 dBFS 15.5 MHz +25 °CI 63.5 67.2 dB 31.0 MHz +25 °CV 6 7 .0 dB 69.0 MHz +25 °CV 6 5 .5 dB Worst Harmonic2 (2nd or 3rd) Analog Input 2.2 MHz +25 °CV 8 0 dBc @ –1 dBFS 15.5 MHz +25 °CI 7 4 80 dBc 31.0 MHz +25 °CV 7 9 .5 dBc 69.0 MHz +25 °CV 7 8 .5 dBc Worst Harmonic2 (4th or Higher) Analog Input 2.2 MHz +25 °CV 8 5 dBc @ –1 dBFS 15.5 MHz +25 °CI 7 4 85 dBc

31.0 MHz +25 °CV 8 5 dBc

69.0 MHz +25 °CV 8 4 dBc

Multitone SFDR (with Dither) 3 Eight Tones @ –20 dBFS Full V 90 dBFS Two-Tone IMD Rejection 4 F1, F2 @ –7 dBFS Full V 80 dBc Analog Input Bandwidth 5 +25°CV 300 MHz NOTES 1All ac specifications tested by driving ENCODE and ENCODE differentially. 2For a single test tone at –1 dBFS, the worst-case spectral performance is typically limited by the direct or aliased second or third harmonic. If a system is designed such that the second and third harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst harmonic (fourth or higher) includes fourth and higher order harmonics and all other spurious components. Reference TPC 6 for more detail. 3See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tone s from 14 MHz to 18 MHz (0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR. 4F1 = 14.9 MHz, F2 = 16 MHz. 5Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in TPCs 4, 5, and 6. Sampling wide bandwidths (5 MHz–15 MHz) should be limited to 70 MHz center frequency. Specifications subject to change without notice. REV. A –3– (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40 /H11543C, TMAX = +85/H11543C, unless otherwise noted.) (AVCC = +5 V, DVCC = +3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40 /H11543C, TMAX = +85/H11543C, unless otherwise noted.) SWITCHING SPECIFICATIONS1 AC SPECIFICATIONS1 AD6640

–4– REV. A ABSOLUTE MAXIMUM RATINGS 1 Parameter Min Max Unit ELECTRICAL AVCC Voltage 0 7 V DVCC Voltage 0 7 V Analog Input Voltage 0 AV CC V Analog Input Current 25 mA Digital Input Voltage (ENCODE) 0 5 V Digital Output Current –10 +10 mA ENVIRONMENTAL2 Operating Temperature Range (Ambient) –40 +85 °C Maximum Junction Temperature 150 °C Lead Temperature (Soldering, 10 sec) 300 °C Storage Temperature Range (Ambient) –65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances (44-lead LQFP); θJA = 55°C/W. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6640AST –40 °C to +85°C (Ambient) 44-Lead Plastic Quad Flatpack (LQFP) ST-44 AD6640ST/PCB Evaluation Board with AD6640AST EXPLANATION OF TEST LEVELS Test Level I– 100% production tested. II – 100% production tested at +25 °C and sample tested at specified temperatures. AC testing done on sample basis. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V– Parameter is a typical value only. VI – All devices are 100% production tested at +25°C; sample tested at temperature extremes. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6640 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. A PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 2, 36, 37, 40, 41 DV CC 3.3 V/5 V Power Supply (Digital). Powers output stage only. 3 ENCODE Encode Input. Data conversion initiated on rising edge. 4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode. See Encoding the AD6640 section. 5, 6, 13, 14, 17, 18, 21, GND Ground 22, 24, 34, 35, 38, 39

7 AIN Analog Input

8 AIN Complement of Analog Input

REF Internal Voltage Reference. Nominally 2.4 V. Bypass to ground with 0.1 µF + 0.01 µF microwave chip capacitor. 10 C1 Internal Bias Point. Bypass to ground with 0.01 µF capacitor. 11, 12, 15, 16, 19, 20 AV CC 5 V Power Supply (Analog)

23 NC No Connect

25 D0 (LSB) Digital Output Bit (Least Significant Bit)

26–33 D1–D8 Digital Output Bits 42, 43 D9–D10 Digital Output Bits

44 D11 (MSB)* Digital Output Bit (Most Significant Bit)

*Output coded as twos complement. PIN CONFIGURATION 40 39 3841424344 36 35 34 37 12 13 14 15 16 17 18 19 20 21 22 PIN 1 TOP VIEW (Not to Scale) AVCC AVCC AVCC AVCC AVCC AD6640 DVCC DVCC ENCODE ENCODE GND GND AIN NC = NO CONNECT VREF AVCC D0 (LSB) GND NC D11 (MSB) GND GND GND GND D10 GND GND GND GND GND DV CC DVCC DVCC DVCC GND AIN

–6– REV. A DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. Integral Nonlinearity The deviation of the transfer function from a reference line mea- sured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The ENCODE rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The ENCODE rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Worst Harmonic The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc.

–8– REV. A –Typical Performance Characteristics FREQUENCY – MHz 100 dc 32.5 POWER RELATIVE TO ADC FULL SCALE – dB 6.5 13.0 19.5 26.0 120 ENCODE = 65MSPS AIN = 2.2MHz 4 8 9537 62 TPC 1. Single Tone at 2.2 MHz FREQUENCY – MHz 100 dc 32.5 POWER RELATIVE TO ADC FULL SCALE – dB 6.5 13.0 19.5 26.0 120 ENCODE = 65MSPS AIN = 15.5MHz 48 95 37 62 TPC 2. Single Tone at 15.5 MHz FREQUENCY – MHz 100 dc 32.5 POWER RELATIVE TO ADC FULL SCALE – dB 6.5 13.0 19.5 26.0 120 ENCODE = 65MSPS AIN = 31.0MHz 48 95 3 762 TPC 3. Single Tone at 31.0 MHz ANALOG INPUT FREQUENCY – MHz 07 0 7 WORST CASE HARMONIC – dBc 14 21 28 35 42 49 56 63 T = +25 C T = –40 C, +85 C ENCODE = 65MSPS TEMP = –40 C, +25 C, and +85 C TPC 4. Harmonics vs. AIN ANALOG INPUT FREQUENCY – MHz 07 0 7 SNR – dB 14 21 28 35 42 49 56 63 ENCODE = 65MSPS TEMP = –40 C, +25 C, and +85 C T = +25 C T = –40 C T = +85 C TPC 5. Noise vs. AIN ENCODE = 65MSPS ANALOG INPUT FREQUENCY – MHz 1 10010 SNR, HARMONICS – dB, dBc 24 2 0 40 200 300 WORST OTHER SPUR HARMONICS (SECOND, THIRD) SNR TPC 6. Harmonics, Noise vs. AIN

–9–REV. A FREQUENCY – MHz 100 dc 32.5 POWER RELATIVE TO ADC FULL SCALE – dB 6.5 13.0 19.5 26.0 120 ENCODE = 65MSPS AIN = 15.0MHz, 16.0MHz NO DITHER TPC 7. Two Tones at 15.0 MHz and 16.0 MHz ANALOG INPUT POWER LEVEL – dBFS 100 –80 0 –70 WORST CASE SPURIOUS – dBc and dBFS ENCODE = 65MSPS AIN = 31.0MHz dBFS dBc SFDR = 80dB REFERENCE LINE TPC 8. Single Tone SFDR INPUT POWER LEVEL (F1 = F2) – dBFS 100 –80 0 –70 WORST CASE SPURIOUS – dBc and dBFS ENCODE = 65MSPS F1 = 15.0MHz F2 = 16.0MHz SFDR = 80dB REFERENCE LINE dBFS dBc TPC 9. Two Tone SFDR SAMPLE RATE – MSPS dc 80 8 SNR, WORST CASE SPURIOUS – dB, dBc 16 24 32 40 48 56 64 72 AIN = 19.5MHz SNR WORST SPUR TPC 10. SNR, Worst Spurious vs. ENCODE ENCODE DUTY CYCLE – % 25 75 30 SNR, WORST FULL-SCALE SPURIOUS – dB, dBc 35 40 45 50 55 60 65 70 ENCODE = 65MSPS AIN = 2.2MHz WORST SPUR SNR TPC 11. SNR, Worst Spurious vs. Duty Cycle ENCODE POWER – dBm –15 15–12 SNR, WORST FULL-SCALE SPURIOUS – dB, dBc –9 –6 –3 0 3 6 9 12 ENCODE = 65MSPS WORST SPUR SNR 2.2MHz 2.2MHz 69MHz 69MHz TPC 12. SNR, Worst Spurious vs. ENCODE Power

–10– REV. A dc –80 –120 –40 –100 –20 –60 POWER RELATIVE TO ADC FULL SCALE – dB ENCODE = 65MSPS AIN = 19.5MHz @ –36dBFS NO DITHER FREQUENCY – MHz TPC 13. 16K FFT without Dither ANALOG INPUT POWER LEVEL – dBFS 100 –80 0 –70 WORST CASE SPURIOUS – dBc ENCODE = 65MSPS AIN = 19.5MHz NO DITHER SFDR = 80dB REFERENCE LINE TPC 14. SFDR without Dither –80 –120 –40 –100 –20 –60 POWER RELATIVE TO ADC FULL SCALE – dB ENCODE = 50MSPS AIN = 65.5MHz, 68.5MHz NO DITHER –90 –120 –30 –60 50 7555 60 70 FREQUENCY – MHz ALIASED SIGNALS ANALOG IF FILTER MASK TPC 15. IF Sampling at 70 MHz without Dither –80 –120 –40 –100 –20 –60 POWER RELATIVE TO ADC FULL SCALE – dB ENCODE = 65MSPS AIN = 19.5MHz @ –36dBFS DITHER = –32.5dBm FREQUENCY – MHz TPC 16. 16K FFT with Dither ANALOG INPUT POWER LEVEL – dBFS 100 –80 0 –70 WORST CASE SPURIOUS – dBc ENCODE = 65MSPS AIN = 19.5MHz DITHER = –32.5dBm SFDR = 80dB REFERENCE LINE TPC 17. SFDR with Dither 50 75 55 60 65 70 FREQUENCY – MHz –80 –120 –40 –100 –20 –60 POWER RELATIVE TO ADC FULL SCALE – dB ENCODE = 50MSPS AIN = 65.5MHz, 68.5MHz DITHER = –32.5dBm –60 –90 –120 –30 ANALOG IF FILTER MASK ALIASED SIGNALS TPC 18. IF Sampling at 70 MHz with Dither

previously in this data sheet. Power to the analog supply pins is connected via banana jacks. digital supply connection also powers the digital gates on the PCB. that U5 requires TTL levels to function properly. capacitive input of the ADC. Figure 17. DC-Coupled Analog Input Circuit closely to the package as possible using 0.1µF chip capacitors. for DVCC = 3.3 V as this is a common supply for digital ASICs. resistor (e.g., 348 Ω) followed by a gate like the 74 LCX574. switching currents of the AD6640.

–14– REV. A AD6640 output data is latched using 74LCX574 (U3, U4) latches following 348 Ω series resistors. The resistors limit the current that would otherwise flow due to the digital output slew rate. The resistor value was chosen to represent a time constant of ~25% of the data rate at 65 MHz. This reduces slew rate while not appreciably distorting the data waveform. Data is latched in a pipeline configuration; a rising edge generates the new AD6640 data sample, latches the previous data at the con- verter output, and strobes the external data register over J3. Note that power and ground must be applied to J3 to power the digital logic section of the evaluation board. Table I. AD6640ST/PCB Bill of Material Item Quantity Reference Description 12 +5 VA, GND Banana Jack 21 1C 7–C9, C11–C17, C19 Ceramic Chip Capacitor 0805, 0.1 µF

32 C4, C6 Tantalum Chip Capacitor 10 µF

41 J3 40-Lead Double Row Male Header

53 J1, J2, J4 BNC Coaxial PCB Connector

61 R1 Surface Mount Resistor 1206, 348 Ω

72 5R 2–R14, R20–R25, R30–R35 Surface Mount Resistor 1206, 348 Ω

81 R15 Surface Mount Resistor 1206, 100 Ω

91 R16 Surface Mount Resistor 1206, 270 Ω

10 2 T1, T2 Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio 11 1 U1 Clock Oscillator (Optional) 12 1 DUT AD6640AST 12-Bit–65 MSPS A/D Converter 13 2 U3, U4 74LCX574 Octal Latch 14 1 U5 74LVQ00 Quad Two Input NAND Gate 15 1 C1, C18 Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance 16 2 C2, C3 Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance 17 2 CR1, CR2 1N2810 Schottky Diode DIGITAL WIDEBAND RECEIVERS Introduction Several key technologies are now being introduced that may forever alter the vision of radio. Figure 25 shows the typical dual conversion superheterodyne receiver. The signal picked up by the antenna is mixed down to an intermediate frequency (IF) using a mixer with a variable local oscillator (LO); the variable LO is used to “tune-in” the desired signal. This first IF is mixed down to a second IF using another mixer stage and a fixed LO. Demodulation takes place at the second or third IF using either analog or digital techniques.

Figure 18. AD6640ST/PCB Schematic

The signal-to-noise ratio (SNR) for an ADC can be predicted. processing gain is accomplished using the channelizer chips. reduction is accomplished through a process called decimation. then the decimation rate is 52. process gains through proprietary noise reduction algorithms. better wafer yields meaning lower cost and much lower power. the AD6640, the repetitive cycle is every 15.625 mV p-p. errors, the full effect will only be gained with this larger dither. injection of dither (see TPC 14). Figure 30. Noise Source (Dither Generator) generated, the signal must be introduced to the receiver strip. after the last down conversion as shown in Figure 31.

a channelizer chip such as the AD6620 will yield even better SNR. point for the drive amplifier can be calculated. much the same manner that a mixer will down-convert a signal. may be used to determine the final frequency after aliasing. some cases, the elimination of two IF stages is possible. Figure 33. IF Sampling a 201 MHz Input and AD6620 channelizers allows for a very competitive solution. allow for the electronic beam to form on the receive antennas. with analog or traditional radios, the system grows quite rapidly. With a multicarrier receiver, however, the design is quite compact.

32 AD6620 channelizers, which are phase locked in groups of

with traditional receiver designs.

32 CHANNELS OUT

Figure 34. Receive Chain for a Phased-Array Cellular Base Station with Eight Antennas and 32 Channels

–24– REV. A C00970–0–2/03(A) PRINTED IN U.S.A. OUTLINE DIMENSIONS 44-Lead Plastic Quad Flatpack [LQFP] (ST-44) Dimensions shown in millimeters VIEW A7/H11543 3.5/H11543 0/H11543 0.20 0.09 1.45 1.40 1.35 0.15 0.05

0.10 MAX

(PINS DOWN) 44 34 2212 0.80 BSC

12.00 BSC

10.00 BSC

1.60 MAX

0.75 0.60 0.45 0.45 0.37 0.30 COMPLIANT TO JEDEC STANDARDS MS-026BCB

Revision History

2/03—Data Sheet changed from REV. 0 to REV. A.