AD6636BBCZ1

AD6636 AD | Alldatasheet

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Technical content

150 MSPS Wideband

Digital Down-Converter (DDC) AD6636 Rev. 0 Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

4/6 independent wideband processing channels Processes 6 wideband carriers (UMTS, CDMA2000) 4 single-ended or 2 LVDS parallel input ports (16 linear bit plus 3-bit exponent) running at 150 MHz Supports 300 MSPS input using external interface logic 3 16-bit parallel output ports operating up to 200 MHz Real or complex input ports Quadrature correction and dc correction for complex inputs Supports output rate up to 34 MSPS per channel RMS/peak power monitoring of input ports Programmable attenuator control for external gain ranging 3 programmable coefficient FIR filters per channel 2 decimating half-band filters per channel 6 programmable digital AGC loops with 96 dB range Synchronous serial I/O operation (SPI®-, SPORT-compatible) Supports 8-bit or 16-bit microport modes 3.3 V I/O, 1.8 V CMOS core User-configurable built-in self-test (BIST) capability JTAG boundary scan

APPLICATIONS

Multicarrier, multimode digital receivers GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA Micro and pico cell systems, software radios Broadband data applications Instrumentation and test equipment Wireless local loop In-building wireless telephony FUNCTIONAL BLOCK DIAGRAM INPUT MATRIX CMOS REAL PORTS A, B, C,D CMOS COMPLEX PORTS (AI, AQ) (BI, BQ) LVDS PORTS AB, CD PEAK/ RMS MEAS. I,Q CORR. SYNC [3:0] RESET DATA ROUTER MATRIX DATA ROUTING AGC PARALLEL PORTS 16-BIT MICROPORT INTERFACE SPORT/SPI INTERFACE JTAGPLL CLOCK MULTIPLIER FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 PA PB PC ADC B/AQ CLKB EXPB [2:0] ADC A/AI CLKA EXPA [2:0] ADC D/CQ CLKD EXPD [2:0] ADC C/CI CLKC EXPC [2:0] M = DECIMATION L = INTERPOLATIONARE AVAILABLE ONLY IN 6-CHANNEL PART 04998-0-001NOTE: CHANNELS RENDERED AS Figure 1.

Rev. 0 | Page 2 of 72 TABLE OF CONTENTS

REVISION HISTORY

8/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 72 PRODUCT DESCRIPTION The AD6636 is a digital down-converter intended for IF sampling or oversampled baseband radios requiring wide- bandwidth input signals. Optimized for the demanding filtering requirements of wideband standards, such as CDMA2000, UMTS, and TD-SCDMA, the AD6636 is designed for radio systems that use either an IF sampling ADC or a baseband sampling ADC. The AD6636 channels have the following signal processing stages: a frequency translator, a fifth-order cascaded integrated comb filter, two sets of cascaded fixed-coefficient FIR and half- band filters, three cascaded programmable coefficient sum-of- product FIR filters, an interpolating half-band filter (IHB), and a digital automatic gain control (AGC) block. Multiple modes are supported for clocking data into and out of the chip and provide flexibility for interfacing to a wide variety of digitizers. Programming and control are accomplished via serial or microport interfaces. Input ports can take input data at up to 150 MSPS. Up to

300 MSPS input data can be supported using two input ports

(some external interface logic is required) and two internal channels processing in tandem. Biphase filtering in output data router is selected to complete the combined filtering mode. The four input ports can operate in CMOS mode, or two ports can be combined for LVDS input mode. The maximum input data rate for each input port is 150 MHz. Frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (NCO). It has greater than 110 dBc SDFR. This stage translates either a real or complex input signal from IF (intermediate frequency) to a baseband complex digital output. Phase and amplitude dither can be enabled on-chip to improve spurious performance of the NCO. A 16-bit phase-offset word is available to create a known phase relationship between multiple AD6636 chips or channels. The NCO also can be bypassed so that baseband I and Q inputs can be provided directly from baseband sampling ADC through input ports. Following frequency translation is a fifth-order CIC filter with a programmable decimation between 1 and 32. This filter is used to lower the sample rate efficiently, while providing sufficient alias rejection at frequencies with higher frequency offsets from the signal of interest. Following the CIC5 are two sets of filters. Each set has a non- decimating FIR filter and a decimate-by-2 half-band filter. The FIR1 filter provides about 30 dB of rejection, while the HB1 filter provides about 77 dB of rejection. They can be used together to achieve a 107 dB stopband alias rejection, or they can be individually bypassed to save power. The FIR2 filter provides about 30 dB of rejection, while the HB2 filter provides about 65 dB of rejection. The filters can be used either together to achieve more than 95 dB stopband alias rejection, or can be individually bypassed to save power. FIR1 and HB1 filters can run with a maximum input rate of 150 MSPS. In contrast, FIR2 and HB2 can run with a maximum input rate of 75 MSPS (input rate to FIR2 and HB2 filters). The programmable filtering is divided into three cascaded RAM coefficient filters (RCFs) for flexible and power efficient filtering. The first filter in the cascade is the MRCF, consisting of a programmable nondecimating FIR. It is followed by programmable FIR filters (DRCF) with decimation from 1 to 16. They can be used either together to provide high rejection filters, or independently to save power. The maximum input rate to the MRCF is one-fourth of PLL clock rate. The CRCF (Channel RCF) is the last programmable FIR filter with programmable decimation from 1 to 16. It typically is used to meet the spectral mask requirements for the air standard of interest. This could be an RRC, anti-aliasing filter or any other real data filter. Decimation in preceding blocks is used to keep the input rate of this stage as low as possible for the best filter performance. The last filter stage in the chain is an interpolate-by-2 half-band filter, which is used to up-sample the CRCF output to produce higher output oversampling. Signal rejection requirements for this stage are relaxed because preceding filters already have filtered the blockers and adjacent carriers. Each input port of the AD6636 has its own clock used for latching onto the input data, but Input Port A clock (CLKA) is used also as the input for an on-board PLL clock multiplier. The output of the PLL clock is used for processing all filters and processing blocks beyond the data router following CIC filter. The PLL clock can be programmed to have a maximum clock rate of 200 MHz. A data routing block (DR) is used to distribute data from the CICs to the various channel filters. This block allows multiple back end filter chains to work together to process high bandwidth signals or to make even sharper filter transitions than a single channel can perform. It also can allow complex filtering operations to be achieved in the programmable filters. The digital AGC provides the user with scaled digital outputs based on the rms level of the signal present at the output of the digital filters. The user can set the requested level and time constant of the AGC loop for optimum performance of the postprocessor. This is a critical function in the base station for CDMA applications where the power level must be well controlled going into the RAKE receivers. It has programmable clipping and rounding control to provide different output resolutions.

Rev. 0 | Page 4 of 72 The overall filter response for the AD6636 is the composite of all the combined filter stages. Each successive filter stage is capable of narrower transition bandwidths, but requires a greater number of CLK cycles to calculate the output. More decimation in the first filter stage minimizes overall power consumption. Data from the device is interfaced to a DSP/FPGA/baseband processor via either high speed parallel ports (preferred) or a DSP-compatible microprocessor interface. The AD6636 is available both in 4-channel and 6-channel versions. The data sheet primarily discusses the 6-channel part. The only difference between the 6-channel and 4-channel devices is that on the 4-channel version, Channels 4 and 5 are not available (see Figure 1). The 4-channel device still has the same input ports, output ports, and memory map. The memory map section for Channels 4 and 5 can be programmed and read back, but it serves no purpose. PRODUCT HIGHLIGHTS

• Six independent digital filtering channels
• 101 dB SNR noise performance, 110 dB spurious performance
• Four input ports capable of 150 MSPS input data rates
• RMS/peak power monitoring of input ports and 96 dB range AGCs before the output ports
• Three programmable RAM coefficient filters, three half- band filters, two fixed coefficient filters, and one fifth-order CIC filter per channel
• Complex filtering and biphase filtering (300 MSPS ADC input) by combining filtering capability of multiple channels
• Three 16-bit parallel output ports operating at up to

200 MHz clock

• Blackfin®- and TigerSHARC®-compatible 16-bit microprocessor port
• Synchronous serial communications port is compatible with most serial interface standards, SPORT, SPI, and SSR

Rev. 0 | Page 5 of 72 SPECIFICATIONS Table 1. Recommended Operating Conditions

ELECTRICAL CHARACTERISTICS

Table 2. Electrical Characteristics1 1 One input port, all six channels, and the relevant signal processing blocks are active. 2 PLL is turned off for power savings.

Table 3. General Timing Characteristics1, 2 2 CLOAD = 40 pF on all outputs, unless otherwise noted.

Table 4. Microport Timing Characteristics1, 2 2 CLOAD = 40 pF on all outputs, unless otherwise noted. 3 Specification pertains to control signals: R/W (WR), DS (RD), and CS.

Table 5. Serial Port Timing Characteristics1, 2 2 CLOAD = 40 pF on all outputs, unless otherwise noted. II 100% production tested at 25°C, and sample tested at specified temperatures. IV Parameter guaranteed by design and analysis. V Parameter is typical value only. VI 100% production tested at 25°C, and sampled tested at temperature extremes.

Rev. 0 | Page 9 of 72 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating ELECTRICAL VDDCORE Supply Voltage (Core Supply) 2.2 V VDDIO Supply Voltage (Ring or IO Supply) 4.0 V Input Voltage −0.3 to +3.6 V (not 5 V tolerant) Output Voltage −0.3 to VDDIO + 0.3 V Load Capacitance 200 pF ENVIRONMENTAL Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature under Bias 125°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 256-ball CSP_BGA package: θJA = 25.4°C /W, no airflow θJA = 23.3°C /W, 0.5 m/s airflow θJA = 22.6°C /W, 1.0 m/s airflow θJA = 21.9°C /W, 2.0 m/s airflow Thermal measurements made in the horizontal position on a 4-layer board with vias. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. CSP_BGA Pin Configuration Table 7. Pin Names and Functions VDDCORE Power See Table 8 1.8 V Digital Core Supply. VDDIO Power See Table 8 3.3 V Digital I/O Supply. GND Ground See Table 8 Digital Core and I/O Ground. this clock is used to drive internal circuitry and PLL clock multiplier. CLKB Input L1 Clock for Input Port B. Used to clock INB[15:0] and EXPB[2:0] data. CLKC Input A6 Clock for Input Port C. Used to clock INC[15:0] and EXPC[2:0] data. CLKD Input A5 Clock for Input Port D. Used to clock IND[15:0] and EXPD[2:0] data. INA[0:15] Input See Table 8 Input Port A (Parallel). INB[0:15] Input See Table 8 Input Port B (Parallel). INC[0:15] Input See Table 8 Input Port C (Parallel). IND[0:15] Input See Table 8 Input Port D (Parallel). EXPA[0:2] Bidirectional E3, C1, G5 Exponent Bus Input Port A. Gain control output. EXPB[0:2] Bidirectional D1, F3, G4 Exponent Bus Input Port B. Gain control output. EXPC[0:2] Bidirectional F4, D3, D2 Exponent Bus Input Port C. Gain control output. EXPD[0:2] Bidirectional D4, C2, F5 Exponent Bus Input Port D. Gain control output. CLKA, CLKB Input K1, L1 LVDS Differential Clock for LVDS_A Input Port (LVDS_CLKA+, LVDS_CLKA−).

Rev. 0 | Page 11 of 72 Name Type Pin No. Function CLKC, CLKD Input A6, A5 LVDS Differential Clock for LVDS_C Input Port (LVDS_CLKC+, LVDS_CLKC−). INA[0:15], INB[0:15] LVDS Input See Table 8 In LVDS input mode, INA[0 :15] and INB[0 :15] form a differential pair LVDS_A+[0:15] (positive node) and LVDS_A–[0:15] (negative node), respectively. INC[0:15], IND[0:15] LVDS Input See Table 8 In LVDS input mode, INC[0 :15] and IND[0 :15] form a differential pair LVDS_C+[0:15] (positive node) and LVDS_C–[0:15] (negative node), respectively. OUTPUT PORTS PCLK Bidirectional E16 Parallel Output Port Clock. Master mode output, Slave mode input. PA[0:15] Output See Table 8 Parallel Output Port A Data Bus. PACH[0:2] Output G15, D16, H12 Channel Indicator Output Port A. PAIQ Output H13 Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus. PAGAIN Output G13 Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PAACK Input H14 Parallel Port A Acknowledge (Active High). PAREQ Output F15 Parallel Port A Request (Active High). PB[0:15] Output See Table 8 Parallel Output Port B Data Bus. PBCH[0:2] Output C13, D11, B14 Channel Indicator Output Port B. PBIQ Output D12 Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus. PBGAIN Output A14 Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PBACK Input E12 Parallel Port B Acknowledge (Active High). PBREQ Output E11 Parallel Port B Request (Active High). PC[0:15] Output See Table 8 Parallel Output Port C Data Bus. PCCH[0:2] Output M15, L14, N15 Channel Indicator Output Port C. PCIQ Output P15 Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus. PCGAIN Output P16 Parallel Port C Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PCACK Input L13 Parallel Port C Acknowledge (Active High). PCREQ Output R16 Parallel Port C Request (Active High). MISC PINS RESET Input P3 Master Reset (Active Low). IRP Output T2 Interrupt Pin. SYNC[0:3] Input B12, A12, C10, B11 Synchronization Inputs. SYNC pins are independent of channels or input ports and independent of each other. LVDS_RSET Input E4 LVDS Resistor Set Pin (Analog Pin). See Design Notes. EXT_FILTER Input R4 PLL Loop Filter (Analog Pin). See Design Notes. MICROPORT CONTROL D[0:15] Bidirectional See Table 8 Bidirectional Microport Data. This bus is three-stated when CS is high. A[0:7] Input See Table 8 Microport Address Bus. DS(RD) Input P4 Active Low Data Strobe when MODE = 1. Active Low Read Strobe when MODE = 0. DTACK (RDY)1 Output M6 Active Low Data Acknowledge when MODE = 1. Microport Status Pin when MODE = 0. R/W (WR) Input N4 Read/Write Strobe when MODE = 1. Active Low Write Strobe when MODE = 0. MODE Input T3 Mode Select Pin. When SMODE = 0: Logic 0 = Intel mode; Logic 1 = Motorola mode. When SMODE = 1: Logic 0 = SPI mode; Logic 1 = SPORT mode. CS Input N5 Active Low Chip Select. Logic 1 three-states the microport data bus. CPUCLK Input R1 Microport CLK Input (Input Only). CHIPID[0:3] Input T4, R5, N6, P6 Chip ID Input Pins.

Rev. 0 | Page 12 of 72 Name Type Pin No. Function SERIAL PORT CONTROL SCLK Input R1 Serial Clock. SDO Output M6 Serial Port Data Output. SDI2 Input N11 Serial Port Data Input. STFS Input N4 Serial Transmit Frame Sync. SRFS Input P4 Serial Receive Frame Sync. SCS Input N5 Serial Chip Select. MSB_FIRST Input R3 Select MSB First into SDI Pin and MSB First Out of SDO Pin. Logic 0 = MSB first; Logic 1 = LSB first. SMODE Input P5 Serial Mode Select. Pull high when serial port is used and low when microport is used. JTAG TRST1 Input B13 Test Reset Pin. Pull low when JTAG is not used. TCLK2 Input C12 Test Clock. TMS1 Input C11 Test Mode Select. TDO Output A13 Test Data Output. Three-stated when JTAG is in reset. TDI1 Input D10 Test Data Input. 1 Pin with a pull-up resistor of nominal 70 kΩ. 2 Pin with a pull-down resistor of nominal 70 kΩ. PIN LISTING FOR POWER, GROUND, DATA AND ADDRESS BUSES Table 8. Name Pin No. VDDCORE A9, G6, G11, H1, H6, H11, J6, J11, J16, K6, K11, T8 VDDIO B2, B15, F7, F8, F9, F10, L7, L8, L9, L10, R2, R15 GND A1, A8, A16, E5, F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, H16, J1, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11, M5, P7, T1, T9, T10, T15, T16 INA[0:15] N3, P2, P1, N2, N1, M1, L2, K3, K2, J2, H2, G1, F1, F2, E1, E2 INB[0:15] M4, L4, M3, L5, L3, M2, K4, K5, J4, J5, J3, H4, H3, G2, H5, G3 INC[0:15] C3, C4, B3, A2, D6, C6, E7, D7, E8, D8, C8, E9, D9, C9, B10, E10 IND[0:15] B1, E6, D5, C5, A3, B4, B5, A4, B6, C7, B7, A7, B8, B9, A10, A11 PA[0:15] F16, H15, G16, J12, J15, J14, K16, J13, K15, K14, L16, M16, K12, L15, N16, K13 PB[0:15] F13, E15, G14, G12, E13, E14, F12, F14, C14, D14, C16, A15, B16, D15, D13, C15 PC[0:15] M14, N14, M13, L12, P14, N13, R14, M12, T14, R13, P13, P12, M11, T13, T12, N12 A[0:7] N11, R12, P11, R11, N10, M10, P10, T11

Figure 23. Typical Interconnection of the AD6645 Fixed-Point ADC Table 9. Weighting Factors for Different Exp[2:0] Values real individual input ports. paired with Input Port D to receive I and Q data, respectively. 25 of ADC input control register. Input Port A, and the complex input bit should be selected. C and D, EXPC[2:0] are output. differential pair LVDS_CLKC+ and LVDS_CLKC− pins. clock multiplier to provide a higher clock rate to the RCF filters. as an input to the PLL clock multiplier.

1 FOR BYPASS

Figure 24. PLL Clock Generation

(output) of as high as 200 MHz. CLKA is the Input Port A clock rate. M is a 5-bit programmable multiplication factor. the ADC clock control register, as listed in Table 10. Table 10. PLL Clock Generation Predivider Control

00 Divide-by-1, bypass

01 Divide-by-2

10 Divide-by-4

11 Divide-by-8

programmable dwell-time counter for temporal hysteresis. Each input port has a 3-bit output from the gain control block. pins are set, by default, as input exponent pins. control output is decremented immediately to prevent overflow. the dynamic range of the input signal into the ADC by 6.02 dB. that the gain-ranging block can support it. only change is the increase in the dynamic range of the ADC.

settling delays are compensated for in the AD6636. provide temporal hysteresis. with the settling delay in the external gain ranging circuitry. and EXPB[2:0] is forced to be equal to EXP[2:0]. Figure 25. AD6636 Gain Control Block Diagram

• Peak power
• Mean power
• Number of samples crossing a threshold These functions are controlled via the 2-bit power-monitor function select bits of the power monitor control register for each individual input port. The input ports can be set for different modes, but only one function can be active at a time for any given input port. The three modes of operation can function continuously over a programmable time period. This time period is programmed as the number of input clock cycles in a 24-bit ADC monitor period register (AMPR). This register is separate for each input port. An internal magnitude storage register (MSR) is used to monitor, accumulate, or count, depending on the mode of operation. Peak Detector Mode (Control Bits 00) The magnitude of the input port signal is monitored over a programmable time period (given by AMPR) to give the peak value detected. This mode is set by programming Logic 0 in the power-monitor function select bits of the power-monitor control register for each individual input port. The 24-bit AMPR must be programmed before activating this mode. After enabling this mode, the value in the AMPR is loaded into a monitor period timer and the countdown is started. The magnitude of the input signal is compared to the MSR, and the greater of the two is updated back into the MSR. The initial value of the MSR is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the value in the MSR is transferred to the power-monitor holding register, which can be read through the microport or the serial port. The monitor period timer is reloaded with the value in the AMPR, and the countdown is started. Also, the first input sample’s magnitude is updated in the MSR, and the comparison and update procedure, as explained above, continues. If the interrupt is enabled, an interrupt is generated, and the interrupt status register is updated when the AMPR reaches a count of 1.

control bits are provided in the power-monitor control register. in all three modes of operation. pin, if interrupts are enabled in the interrupt enable register. no possibility of I/Q mismatch in real data. quadrature correction block. Figure 29. Quadrature Correction Block Diagram

Table 11. Correction Control Registers

3 Reserved (Logic 0)

2 Amplitude Correction

1 Phase Correction Enable

0 DC Correction Enable

signal is removed independently from the I and Q path signals. same and are programmable between 212 and 224 in powers of 2. the dc loop BW is 11, decimation is 224. circuit can be used to compensate for this phase offset. between I and Q is estimated (ideally, the phase should be 90°). 11, the decimation value is 224. automatic phase offset correction circuit. BW is 11, the decimation value is 224.

than −100 dBc for all output frequencies. using the low-pass filtering that follows. input ports can be paired to support complex input ports. select from the above-listed input signal choices. complement number entered in the NCO frequency register. 0x8000 0000 represents a frequency given by −CLK/2. corresponding input signal selections. 0x7FFF FFFF represents CLK/2 − CLK/232. ing the NCO frequency register. fch is the desired carrier frequency. fclk is the clock rate for the channel under consideration. 10 and, for negative numbers, mod(−32, 10) = −2. Table 12. Crossbar Mux Selection for Channel Input Signal 0 000 Input Port A magnitude and exponent pins drive the channel. 0 001 Input Port B magnitude and exponent pins drive the channel. 0 010 Input Port C magnitude and exponent pins drive the channel. 0 011 Input Port D magnitude and exponent pins drive the channel. 0 100 Internal PN sequence’s magnitude and exponent bits drive the channel. Port A exponent pins drive the channel exponent bits. Port C exponent pins drive the channel exponent bits. 1 010 Internal PN sequence’s magnitude and exponent bits drive the channel.

Figure 30. Frequency Translation Principle Using the NCO and Mixer complement representation for NCO_FREQ.

80 MHz,

and the Input Port B (or D) is connected to the Q signal path. initiating point for the new frequency. phase is added to LSBs of the phase accumulator of the NCO. filtered by subsequent stages, then phase dither is not needed.

Rev. 0 | Page 28 of 72 Amplitude Dither Amplitude dither can be used to improve spurious performance of the NCO. Amplitude dither is enabled by writing Logic 1 in the amplitude dither enable bit of the NCO control register of the channel under consideration. Random amplitude is added to the LSBs of the sine and cosine amplitudes, when this feature is enabled. Amplitude dither improves performance by randomizing the amplitude quantization errors within the angular-to-Cartesian conversion of the NCO. This option might reduce spurs at the expense of a slightly raised noise floor. Amplitude dither and phase dither can be used together, separately, or not at all. NCO Frequency Hold-Off Register When the NCO frequency registers are written by the microport or serial port, data is passed to a shadow register. Data can be moved to the main registers when the channel comes out of sleep mode, or when a sync hop occurs. In either event, a counter can be loaded with the NCO frequency hold- off register value. The 16-bit unsigned integer counter starts counting down, clocked by the input port clock selected at the crossbar mux. When the counter reaches 0, the new frequency value in the shadow register is written to the NCO frequency register. Writing 1 in this hold-off register updates the NCO frequency register as soon as the start sync or hop sync occurs. See the Chip Synchronization section for details. Phase Offset The phase offset register can be written with a value that is added as an offset to the phase accumulator of the NCO. This 16-bit register is interpreted as a 16-bit unsigned integer. A 0x0000 in this register corresponds to a 0 radian offset and a 0xFFFF corresponds to an offset of 2π × (1 − 1/216) radians. This register allows multiple NCOs (multiple channels) to be synchronized to produce complex sinusoids with a known and steady phase difference. Hop Sync A hop sync should be issued to the channel, when the channel’s NCO frequency needs to be changed from one frequency to a different frequency. This feature is discussed in detail in the Chip Synchronization section. FIFTH-ORDER CIC FILTER The signal processing stage immediately after the NCO is a CIC filter stage. This stage implements a fixed-coefficient, decimating, cascade integrated comb filter. The input rate to this filter is the same as the data rate at the input port; the output rate from this stage is dependent on the decimation factor. cic in CIC M ff = The decimation ratio, MCIC, can be programmed from 2 to 32 (only integer values). The 5-bit word in the CIC decimation register is used to set the CIC decimation factor. A binary value of one less than the decimation factor is written into this register. The decimation ratio of 1 can be achieved by bypassing the CIC filter stage. The frequency response of the filter is given by the following equations. The gain and pass-band droop of the CIC should be calculated by these equations. Both parame- ters can be offset in the RCF stage. 1)5( 1 1)( ⎟⎟ −×= − + Z ZzH CIC CIC M S )5( SIN SIN 1)( ⎛ π in in fCIC S f f f M fH CIC where: fin is the data input rate to the channel under consideration. SCIC, the scale factor, is a programmable unsigned integer between 0 and 20. The attenuation of the data into the CIC stage should be controlled in 6 dB increments. For the best dynamic range, SCIC should be set to the smallest value possible (lowest attenuation possible) without creating an overflow condition. This can be accomplished safely using the following equation, where input_level is the largest possible fraction of the full-scale value at the input port. This value is output from the NCO stage and pipelined into the CIC filter. ( )( ) 5_52log -levelinputCICMceilCICS ×= ( ) levelinputMOL CICS CIC CIC _ ×= + Bypass The fifth-order CIC filter can be bypassed when no decimation is required of it. When it is bypassed, the scaling operation is not performed. In bypass mode, the output of the CIC filter is the same as the input of the CIC filter. CIC Rejection Table 13 illustrates the amount of bandwidth as a percentage of the data rate into the CIC stage, which can be protected with various decimation rates and alias rejection specifications. The maximum input rate into the CIC is 150 MHz (the same as the maximum input port data rate). The data may be scaled to any other allowable sample rate.

on decimation, MCIC, given the desired filter characteristics. Table 13. SSB CIC5 Alias Rejection Table (fin = 1) requiring 100 dB of alias rejection for a ± 1.4 MHz pass band. is represented by the pass band. 1.48%, which is slightly larger than the 1.4% calculated. FIR2, HB2) are described in the following sections. decimate. The coefficients of this symmetric filter are {1, 2, 1}. Figure 31. FIR1 Filter Response to the Input Rate of the Filter

fFIR1 is the input rate of the FIR1 filter. fHB1 is the input rate of the HB1 filter. maximum output rate when not bypassed is 37.5 MHz. than 8.25 MHz, then HB2 might not be useful. Figure 36. Composite Response of FIR1 and HB1 filters to Their Input Rates corresponding settings are listed in Table 17. Table 17. Data Router Select Settings

000 Channel 0

001 Channel 1

010 Channel 2

011 Channel 3

front ends is useful in the polyphase implementation of filters. maximum of eight taps with 6-bit programmable coefficients. word programmed is one less than the number of filter taps. and output data to the block are both 20-bit. filters, the number of filter taps is limited to eight. savings, but can only be used if certain conditions are met.

savings). Otherwise, the PLL clock should be used. Table 18. MRCF Scaling Factor Settings

11 No scaling, 0 dB

Following the MRCF is the programmable DRCF FIR filter. of the number of taps minus one is written to this register. value written is the decimation rate minus one. of the filter is the same as the input to the DRCF filter. Table 19. DRCF Scaling Factor Settings taps or 128 symmetrical filter taps. coefficient offset from the next data sample calculation is used. DRCF or CRCF is possible using the decimation phase feature. decimation phase word of the DRCF control register.

Rev. 0 | Page 34 of 72 Maximum Number of Taps Calculated The output rate of the DRCF filter is given by DRCF MRCF DRCF M ff = where: fMRCF is the data rate out of the MRCF filter and into the DRCF filter. MDRCF is the decimation rate in the DRCF filter. The DRCF filter consists of two multipliers (one each for the I and Q paths). Each multiplier, working at the high speed clock rate (PLL clock), can do one multiply (or one tap) per high speed clock cycle. Therefore, the maximum number of filter taps that can be calculated (symmetrical or asymmetrical filter) is given by 1−⎟⎟ DRCF PLLCLK f fceilTapsofNumberMaximum where: fPLLCLK is the high speed internal processing clock generated by the PLL clock multiplier. fDRCF is the output rate of the DRCF filter calculated above. Programming DRCF Registers for an Asymmetrical Filter To program the DRCF registers for an asymmetrical filter: 1. Write NTAPS – 1 in the DRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for NTAPS is 64 in asymmetrical filter mode. 2. Write 0 for the DRCF coefficient offset register. 3. Write 0 for the symmetrical filter bit in the DRCF control register. 4. Write the start address for the coefficient RAM, typically equal to the coefficient offset register in the DRCF start address register. 5. In the DRCF stop address register, write the stop address for the coefficient RAM, typically equal to the following: Coefficient Offset + NTAPS − 1 6. Write all coefficients in reverse order (start with last coefficient) to the DRCF coefficient memory register. If in 8-bit microport mode or serial port mode, write the lower byte of the memory register first and then the higher byte. 7. After each write access to the DRCF coefficient memory register, the internal RAM address is incremented starting with the start address and ending with the stop address. Note that each write or read access increments the internal RAM address. Therefore, all coefficients should be read first before reading them back. Also, for debugging purposes, each RAM address can be written individually by making the start address and stop addresses the same. Therefore, to program one RAM location, the user writes the address of the RAM location to both the start and stop address registers, and then writes the coefficient memory register. Programming DRCF Registers for a Symmetric Filter To program the DRCF registers for a symmetrical filter: 1. Write NTAPS – 1 in the DRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for NTAPS is 128 in symmetric filter mode. 2. Write ceil(64 – NTAPS/2) for the DRCF coefficient offset register, where the ceil function takes the closest integer greater than or equal to the argument. 3. Write 1 for the symmetrical filter bit in the DRCF control register. 4. Write the start address for the coefficient RAM, typically equal to coefficient offset register, in the DRCF start address register. 5. Write the stop address for the coefficient RAM, typically equal to ceil(NTAPS/2) – 1, in the DRCF stop address register. 6. Write all coefficients to the DRCF coefficient memory register, starting with the middle of the filter and working towards the end of the filter. When coefficients are numbered 0 to NTAPS – 1, the middle coefficient is given by the coefficient number ceil(NTAPS/2). If in 8-bit microport mode or serial port mode, write the lower byte of the memory register first and then the higher byte. After each write access to the DRCF coefficient memory register, the internal RAM address is incremented starting with the start address and ending with stop address. Note that each write or read access increments the internal RAM address. Therefore, all coefficients should be read first before reading them back. Also, for debugging purposes, each RAM address can be written individually by making the start and stop addresses the same. Therefore, to program one RAM location, the user writes the address of the RAM location to both the start and stop address registers, and then writes the coefficient memory register.

coefficients, while the DRCF has 20-bit coefficients. CRCF decimation rate word in the CRCF control register. Again, the value written is the decimation rate minus one. of the filter is the same as the input to the CRCF filter. form) used to calculate the FIR filter. Table 20. CRCF Scaling Factor Settings taps or 128 symmetrical filter taps. MCRCF is the decimation rate in the CRCF filter.

1. Write NTAPS – 1 in the CRCF taps register, where NTAPS

for NTAPS is 64 in asymmetrical filter mode.

1. Write 0 for the CRCF coefficient offset register.
2. Write 0 for the symmetrical filter bit in the CRCF control
3. In the CRCF start address register, write the start address
4. In the CRCF stop address register, write the stop address
5. Write all coefficients in reverse order (start with last

byte of the memory register first and then the higher byte. CRCF memory register first and then the high four bits. with the start address and ending with the stop address. coefficient memory register.

1. Write NTAPS – 1 in the CRCF taps register, where NTAPS

for NTAPS is 128 in symmetrical filter mode.

1. Write ceil(64 – NTAPS/2) for the CRCF coefficient offset

greater than or equal to the argument.

1. Write 1 for the symmetrical filter bit in the CRCF control
2. In the CRCF start address register, write the start address
3. In the CRCF stop address register, write the stop
4. Write all coefficients to the CRCF coefficient memory

CRCF memory register first and then the high four bits. with the start address and ending with the stop address. coefficient memory register. Table 21. Other coefficients are 0. Table 21. Interpolating HB Filter Fixed Coefficients filtered out by the half-band filter.

input stream data rates that are combined. real coefficient, complex data filtering. part (quadrature) of the coefficients.

• (ICi, QCi) from first channel
• (Icq, QCq) from the second channel Using these terms, the complex filter is completed by applying the following formula: (I + jQ) (Ci + jCq) = (ICi − QCq) + j(ICq + QCi) The channels to be combined can be programmed using a 3-bit complex control word in the Parallel Output Control 2 register. The values for the 3-bit control word and the corresponding settings are listed in Table 23. These outputs go to the six available AGCs. Not all AGCs need to be used in the different applications, so unused AGCs can be bypassed and the output data streams ignored by the parallel output ports. For example, if Streams 0 and 1 are combined for a complex filter, AGC 1 can be bypassed, because Stream 1 is already combined into Stream 0 and sent to AGC 0.

Table 22. Stream Control Bit Combinations

0000 Ch 0/1 combined, Ch 2, Ch 3, Ch 4, Ch 5 independent 5

0001 Ch 0/1/2 combined, Ch 3, Ch 4, Ch5 independent 4

0010 Ch 0/1/2/3 combined; Ch 4, Ch 5 independent 3

0011 Ch 0/1/2/3/4 combined; Ch 5 independent 2

0100 Ch 0/1/2/3/4/5 combined 1

0101 Ch 0/1/2 combined, Ch 3/4/5 combined 2

0110 Ch 0/1 combined, Ch 2/3 combined, Ch 4/5 combined 3

0111 Ch 0/1 combined, Ch 2/3 combined, Ch 4, Ch 5 independent 3

1000 Ch 0/1/2 combined, Ch 3/4 combined, Ch 5 independent 3

Table 23. Definitions for Complex Control Register Selections 000 No complex filters Stream control register controls AGC usage. 001 Stream 0/1 combined Allows Ch 0 and Ch 1 to form a complex filter.

010 Stream 0/1 combined, Stream 2/3

011 Stream 0/1 combined, Stream 2/3

complex filte,r and Ch 4 and Ch 5 to form a complex filter. 101 Stream 0/1 Combined Allows Ch 0 and Ch 1 to form a biphase filter.

110 Stream 0/1 combined, Stream 2/3

111 Stream 0/1 combined, Stream 2/3

biphase filter, and Ch 4 and Ch 5 to form a biphase filter.

Rev. 0 | Page 39 of 72 Biphase Filtering Option The second special function that can be performed by the second subblock of the output data router is called the biphase filtering option. With this option, the AD6636 can be used to process data from ADCs that run faster than the input clock frequency by using two channels or two streams to form a biphase filter. For example, a 300 MHz ADC can be used with a clock rate of 150 MHz driving the ADC. The ADC data can be decimated by 2 to produce even and odd data streams of data. The even stream can be clocked into ADC Input Port A, and the odd stream can be clocked into ADC Input Port B. These input ports drive separate channels or separate groups of channels. The filters of the RCF can be designed to place a 300 MHz sample time difference (1/300 MHz = 3.3 ns) between the even and odd path filters. After the channel-filter coefficients have appropriate delay, a complex addition of the odd and even sample channels can be performed to create a single filter. This equivalent filter looks like a single channel with a 300 MHz input rate, even though the clock rate of the chip runs at only 150 MHz. A biphase filter summation is implemented by the following equation: Output = (Ie × Ce + Io × Co) + j(Qe × Ce + Qo × Co) where: Ie × Ce, Qe × Ce are even in-phase and quadrature-phase samples from one stream. Io × Co and Qo × Co are odd in-phase and quadrature-phase samples from the other stream. Ce and Co are the even and odd coefficients, which differ by 1 high speed sample time (300 MHz in the previous example). Users can program certain streams to be summed using the biphase filtering option. This option can be programmed using the same 3-bit complex control word in the Parallel Output Control 2 register. The values for the 3-bit control word and their corresponding settings are listed in Table 23. AUTOMATIC GAIN CONTROL The AD6636 is equipped with six independent automatic gain control (AGC) loops that directly follow the second data router and immediately precede the parallel output ports. Each AGC circuit has 96 dB of range. It is important that the decimating filters of the AD6636 preceding the AGC reject unwanted signals, so that each AGC loop is operating only on the carrier of interest, and carriers at other frequencies do not affect the ranging of the loop. The AGC compresses the 24-bit complex output from the second data router into a programmable word size of 4 to 8, 10, 12, or 16 bits. Because the small signals from the lower bits are pushed in to higher bits by adding gain, the clipping of the lower bits does not compromise the SNR of the signal of interest. The AGC maintains a constant mean power on the output despite the level of the signal of interest, allowing operation in environments where the dynamic range of the signal exceeds the dynamic range of the output resolution. The output width of the AGC is set by writing a 3-bit AGC word length word in the AGC control register of the individual channel’s memory map. The AGC can be bypassed, if needed, and, when bypassed, the 24-bit complex input word is still truncated to a 16-bit value that is output through the parallel port output. The six AGCs available on the AD6636 are programmable through the six channel memory maps. AGCs corresponding to individual channels can be bypassed by writing Logic 1 to AGC bypass bit in the AGC control register. Three sources of error can be introduced by the AGC function: underflow, overflow, and modulation. Underflow is caused by truncation of bits below the output range. Overflow is caused by clipping errors when the output signal exceeds the output range. Modulation error occurs when the output gain varies while receiving data. The desired signal level should be set based on the probability density function of the signal, so that the errors due to under- flow and overflow are balanced. The gain and damping values of the loop filter should be set, so that the AGC is fast enough to track long-term amplitude variations of the signal that might cause excessive underflow or overflow, but slow enough to avoid excessive loss of amplitude information due to the modulation of the signal. AGC Loop The AGC loop is implemented using a log-linear architecture. It contains four basic operations: power calculation, error calcula- tion, loop filtering, and gain multiplication. The AGC can be configured to operate in either desired signal level mode or desired clipping level mode. The mode is set by the AGC clipping error bit of the AGC control register. The AGC adjusts the gain of the incoming data according to how far it is from a given desired signal level or desired clipping level, depending on the selected mode of operation. Two datapaths to the AGC loop are provided: one before the clipping circuitry and one after the clipping circuitry, as shown in Figure 39. For the desired signal level mode, only the I/Q path from before the clipping is used. For the desired clipping level mode, the difference of the I/Q signals from before and after the clipping circuitry is used.

Rev. 0 | Page 40 of 72 I Q POWER OF 2 P POLE R DESIRED I QCLIP BITS PROGRAMMABLE BIT WIDTH ERROR K1 GAIN USED ONLY FOR DESIRED CLIPPING LEVEL MODE GAIN MULTIPLIER K2 GAIN E ERROR THRESHOLD K× z–1 SQUARE ROOT AVERAGE 1 – 16384 SAMPLES DECIMATE 1 – 4096 SAMPLES log2(x) MEAN SQUARE (I2 + Q2) CLIP 04998-0-039 Figure 39: Block Diagram of the AGC Desired Signal Level Mode In this mode of operation, the AGC strives to maintain the output signal at a programmable set level. The desired signal level mode is selected by writing Logic 0 into the AGC clipping error enable bit of the AGC control register. The loop finds the square (or power) of the incoming complex data signal by squaring I and Q and adding them. The AGC loop has an average and decimate block. This average and decimate operation takes place on power samples and before the square root operation. This block can be pro- grammed to average from 1 to 16,384 power samples, and the decimate section can be programmed to update the AGC once every 1 to 4,096 samples. The limitation on the averaging operation is that the number of averaged power samples should be a multiple of the decimation value (1×, 2×, 3×, or 4×). The averaging and decimation effectively means that the AGC can operate over averaged power of 1 to 16,384 output samples. Updating the AGC once every 1 to 4,096 samples and operating on average power facilitates the implementation of the loop filter with slow time constants, where the AGC error converges slowly and makes infrequent gain adjustments. It is also useful when the user wants to keep the gain scaling constant over a frame of data or a stream of symbols. Due to the limitation that the number of average samples must be a multiple of the decimation value, only the multiple numbers 1, 2, 3, or 4 are programmed. This is set using the AGC average samples word in the AGC average sample register. These averaged samples are then decimated with decimation ratios programmable from 1 to 4,096. This decimation ratio is defined in the 12-bit AGC update decimation register. The average and decimate operations are tied together and implemented using a first-order CIC filter and FIFO registers. Gain and bit growth are associated with CIC filters and depend on the decimation ratio. To compensate for the gain associated with these operations, attenuation scaling is provided before the CIC filter. This scaling operation accounts for the division associated with the averaging operation as well as the traditional bit growth in CIC filters. Because this scaling is implemented as a bit-shift operation, only coarse scaling is possible. Fine scaling is implemented as an offset in the request level, as explained later in this section. The attenuation scaling SCIC is programmable from 0 to 14 using a 4-bit CIC scale word in the AGC average samples register and is given by ( )[ ]avgCICCIC NMceilS ×= 2log where: MCIC is the decimation ratio (1 to 4,096). NAVG is the number of averaged samples programmed as a multiple of the decimation ratio (1, 2, 3, or 4). For example, if a decimation ratio Mcic is 1,000 and Navg is 3 (decimation of 1,000 and averaging of 3,000 samples), then the actual gain due to averaging and decimation is 3,000 or 69.54 dB (log2 (3000)). Because attenuation is implemented as a bit- shift operation, only multiples of 6.02 dB attenuations are possible. SCIC in this case is 12, corresponding to 72.24 dB. This way, SCIC scaling always attenuates more than is sufficient to compensate for the gain in the average and decimate sections and, therefore, prevents overflows in the AGC loop. But it is also evident that the SCIC scaling induces a gain error (the difference between gain due to CIC and attenuation provided by scaling) of up to 6.02 dB. This error should be compensated for in the request signal level, as explained later in this section. A logarithm to the Base 2 is applied to the output from the average and decimate section. These decimated power samples are converted to rms signal samples by applying a square root operation. This square root is implemented using a simple shift

Rev. 0 | Page 41 of 72 operation in the logarithmic domain. The rms samples obtained are subtracted from the request signal level R specified in the AGC desired level register, leaving an error term to be processed by the loop filter, G(z). The user sets this programmable request signal level R accord- ing to the output signal level that is desired. The request signal level R is programmable from −0 dB to −23.99 dB in steps of 0.094 dB. The request signal level should also compensate for errors, if any, due to the CIC scaling, as explained previously in this section. Therefore, the request signal level is offset by the amount of error induced in CIC, given by Offset = 10 × log(MCIC × Navg) − SCIC × 3.01 dB where Offset is in dB. Continuing the previous example, this offset is given by Offset = 72.24 − 69.54 = 2.7 dB So the request signal level is given by dBFS094.0094.0 )( ×⎥⎦ ⎡ −−= OffsetDSLceilR where: R is the request signal level. DSL (desired signal level) is the output signal level that the user desires. Therefore, in the previous example, if the desired signal level is −13.8 dB, the request level R is programmed to be −16.54 dB, compensating for the offset. This request signal level is programmed in the 8-bit AGC desired level register. This register has a floating-point represen- tation, where the 2 MSBs are exponent bits and the 6 LSBs are mantissa bits. The exponent is in steps of 6.02 dB, and the mantissa is in steps of 0.094 dB. For example, a value 10’100101 represents 2 × 6.02 + 37 × 0.094 = 15.518 dB. The AGC provides a programmable second-order loop filter. The programmable parameters gain 1 (K1), gain 2 (K2), error threshold E, and pole P completely define the loop filter characteristics. The error term after subtracting the request signal level is processed by the loop filter, G(z). The open loop poles of the second-order loop filter are 1 and P, respectively. The loop filter parameters, pole P and gain K, allow the adjustment of the filter time constant that determines the window for calculating the peak-to-average ratio. Depending on the value of the error term that is obtained after subtracting the request signal level from the actual signal level, either gain value, K1 or K2, is used. If the error is less than the programmable threshold E, K1 or K2 is used. This allows a fast loop when the error term is high (large convergence steps required) and a slower loop function when error term is smaller (almost converged). The open-loop gain used in the second-order loop G(z) is given by one of the following equations: K = K1, if Error < Error Threshold K = K2, if Error > Error Threshold The open-loop transfer function for the filter, including the gain parameter, is () 21 11 −− ++− PzzP KzzG If the AGC is properly configured in terms of offset in request level, then there are no gains in the AGC loop except for the filter gain K. Under these circumstances, a closed-loop expression for the AGC loop is given by () () () () 21 111 −− +−−+ =+= PzzPK Kz zG zGzGclosed The gain parameters K1, K2, and pole P are programmable through AGC loop gain 1, 2, and AGC pole location registers from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For example, 1000 1001 represent (137/256 = 0.535156). The error threshold value is programmable between 0 dB and 96.3 dB in steps of 0.024 dB. This value is programmed in the 12-bit AGC error threshold register, using floating-point representation. It consists of four exponent bits and eight mantissa bits. Exponent bits are in steps of 6.02 dB and mantissa bits are in steps of 0.024 dB. For example, 0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB. The user defines the open-loop pole P and gain K, which also directly impact the placement of the closed-loop poles and filter characteristics. These closed-loop poles, P1, P2, are the roots of the denominator of the previous closed-loop transfer function and are given by 4)1()1(

2 PKPKP

−−++−+ Typically, the AGC loop performance is defined in terms of its time constant or settling time. In this case, the closed-loop poles should be set to meet the time constants required by the AGC loop.

Rev. 0 | Page 42 of 72 The relationship between the time constant and the closed-loop poles that can be used for this purpose is τ×= 21, CIC 21, RateSample MP exp where are the time constants corresponding to poles P1, 2. 21,τ The time constants can also be derived from settling times as given by %2 timesettlingortimesettling=τ MCIC (CIC decimation is from 1 to 4,096), and either the settling time or time constant are chosen by the user. The sample rate is the sample rate of the stream coming into the AGC. If channels were interleaved in the output data router, then the combined sample rate into the AGC should be considered. This rate should be used in the calculation of poles in the previous equation, where the sample rate is mentioned. The loop filter output corresponds to the signal gain that is updated by the AGC. Because all computation in the loop filter is done in logarithmic domain (to the Base 2) of the samples, the signal gain is generated using the exponent (power of 2) of the loop filter output. The gain multiplier gives the product of the signal gain with both the I and Q data entering the AGC section. This signal gain is applied as a coarse 4-bit scaling and then as a fine scale 8-bit multiplier. Therefore, the applied signal gain is from 0 to 96.3 dB in steps of 0.024 dB. The initial signal gain is program- mable using the AGC signal gain register. This register is again a 4 exponent + 8 mantissa bit floating-point representation similar to the error threshold. This is taken as the initial gain value before the AGC loop starts operating. The products of the gain multiplier are the AGC scaled outputs with a 19-bit representation. These are in turn used as I and Q for calculating the power, and the AGC error and loop are filtered to produce the signal gain for the next set of samples. These AGC scaled outputs can be programmed to have 4-, 5-, 6-, 7-, 8-, 10-, 12-, or 16-bit widths by using the AGC output word length word in the AGC control register. The AGC scaled outputs are truncated to the required bit widths by using the clipping circuitry, as shown in Figure 39. Average Samples Setting Though it is complicated to express the exact effect of the number of averaging samples by using equations, intuitively it has a smoothing effect on the way the AGC loop addresses a sudden increase or a spike in the signal level. If averaging of four samples is used, the AGC addresses a sudden increase in signal level more slowly compared to no averaging. The same applies to the manner in which the AGC addresses a sudden les re 39; the operation er rror ce of n error term to be processed by the second- he d is sired level registers instead of in the op C ed by setting the appropriate bits of the AGC control register.

• nchronize the Sync now bit: Through the AGC control register. decrease in the signal level. Desired Clipping Level Mode Each AGC can be configured so that the loop locks onto a desired clipping level or a desired signal level. Desired clipping level mode is selected by writing Logic 1 in the AGC clipping error mode bit in the AGC control register. For signals that tend to exceed the bounds of the peak-to-average ratio, the desired clipping level option provides a way to prevent truncating those signals and still provide an AGC that attacks quickly and sett to the desired output level. The signal path for this mode of operation is shown with dotted lines in Figu is similar to the desired signal level mode. First, the data from the gain multiplier is truncated to a low resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC output word length word in the AGC control register. An e term (for both I and Q) is generated that is the difference between the signals before and after truncation. This term is passed to the complex squared magnitude block, for averaging and decimating the update samples and taking their square root to find rms samples as in desired signal level mode. In pla the request desired signal level, a desired clipping level is subtracted, leaving a order loop filter. The rest of the loop operates the same way as the desired signal level mode. This way, the truncation error is calculated and t AGC loop operates to maintain a constant truncation error level. The only register setting that is different from the desire signal level mode settings is that the desired clipping level stored in the AGC de request signal level. AGC Synchronization When the AGC output is connected to a RAKE receiver, the RAKE receiver can synchronize the average and update section to update the average power for AGC error calculation and lo filtering. This external sync signal synchronizes the AGC changes to the RAKE receiver and makes sure that the AG gain word does not change over a symbol period, which, therefore, provides a more accurate estimation. This synchro- nization can be accomplish Sync Select Alternatives The AGC can receive a sync as follows: Channel sync: The sync signal is used to sy NCO of the channel under consideration.
• Pin sync: Select one of the four SYNC pins.

AGC control register is used to provide the sync to the AGC. default, the parallel ports are in slave mode on power-up. is programmable through the two parallel port control registers. value to the square root, error estimation, and loop filter blocks. parameters are not loaded from the registers. diagram for the interleaved I/Q mode. more flexible and applicable to varied circumstances. PxCH [2:0] PxCH [2:0] = CHANNEL NO. Figure 40. Interleaved I/Q Mode without an AGC Gain Word

Rev. 0 | Page 47 of 72 USER-CONFIGURABLE BUIL T-IN SELF-TEST (BIST) Each channel of AD6636 includes a BIST block. The BIST, along with an internal test signal (pseudorandom test input signal), can be used to generate a signature. This signature can be compared with a known good device and an untested device to see if the untested device is functional. BIST timer bits in the BIST control register can be programmed with a timer value that determines the number of clock cycles that the output of the channels (output of AGC) have accumulated. When the disable signature generation bit is written with Logic 0, the BIST timer is counted down and a signature register is written with the accumulated output of the AD6636 channel. When the BIST timer expires, the signature register for I and Q paths can be read back to compare it with the signature register from a known good device. CHIP SYNCHRONIZATION The AD6636 offers two types of synchronization: start sync and hop sync. Start sync is used to bring individual channels out of sleep after programming. It can also be used while AD6636 is operational to resynchronize the internal clocks. Hop sync is used to change or update the NCO frequency tuning word and the NCO phase offset word. Two methods can be used to initiate a start sync or hop sync:

• Soft sync is provided by the memory map registers and is applied to channels directly through the microport or serial port interface.
• Pin sync is provided using four hard-wired SYNC[3:0] pins. Each channel is programmed to listen to one of these SYNC pins and do a start sync or a hop sync when a signal is received on these pins. The pin synchronization configuration register (Address 0x04) is used to make pin synchronization even more flexible. The part can be programmed to be edge-sensitive or level-sensitive for SYNC pins. In edge-sensitive mode, a rising edge on the SYNC pins is recognized as a synchronization event. Start Start refers to the startup of an individual channel or chip, or of multiple chips. If a channel is not used, it should be put into sleep mode to reduce power dissipation. Following a hard reset (low pulse on the RESET pin), all channels are placed into sleep mode. Alternatively, channels can be put to sleep manually by writing 0 to the sleep register. Start with Soft Sync The AD6636 can synchronize channels or chips under micro- processor control. The start hold-off counter, in conjunction with the soft start enable bit and the channel enable bits, enables this synchronization. To synchronize the start of multiple channels via micro- processor control: 1. Write the channel enable register to enable one or more channels, if the channels are inactive. 2. Write the NCO start hold-off counter(s) to the appropriate value (greater than 1 and less than 216). 3. Write the soft sync channel enable bit(s) and soft start synchronization enable bit high in the soft synchronization configuration register. This starts the countdown by the start hold-off counter. When the count reaches 1, the channels are activated or resynchronized. Start with Pin Sync Four sync pins (0, 1, 2, and 3) provide very accurate synchro- nization among channels. Each channel can be programmed to monitor any of the four sync pins. To start the channels with a pin sync: 1. Write the channel register to enable one more channels, if the channels are inactive. 2. Write the NCO start hold-off counter(s) to the appropriate value (greater than 1 and less than 2 16 − 1). 3. Program the channel NCO control registers to monitor the appropriate SYNC pins. 4. Write the start synchronization enable bit and SYNC pin enable bits high in the pin synchronization configuration register. This starts the countdown of the start hold-off counter. When the count reaches 1, the channels are activated or resynchronized. Hop Hop is a jump from one NCO frequency and/or phase offset to a new NCO frequency and/or phase offset. This change in frequency and/or phase offset can be synchronized via microprocessor control (soft sync) or via an external sync signal (pin sync).

bits, enables this synchronization.

1. Write the NCO frequency register(s) or phase offset

register(s) to the new value.

1. Write the NCO frequency hold-off counter(s) to the

appropriate value (greater than 1 and less than 2^16).

1. Write the soft hop synchronization enable bit and the

look at any of the four sync pins.

1. Write the NCO frequency register(s) or phase offset

register(s) to the new value.

1. Write the NCO frequency hold-off counter(s) to the
2. Program the channel NCO control registers to monitor the
3. Write the hop synchronization enable bit and SYNC pin

and/or phase offset is loaded into the NCO. made using the SMODE pin (serial port = 1, microport = 0). resistor (typical value of 1 kΩ). Table 25. Serial Port Pin Names and Functions SCLK Serial clock in both SPI and SPORT modes. Serial data is clocked in on the rising edge of SCLK. MSBFIRST Indicates whether the first bit shifted in or out of the serial port is the MSB (1) or LSB (0) of the data word. STFS Serial transmit frame sync in SPORT mode; ignored in SPI mode. SRFS Serial receive frame sync in SPORT mode; ignored in SPI mode. SDI Serial data input in both modes. SDO Serial data output in both modes. any read/write operation on serial port. SMODE Serial mode. Partis programmed through the serial port when this pin is Logic 1. MODE Mode pin. Selects between SPI (0) and SPORT (1) modes.

address locations to write (N). significant byte of the N-byte transfer). are 0x07 (Address 7) and 0x07 (number of addresses to write). The data corresponds to Addresses 0x07 to 0x01, in that order. The instruction words and data are MSB first. impedance when data is not being output. LSB first, and data comes out on the SDO with the LSB first. on SDO corresponds to Addresses 0x07 to 0x01, in that order. out on the SDO with MSB first. Figure 44. SPI Write to the AD6636 Serial Port and Transfer of 1-Byte Data to Internal Registers

Figure 45. SPI Readback Timing received in 8-bit words by using the appropriate framing signals. byte long), where N is the number of address locations to write. instruction words and data are written with the LSB first. when data is not being output. A read operation is similar to a write operation in its format. comes out on the SDO with the LSB first.

read/write cycle is complete, the AD6636 drives DTACK low. using the microport in MNM mode. clock cycles to indicate that valid data is on the data bus. can program all AD6636 devices connected to it. access is completed; otherwise, the access is ignored. intended chip; all other chips would ignore the access. The AD6636 has five pins associated with the JTAG interface. Table 27. Boundary Scan Test Pins instructions set the mode of the JTAG interface. Table 28. Boundary Scan Op Codes receive test data off-chip from boundary inputs. boundary scan register before an EXTEST instruction. affecting operation of the IC.

Rev. 0 | Page 54 of 72 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has four address locations. The memory map is roughly divided into four regions: global register map (Addresses 0x00 to 0x0B), input port register map (Addresses 0x0C to 0x67), channel register map (Addresses 0x68 to 0xBB), and output port register map (Addresses 0xBC to 0xE7). The channel register map is shared by all six channels, and access to individual channels is given by the channel I/O access control register (Address 0x02). In the memory map, Table 29, the addresses are given in the right column. The column with the heading Byte 0 has the address given in the right column. The column Byte 1 has the address given by 1 more than the address listed in the right column (address offset of 1). Similarly, the address offset for the Byte 2 column is 2, and for the Byte 3 column is 3. For example, the second row lists 0x04 as the address in the right column. The pin synchronization configuration register has Address 0x04, the soft synchronization configuration register has Address 0x05, and the LVDS control register lists Addresses 0x07 and 0x06. Bit Format All registers are in little-endian format. For example, if a register takes 24 bits or three address locations, then the most significant byte is at the highest address location and the least significant byte is at a lowest address location. In all registers, the least significant bit is Bit 0 and the most significant bit is Bit 7. For example, the NCO frequency <31:0> register is 32 bits wide. Bit 0 (LSB) of this register is written at Bit 0 of Address 0x70 and Bit 32 (MSB) of this register is written at Bit 7 of Address 0x73. When referring to a register that takes up multiple address locations, it is referred to by the address location of the most significant byte of the register. For example, the text reads, “Port A dwell timer at Address 0x2A. ” Note that only the four most significant bits of this register are at this location, and this register also takes up Addresses 0x29 and 0x28. Open Locations All locations marked as open are currently not used. When required, these locations should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x78). If the whole address location is open (for example, Address 0x00), then this address location does not need to be written. If the open locations are readback using the microport or serial port, the readback value is undefined (each bit can be independently 1 or 0), and these bits have no significance. If an address location has more than one register or has one register with some open bits, then the order of these registers is as given in the table. For example, Address 0x33 reads Open <7:5>, Port A Signal Monitor <4:0>. The open <7:5> is located at Bits <7:5> and the Port A signal monitor <4:0> is located at Bits <4:0>. Another example is Address 0x35: Open <15:10>, Port A Upper Threshold <9:0> Here, Bits <7:2> of Address 0x35 are open <15:10>. Bits <1:0> of Address 0x35 and Bits <7:0> of Address 0x34 make up the Port A upper threshold <9:0> register (Bit 1 of Address 0x35 is the MSB of the Port A upper threshold register). Default Values On coming out of reset, some of the address locations (but not all) are loaded with default values. When available, the default values for the registers are given in the table. If the default value is not listed, then these address locations are in an undefined state (Logic 0 or Logic 1) on RESET. Logic Levels In the explanation of various registers, “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ” Similarly “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ”

Table 29. Memory Map

the microport operation. Table 30 shows details. Table 30. Microport Data Bus Width Selection These bits enable/disable the channel I/O access capability. channel register map are output when this bit is set to Logic 1.

Rev. 0 | Page 57 of 72 <4>: Channel 4 Access Bit. Similar to Bit <5> for Channel 4. <3>: Channel 3 Access Bit. Similar to Bit <5> for Channel 3. <2>: Channel 2 Access Bit. Similar to Bit <5> for Channel 2. <1>: Channel 1 Access Bit. Similar to Bit <5> for Channel 1. <0>: Channel 0 Access Bit. Similar to Bit <5> for Channel 0. Note: If the access bits are set for more than one channel, during write access all channels with access are written with same the data. This is especially useful when more than one channel has similar configurations. During a read operation, if more than one channel has access, the read access is given to the channel with the lowest channel number. For example, if both Channel 4 and Channel 2 have access bits set, then read access is given to Channel 2. Channel Enable Register <5:0> <5>: Channel 5 Enable Bit. When this bit is set, Channel 5 logic is enabled. When this bit is cleared, Channel 5 is disabled and the channel’s logic does not consume any power. On power-up, this bit comes up with Logic 0 and the channel is disabled. A start sync does not start Channel 5 unless this bit is set before issuing the start sync. <4>: Channel 4 Enable Bit. Similar to Bit <5> for Channel 4. <3>: Channel 3 Enable Bit. Similar to Bit <5> for Channel 3. <2>: Channel 2 Enable Bit. Similar to Bit <5> for Channel 2. <1>: Channel 1 Enable Bit. Similar to Bit <5> for Channel 1. <0>: Channel 0 Enable Bit. Similar to Bit <5> for Channel 0. Pin Synchronization Configuration <7:0> <7>: Hop Synchronization Enable Bit. This bit is a global enable for any hop synchronization involving SYNC pins. When this bit is set, hop synchronization is enabled for all channels that are programmed for pin synchronization. When this bit is cleared, hop synchronization is not performed for any channel that is programmed for pin synchronization. <6>: Start Synchronization Enable Bit. This bit is a global enable for any start synchronization involving SYNC pins. When this bit is set, start synchronization is enabled for all channels that are programmed for pin synchronization. When this bit is cleared, start synchronization is not performed for any channel that is programmed for pin synchronization. <5>: First Sync Only Bit. When this bit is set, the NCO synchronization logic recognizes only the first synchronization event as valid. All other requests for synchronization events are ignored as long as this bit is set. When cleared, all synchro- nization events are acted upon. <4>: Edge-Sensitivity Bit. When this bit is set, the rising edge on the SYNC pin(s) is detected as a synchronization event (edge- sensitive detection). When cleared, Logic 1 on the SYNC pin(s) is detected as a synchronization event (level-sensitive detection). <3>: Enable Synchronization from SYNC3 Bit. When this bit is set, the SYNC3 pin can be used for synchronization. When this bit is cleared, the SYNC3 pin is ignored. This is a global enable for all SYNC pins, and each individual channel selects which pin it listens to. <2>: Enable Synchronization from SYNC2 Bit. Similar to Bit <3> for the SYNC[2] pin. <1>: Enable Synchronization from SYNC1 Bit. Similar to Bit <3> for the SYNC1 pin. <0>: Enable Synchronization from SYNC0 bit. Similar to Bit <3> for the SYNC0 pin. Soft Synchronization Configuration <7:0> <7>: Soft Hop Synchronization Enable Bit. When this bit is set, hop synchronization is enabled for all channels selected using Bits 5:0. When this bit is cleared, hop synchronization is not performed for any channels selected using Bits 5:0. <6>: Soft Start Synchronization Enable Bit. When this bit is set, start synchronization is enabled for all channels selected using Bits 5:0. When this bit is cleared, start synchronization is not performed for any channels selected using Bits 5:0. Bits<5:0> form the SOFT_SYNC control bits. These bits can be written to by the controller to initiate the synchronization of a selected channel. <5>: Soft Sync Channel 5 Enable Bit. When this bit is set, it enables Channel 5 to receive a hop sync or start sync, as defined by Bits 7 and 6, respectively. When cleared, Channel 5 does not receive any soft sync. <4>: Soft Sync Channel 4 Enable Bit. Similar to Bit <5> for Channel 4. <3>: Soft Sync Channel 3 Enable Bit. Similar to Bit <5> for Channel 3. <2>: Soft Sync Channel 2 Enable Bit. Similar to Bit <5> for Channel 2. <1>: Soft Sync Channel 1 Enable Bit. Similar to Bit <5> for Channel 1. <0>: Soft Sync Channel 0 Enable Bit. Similar to Bit <5> for Channel 0.

Rev. 0 | Page 58 of 72 LVDS Control Register <10:0> <10>: CMOS Mode Bit. When this bit is set, the ADC ports operate in CMOS mode. When this bit is cleared, the ADC ports operate in LVDS mode. The default is Logic 1 or CMOS mode. In LVDS mode, two CMOS ADC port pins are used to form one differential pair of LVDS ADC ports. <9>: Reserved. This bit should always be written Logic 1. <8>: Autocalibrate Enable Bit. When this bit is set, the auto- calibration cycle is invoked for the LVDS pads. At the end of calibration, this calibration value is set for the LVDS pads. When this bit is cleared, the output for the LVDS controller is taken from manual calibration value (Bits <7:0> of this register). <7:4>: These bits are open. <3:0>: Manual Calibration Value Bits. The value of these bits is used for manual LVDS calibration. When the autocalibrate bit is set, these bits are don’t care. Interrupt Status Register <15:0> This register is read-only. <15>: AGC 5 RSSI Update Interrupt Bit. If the AGC 5 update interrupt enable bit is set, this bit is set by the AD6636 whenever AGC 5 updates a new RSSI word (the new word should be different from the previous word). If the AGC 5 update interrupt enable bit is cleared, then this bit is not set (not updated). An interrupt is not generated in this case. Note: For Bits <15:10>, no interrupt is generated, if the new RSSI word is the same as the previous RSSI word. <14>: AGC 4 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC 4. <13>: AGC 3 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC 3. <12>: AGC 2 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC 2. <11>: AGC 1 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC 1. <10>: AGC 0 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC 0. <9>: Channel 5 Data Ready Interrupt Bit. This bit is set to Logic 1 whenever the channel BIST signature registers are loaded with data. The conditions required for setting this bit are: the channel BIST signature registers is programmed for BIST signature generation and the Channel 5 data ready enable bit in the interrupt enable register is cleared. If the Channel 5 data ready enable bit in the interrupt enable register is set, the AD6636 does not set this bit on signature generation and an interrupt is not generated. <8>: Channel 4 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 4. <7>: Channel 3 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 3. <6>: Channel 2 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 2. <5>: Channel 1 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 1. <4>: Channel 0 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 0. <3>: ADC Port D Power Monitoring Interrupt Bit. This bit is set by the AD6636 whenever the ADC Port D power monitor interrupt enable bit is set and the Port D power monitor timer runs out (end of the Port D power monitor period). If the ADC Port D power monitoring interrupt enable bit is cleared, the AD6636 does not set this bit and does not generate an interrupt. Note: In real input CMOS mode, all four input ports exist. In complex input CMOS mode, only ADC Ports A and C function. In real input LVDS mode, only ADC Ports A and C function. <2>: ADC Port C Power Monitoring Interrupt Bit. Similar to Bit <3> for ADC Port C. <1>: ADC Port B Power Monitoring Interrupt Bit. Similar to Bit <3> for ADC Port B. <0>: ADC Port A Power Monitoring Interrupt Bit. Similar to Bit <3> for ADC Port A. Interrupt Enable Register <15:0> <15>: AGC 5 RSSI Update Enable Bit. When this bit is set, the AGC 5 RSSI update interrupt is enabled, allowing an interrupt to be generated when the RSSI word is updated. When this bit is cleared, an interrupt cannot be generated for this event. Also, see the Interrupt Status Register <15:0> section. <14>: AGC 4 RSSI Update Enable Bit. Similar to Bit <15> for the AGC 4. <13>: AGC 3 RSSI Update Enable Bit. Similar to Bit <15> for the AGC 3. <12>: AGC 2 RSSI Update Enable Bit. Similar to Bit <15> for the AGC 2. <11>: AGC 1 RSSI Update Enable Bit. Similar to Bit <15> for the AGC 1. <10>: AGC 0 RSSI Update Enable Bit. Similar to Bit <15> for the AGC 0.

the ADC Port D power monitoring interrupt is disabled. These bits are general control bits for the ADC input logic. generator is disabled and the seed is set to its default value. and ADC Port D interpreted as real and independent input. and ADC Port B is interpreted as real and independent input. Table 31. Channel 5 Input Configuration

These bits control the ADC clocks and internal PLL clock. is, without any inversion or phase change. Table 32. PLL Clock Divider Select Bits <0>: This bit is open (write Logic 0). increases the decimation value by a power of 2. decimation value by a power of 2. decimation/interpolation value by a power of 2. function of the I/Q correction logic for the AB port is enabled. cleared (real input mode), this bit is a don’t care. increases the decimation value by a power of 2. decimation value by a power of 2. decimation/interpolation value by a power of 2.

Rev. 0 | Page 61 of 72 <2>: Port CD Amplitude Correction Enable Bit. When this bit is set, the amplitude correction function of the I/Q correction logic for the AB port is enabled. When this bit is cleared, the amplitude correction value is given by the value of the AB amplitude correction register. If the Port A complex data active bit of the ADC input control register is cleared (real input mode), this bit is a don’t care. <1>: Port CD Phase Correction Enable Bit. When this bit is set, the phase correction function of the I/Q correction logic for the AB port is enabled. When this bit is cleared, the phase correction value is given by the value of the AB phase correction register. If the Port A complex data active bit of the ADC input control register is cleared (real input mode), this bit is a don’t care. <0>: Port CD DC Correction Enable Bit. When the dc correction enable bit is set, the dc offset correction function of the I/Q correction block for the AB port is enabled. When cleared, the dc offset correction value is given by the value of the AB offset correction registers. If the Port A complex data active bit of the ADC input control register is cleared (real input mode), this bit is a don’t care. Port AB, DC Offset Correction I <15:0> This register holds the in-phase signal dc offset correction value for complex data stream when dc correction is enabled. This value should be set manually when automatic correction is disabled. This 16-bit value is subtracted from the 16-bit ADC Port A data (in-phase signal). This data is a don’t care in real input mode. Port AB, DC Offset Correction Q <15:0> This register holds the quadrature phase signal dc offset correction value for complex data stream when dc correction enabled. This value should be set manually when automatic correction is disabled. This 16-bit value is subtracted from the 16-bit ADC Port B data (quadrature phase signal). This data is a don’t care in real input mode. Port CD, DC Offset Correction I <15:0> This register holds the in-phase signal dc offset correction value for complex data stream when dc correction is enabled. This value should be set manually when automatic correction is disabled. This 16-bit value is subtracted from the 16-bit ADC Port C data (in-phase signal). This data is a don’t care in real input mode. Port CD, DC Offset Correction Q <15:0> This register holds the quadrature phase signal dc offset correction value for complex data stream when dc correction is enabled. This value should be set manually when automatic correction is disabled. This 16-bit value is subtracted from the 16-bit ADC Port D data (quadrature phase signal). This data is a don’t care in real input mode. Port AB, Phase Offset Correction <15:0> This register holds the phase offset correction value for complex data stream when the AB port phase correction is enabled. This value is set manually when automatic correction is disabled. This value is calculated as tan(phase_mismatch), where phase_mismatch is the mismatch in phase between I (in-phase signal) and Q (quadrature phase signal). This 14-bit value is multiplied with 16-bit Q (quadrature phase signal, Input Port B) and added to 16-bit I (in-phase signal, Input Port A). This data is a don’t care in real input mode. Port AB, Amplitude Offset Correction <15:0> This register holds the amplitude offset correction value for complex data stream when the AB port amplitude correction is enabled. This value is set manually when automatic correction is disabled. This value is calculated as (Mag(Q) − Mag(I)), where I is the in-phase signal and Q is the quadrature phase signal. This 14-bit value is multiplied with 16-bit Q (quadrature phase signal, Input Port B) and added to 16-bit Q (quadrature phase signal, Input Port B). This data is a don’t care in real input mode. Port CD, Phase Offset Correction <15:0> This register holds the phase offset correction value for the complex data stream when CD port phase correction is enabled. This value should be set manually when automatic correction is disabled. This value should be calculated as tangent (phase_mismatch), where phase_mismatch is the mismatch in phase between I (in-phase signal) and Q (quadrature phase signal). This 14-bit value is multiplied with 16-bit Q (quadrature phase signal, Input Port D) and added to 16-bit I (in-phase signal, Input Port C). This data is a don’t care in real input mode. Port CD, Amplitude Offset Correction <15:0> This register holds the amplitude offset correction value for complex data stream when CD port amplitude correction is enabled. This value is set manually when automatic correction is disabled. This value is calculated as (Mag(Q) − Mag(I)), where I is the in-phase signal and Q is the quadrature phase signal. This 14-bit value are multiplied with 16-bit Q (quadrature phase signal, Input Port D) and added to 16-bit Q (quadrature phase signal, Input Port D). This data is a don’t care in real input mode. Port A Gain Control <7:0> <7>: This bit is open. <6:1>: This 6-bit word specifies the relinearization pipe delay to be used in the ADC input gain control block. The decimal representation of these bits is the number of input clock cycle pipeline delays between the external EXP data output and the internal application of relinearization based on EXP .

outputs. When this bit is cleared, the EXP<2:0> bits are inputs. drop below the lower threshold is detected in the signal level. interrupt signal is not generated. of the data after removing the negative sign. compared with the absolute magnitude of the input port data. the value of the data after removing the negative sign. don’t care if the disable integration counter bit is clear. Table 33. Monitor Function Select Bits

00 Peak Detect Mode

01 Mean Power Monitor Mode

10 Threshold Crossing Mode

11 Invalid Selection

corresponding registers definitions for Port A. access register (Address 0x02). These bits control the NCO operation. tion operation. Table 34 describes the selection. Table 34. Sync Start Select Bits

00 SYNC0

01 SYNC1

10 SYNC2

11 SYNC3

tion operation. Table 35 describes the selection. Table 35. Sync Hop Select Bits this bit is cleared, the NCO operates as programmed. cleared, amplitude dithering is disabled. channel operation is started. the shadow register is written to the NCO frequency register. NCO_FREQUENCY is the desired NCO tuning frequency. 0xFFFF corresponds to an offset of 2π (1 − 1/(216)) radians.

1. A value of 0x00 is a decimation of 1 (bypass), and 0x1F is a

CIC filtering, but does not bypass the CIC scaling operation. in the CIC decimation register). The valid range for this register is decimal 0 to 20. coefficient filter is enabled. When cleared, FIR1 is bypassed. filter is enabled. When cleared, HB1 is bypassed. coefficient filter is enabled. When cleared, FIR2 is bypassed. filter is enabled. When cleared, HB2 is bypassed.

ently. Table 36 shows the selections available. Table 36. MRCF Data Select Bits

000 MRCF input taken from Channel 0

001 MRCF input taken from Channel 1

010 MRCF input taken from Channel 2

011 MRCF input taken from Channel 3

band filter is bypassed and its output is the same as its input. The interpolating half-band filter doubles the data rate. and maximum value of 7 represents an 8-tap filter. the attenuation corresponding to each setting. Table 37. MRCF Scale Factor

11 No Scaling (0 dB)

operation as programmed by its control register. grammed by the rest of this control register. implement up to 128 filter taps. DRCF filter is scaled according to the value of these bits. Table 38 lists the attenuation corresponding to each setting. Table 38. DRCF Multiply Accumulate Scale Bits is used for filtering one signal (one carrier). comes out of the DRCF with the new filter.

coefficient memory to be updated. coefficient memory to be updated. program the coefficients into the coefficient memory. grammed by its control register. implement up to 128 filter taps. CRCF filter is scaled according to the value of these bits. Table 39 lists the attenuation corresponding to each setting. Table 39. CRCF Multiply Accumulate Scale Bits is used for filtering one signal (one carrier). comes out of the CRCF with the new filter. uses the sync signal from the channel for its synchronization. is defined by Bits <9:8> of this register. AGC control register is set to Logic 1. Table 40. SYNC Pin Select Bits

10, 12, or 16 bits wide. Table 41 shows the possible selections. Table 41. AGC Word Length Control Bits Automatic Gain Control section for details about these modes. and starts working toward a new update sample. scale, signal gain Gs’ gain K, and pole parameter P are loaded. decimation factor of the AGC CIC filter. output of the AGC accomplishes this task.

1. An appropriate scaling factor should be set to avoid loss of

describes a decimation ratio of 4096. gain in the range of 0 dB and 96.296 dB in steps of 0.024 dB. which loop gain value (K1 or K2) to use for optimum operation. Gain Control section for details. CIC decimating filter. See Table 42. Table 42. Number of AGC Average Samples

Rev. 0 | Page 67 of 72 AGC Pole Location <7:0> This 8-bit register is used to define the open-loop filter pole location P. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of P is updated in the AGC loop each time the AGC is initialized. This open-loop pole location directly impacts the closed-loop pole locations, as explained in the Automatic Gain Control section. AGC Desired Level <7:0> This register contains the desired signal level or desired clipping level, depending on operational mode. This desired request level (R) can be set in dB from 0 to 23.99 in steps of 0.094 dB. The request level (R) in dB should be converted to a register setting using the following formula: Register Value = round ⎥ ⎡ ×64)2(log20 10 R AGC Loop Gain2 <7:0> This 8-bit register is used to define the second possible open- loop gain, K2. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of K2 is updated each time the AGC is initialized. When the magnitude-of-error signal in the loop is greater than the AGC error threshold, then K2 is used by the loop. K2 is updated only when the AGC is initialized. AGC Loop Gain1 <7:0> This 8-bit register is used to define the open-loop gain K1. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of K is updated in the AGC loop each time the AGC is initialized. When the magnitude-of-error signal in the loop is less than the AGC error threshold, then K1 is used by the loop. K1 is updated only when the AGC is initialized. I Path Signature Register <15:0> This 16-bit signature register is for the I path of the channel logic. The signature register records data on the networks that leave the channel logic, just before entering the second data router. Q Path Signature Register <15:0> This 16-bit signature register is for the Q path of the channel logic. The signature register records data on the networks that leave the channel logic, just before entering the second data router. BIST Control <23:0> <15>: Disable Signature Generation Bit. When this bit is active high, the signature registers do not produce a pseudorandom output value, but instead directly load the 24-bit input data. When this bit is cleared, the signature register produces a pseudorandom output for every clock cycle that it is active. See the User-Configurable Built-In Self-Test (BIST) section for details. <14:0>: BIST Timer Bits. The <14:0> bits of this register form a 15-bit word that is loaded into the BIST timer. After loading the BIST timer, the signature register is enabled for operation while the timer is actively counting down. (See the User-Configurable Built-In Self-Test (BIST) section.) OUTPUT PORT REGISTER MAP This part of the memory map deals with the output data and controls for parallel output ports. Parallel Port Output Control <31:0> <23>: Port C Append RSSI Bit. When this bit is set, an RSSI word is appended to every I/Q output sample, irrespective of whether the RSSI word is updated in the AGC. When this bit is cleared, an RSSI word is appended to an I/Q output sample only when the RSSI word is updated. The RSSI word is not output for subsequent I/Q samples until the next time the RSSI is updated in the AGC. <22>: Port C, Data Format Bit. When this bit is set, the port is configured for 8-bit parallel I/Q mode. When cleared, the port is configured for 16-bit interleaved I/Q mode. See the Parallel Port Output section for details. <21>: Port C, AGC 5 Enable Bit. When this bit is set, AGC 5 data (I/Q data) is output on parallel Output Port C (data bus). When this bit is cleared, AGC 5 data does not appear on Output Port C. <20>: Port C, AGC 4 Enable Bit. Similar to Bit <21> for AGC 4. <19>: Port C, AGC 3 Enable Bit. Similar to Bit <21> for AGC 3. <18>: Port C, AGC 2 Enable Bit. Similar to Bit <21> for AGC 2. <17>: Port C, AGC 1 Enable Bit. Similar to Bit <21> for AGC 1. <16>: Port C, AGC 0 Enable Bit. Similar to Bit <21> for AGC 0. <15>: Port B Append RSSI Bit. When this bit is set, an RSSI word is appended to every I/Q output sample, irrespective of whether or not the RSSI word is updated in the AGC. When this bit is cleared, an RSSI word is appended to an I/Q output sample only when the RSSI word is updated. The RSSI word is not output for subsequent I/Q samples until the next time the RSSI is updated in the AGC. <14>: Port B, Data Format Bit. When this bit is set, the port is configured for 8-bit parallel I/Q mode. When this bit is cleared, the port is configured for 16-bit interleaved I/Q mode. See the Parallel Port Output section. <13>: Port B, AGC 5 Enable Bit. When this bit is set, AGC 5 data (I/Q data) is output on parallel output Port A (data bus). When this bit is cleared, AGC 5 data does not appear on output Port C.

<12>: Port B, AGC 4 Enable Bit. Similar to Bit <13> for AGC 4. <11>: Port B, AGC 3 Enable Bit. Similar to Bit <13> for AGC 3. <10>: Port B, AGC 2 Enable Bit. Similar to Bit <13> for AGC 2. <9>: Port B, AGC 1 Enable Bit. Similar to Bit <13> for r AGC 1. <8>: Port B, AGC 0 Enable Bit. Similar to Bit <13> for AGC 0. Parallel Port Output section. this bit is cleared, AGC 5 data does not appear on output Port C. <4>: Port A, AGC 4 Enable Bit. Similar to Bit <5> for AGC 4. <3>: Port A, AGC 3 Enable Bit. Similar to Bit <5> for AGC 3. <2>: Port A, AGC 2 Enable Bit. Similar to Bit <5> for AGC 2. <1>: Port A, AGC 1 Enable Bit. Similar to Bit <5> for AGC 1. <0>: Port A, AGC 0 Enable Bit. Similar to Bit <5> for AGC 0. obtain the PCLK. These bits are don’t care in slave mode. Table 43. PCLK Divisor Bits to avoid contention on the PCLK pin. Table 44. Complex Control Bits

000 No complex filters Stream control register controls

001 Str0/1 combined Ch 0 and Ch 1 form a complex

010 Str0/1 combined,

011 Str0/1 combined,

101 Str0/1 combined Ch 0 and Ch 1 form a biphase

110 Str0/1 combined,

111 Str0/1 combined,

<3:0>: Stream Control Bits. These bits are described in Table 45. Table 45. Stream Control Bits

0000 Ch 0/1 combined; Ch 2, Ch 3,

0001 Ch 0/1/2 combined; Ch 3, Ch 4,

0010 Ch 0/1/2/3 combined; Ch 4, Ch

0011 Ch 0/1/2/3/4 combined; Ch 5

0101 Ch 0/1/2 combined, Ch 3/4/5

0110 Ch 0/1 combined, Ch 2/3

0111 Ch 0/1 combined, Ch 2/3

1000 Ch 0/1/2 combined, Ch 3/4

1001 Ch 0/1/2/3 combined, Ch 4/5

Rev. 0 | Page 69 of 72 AGC 0, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC 0. Note that AGC 0 might be bypassed, and that AGC 0 here is representative of the datapath only. AGC 0, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 0. Note that AGC 0 might be bypassed, and that AGC 0 here is representative of the datapath only. AGC 1, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC 1. Note that AGC 1 might be bypassed and that AGC 1 here is representative of the datapath only. AGC 1, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 1. Note that AGC 1 might be bypassed and that AGC 1 here is representative of the datapath only. AGC 2, I Output <15:0: This read-only register provides the latest in-phase output sample from AGC 2. Note that AGC 2 might be bypassed and that AGC 2 here is representative of the datapath only. AGC 2, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 2. Note that AGC 2 might be bypassed and that AGC 2 here is representative of the datapath only. AGC 3, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC 3. Note that AGC 3 might be bypassed and that AGC 3 here is representative of the datapath only. AGC 3, Q output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 3. Note that AGC 3 might be bypassed and that AGC 3 here is representative of the datapath only. AGC 4, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC 4. Note that AGC 4 might be bypassed and that AGC 4 here is representative of the datapath only. AGC 4, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 4. Note that AGC 4 might be bypassed and that AGC 4 here is representative of the datapath only. AGC 5, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC 5. Note that AGC 5 might be bypassed and that AGC 5 here is representative of the datapath only. AGC 5, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC 5. Note that AGC 5 might be bypassed and that AGC 5 here is representative of the datapath only. AGC 0, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 0. This register is updated only when AGC 0 is enabled and operating. AGC 1, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 1. This register is updated only when AGC 1 is enabled and operating. AGC 2, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 2. This register is updated only when AGC 2 is enabled and operating. AGC 3, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 3. This register is updated only when AGC 3 is enabled and operating. AGC 4, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 4. This register is updated only when AGC 4 is enabled and operating. AGC 5, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC 5. This register is updated only when AGC 5 is enabled and operating.

Rev. 0 | Page 71 of 72 If JTAG is used, the designer should ensure that the TRST pin is pulled low during power-up. After the power supplies have settled to nominal values (1.8 V and 3.3 V), the TRST pin can be pulled high for JTAG control. When JTAG control is no longer required, the TRST pin should ideally be pulled low again.

• The CPUCLK (SCLK) is the clock used for programming via the microport (serial port). This clock needs to be provided by the designer to the part (slave clock). The designer should ensure that this clock’s frequency is less than or equal to the frequency of the CLKA signal. Additionally, the frequency of the CPUCLK (SCLK) should always be less than 100 MHz.
• CLKA, CLKB, CLKC, and CLKD are used as individual clocks to input data into Input Ports A, B, C, and D, respectively. All these clocks are required to have same frequency and should ideally be generated from the same clock source. Note that CLKA is used to drive the internal circuitry and the PLL clock multiplier. Therefore, even if Input Port A is not used, CLKA should be driven by the input clock.
• The microport data bus is 16 bits wide. Both 8-bit and 16 bit modes are available using this part. If 8-bit mode is used, the MSB of the data bus (D[15:8]) can be left floating or connected to GND.
• The output parallel port has a one clock cycle overhead. If two channels (with the same data rates) are output on one output port in 16-bit interleaved I/Q mode along with an AGC word, this requires three clock cycles for one sample from each channel (one clock each for I data, Q data, and gain data). Therefore, the total number of clock cycles required to output the data is 3 clocks/channel × 2 channels + 1 (overhead) = 7 clock cycles. The number of clock cycles required for each channel can be 3 (interleaved I + Q + gain word), or 2 (parallel I /Q + gain) or 2 (interleaved I + Q) or 1 (interleaved I/Q). Designers should make sure that sufficient time is allowed to output these channels on one output port. Also note that the I, Q, and gain for a particular channel all come out on a single output port and cannot be divided among output ports.
• When CRCF and DRCF filters are disabled, the coefficient memory cannot be read back, because the clock to the coefficient RAM is also cut off.
• In the Intel mode microport, the beginning of a read and write access is indicated by the RDY pin going low. The access is complete only when the RDY pin goes high. In the Motorola mode microport, the completion of a read and write access is indicated by the DTACK going low. In both modes, CS, RD (DS), and WR (R/W) should be active until access is complete; otherwise, an incomplete access results.
• In both Intel and Motorola modes, if CS is held low even after microport read or write access is complete, the microport initiates a second access. This is a problem while writing or reading from coefficient RAM, where each access writes to or reads from a different RAM address. This can be fixed by writing to one coefficient RAM address at a time, that is, the coefficient start and stop address registers have the same value.
• In SPI mode programming, the SCS pin needs to go high (inactive) after writing or reading each byte (eight clock cycles on the SCLK pin).

0.30 MIN*

EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL. Figure 53. 256-Lead Chip Scale Ball Grid Array [CSP_BGA] registered tra demarks are the prop erty of their respective owners .