AD6624

AD6624_15 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 40

Technical content

a AD6624 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. REV. B The AD6624 is part of Analog Devices’ SoftCell® multicarrier transceiver chipset designed for compatibility with Analog Devices’ family of high sample rate IF sampling ADCs (AD6640/ AD6644 12- and 14-bit). The SoftCell receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and c hannel selection. This architecture eliminates redundant radios in wireless base station applications. High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters remove unwanted signals and noise from the channel of interest. When the channel of interest occupies less bandwidth than the input signal, this rejection of out-of-band noise is called “processing gain.” By using large decimation factors, this “processing gain” can improve the SNR of the ADC by 30 dB or more. In addition, the programmable RAM coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, cost- effective filter. The AD6624 is compatible with standard ADC converters such as the AD664x, AD9042, AD943x, and the AD922x families of data converters. The AD6624 is also compatible with the AD6600 Diversity ADC, providing a cost and size reduction path. Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) FUNCTIONAL BLOCK DIAGRAM CH A NCO rCIC2 RESAMPLER CIC5 RAM COEFFICIENT FIL TER

16 BITS 18 BITS 20 BITS 24 BITS

INA[13:0] EXP A[2:0] IENA LIA-A LIA-B SYNCA SYNCB SYNCC SYNCD INB[13:0] EXPB[2:0] IENB LIB-A LIB-B SDIN[3:0] SDO[3:0] DR[3:0] SDFS[3:0] SDFE[3:0] SCLK[3:0] MODE DS(RD) CS RW (WR) DTACK(RDY) A[2:0] D[7:0] CH B NCO rCIC2 RESAMPLER CIC5 RAM COEFFICIENT FIL TER CH C NCO rCIC2 RESAMPLER CIC5 RAM COEFFICIENT FIL TER CH D NCO rCIC2 RESAMPLER CIC5 RAM COEFFICIENT FIL TER EXTERNAL SYNC CIRCUITRY JT AG INTERFACE BUIL T -IN SELF-TEST

FEATURES

80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)

Dual High Speed Data Input Ports Four Independent Digital Receivers in Single Package Digital Resampling for Noninteger Decimation Rates Programmable Decimating FIR Filters Programmable Attenuator Control for Clip Prevention and External Gain Ranging via Level Indicator Flexible Control for Multicarrier and Phased Array 3.3 V I/O, 2.5 V CMOS Core User-Configurable Built-In Self-Test (BIST) Capability JTAG Boundary Scan

APPLICATIONS

Multicarrier, Multimode Digital Receivers GSM, IS136, EDGE, PHS, IS95 Micro and Pico Cell Systems Wireless Local Loop Smart Antenna Systems Software Radios In-Building Wireless Telephony PRODUCT DESCRIPTION The AD6624 is a four-channel (quad) digital receive signal processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable-coefficient decimating filter.

REV. B AD6624 –2– TABLE OF CONTENTS Scaling with Floating-Point or Gain-Ranging ADCs . . . . 16 FIFTH ORDER CASCADED INTEGRATOR COMB USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) 22 0x90: rCIC2 Decimation – 1 (M 0x94: CIC5 Decimation – 1 (M 0xA0: RCF Decimation – 1 (M

REV. B –3– AD6624 RECOMMENDED OPERATING CONDITIONS Test AD6624AS Parameter Level Min Typ Max Unit VDD IV 2.375 2.5 2.675 V VDDIO IV 3.0 3.3 3.6 V TAMBIENT IV –40 +25 +70 °C

ELECTRICAL CHARACTERISTICS

Parameter (Conditions) Temp Level Min Typ Max Unit LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Full 3.3 V CMOS Logic “1” Voltage Full IV 2.0 5.0 V Logic “0” Voltage Full IV –0.3 +0.8 V Logic “1” Current Full IV 1 10 µA Logic “0” Current Full IV 1 10 µA Input Capacitance 25 °CV 4 p F LOGIC OUTPUTS Logic Compatibility Full 3.3 V CMOS/TTL Logic “1” Voltage (IOH = 0.25 mA) Full IV 2.4 VDD – 0.2 V Logic “0” Voltage (IOL = 0.25 mA) Full IV 0.2 0.4 V IDD SUPPLY CURRENT CLK = 80 MHz, (VDD = 2.75 V, VDDIO = 3.6 V) Full IV IVDD 400 mA IVDDIO 60 mA CLK = GSM Example (65 MSPS, VDD = 2.5 V, VDDIO = 3.3 V, Dec = 2/10/6 120 Taps 4 Channels) 25 °CV IVDD 250 mA IVDDIO 24 mA POWER DISSIPATION CLK = 80 MHz TD-SCDMA Full IV 1.1 W CLK = 65 MHz GSM/EDGE Example V 700 mW Sleep Mode Full IV 287 µW Specifications subject to change without notice. SPECIFICATIONS(VDD = 2.5 V /H11550 5%, VDDIO = 3.3 V /H11550 10%. All specifications T A = TMIN to TMAX, unless otherwise noted.)

REV. B–4– AD6624–SPECIFICATIONS GENERAL TIMING CHARACTERISTICS1, 2 Test AD6624AS Parameter (Conditions) Temp Level Min Typ Max Unit CLK Timing Requirements : tCLK CLK Period Full I 12.5 ns tCLKL CLK Width Low Full IV 4.5 0.5 × tCLK ns tCLKH CLK Width High Full IV 4.5 0.5 × tCLK ns RESET Timing Requirement: tRESL RESET Width Low Full I 30.0 ns Input Wideband Data Timing Requirements : tSI Input to ↑CLK Setup Time Full IV 0.8 ns tHI Input to ↑CLK Hold Time Full IV 2.0 ns Level Indicator Output Switching Characteristic : tDLI ↑CLK to LI (A–A, B; B–A, B) Output Delay Time Full IV 3.8 12.6 ns SYNC Timing Requirements : tSS SYNC (A, B, C, D) to ↑CLK Setup Time Full IV 1.0 ns tHS SYNC (A, B, C, D) to ↑CLK Hold Time Full IV 2.0 ns Serial Port Timing Requirements (SBM = 1): Switching Characteristics :3 tDSCLK1 ↑CLK to ↑SCLK Delay (Divide by 1) Full IV 3.9 13.4 ns tDSCLKH ↑CLK to ↑SCLK Delay (For Any Other Divisor) Full IV 4.4 14.0 ns tDSCLKL ↑CLK to ↓SCLK Delay (Divide by 2 or Even #) Full IV 3.25 6.7 ns tDSCLKLL ↓CLK to ↓SCLK Delay (Divide by 3 or Odd #) Full IV 3.8 6.9 ns tDSDFS ↑SCLK to SDFS Delay Full IV 0.2 5.3 ns tDSDFE ↑SCLK to SDFE Delay Full IV –0.4 +4.7 ns tDSDO ↑SCLK to SDO Delay Full IV –1.0 +4.0 ns tDSDR ↑SCLK to DR Delay Full IV –0.3 +4.6 ns tDDR ↑CLK to DR Delay Full IV 5.4 17.6 ns Input Characteristics : tSSI SDI to ↓SCLK Setup Time Full IV 2.4 ns tHSI SDI to ↓SCLK Hold Time Full IV 3.0 ns Serial Port Timing Requirements (SBM = 0): Switching Characteristics :3 tSCLK SCLK Period Full IV 16 ns tSCLKL SCLK Low Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns tSCLKH SCLK High Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns tDSDFE ↑SCLK to SDFE Delay Full IV 3.8 15.4 ns tDSDO ↑SCLK to SDO Delay Full IV 3.7 15.2 ns tDSDR ↑SCLK to DR Delay Full IV 3.9 15.9 ns Input Characteristics : tSSF SDFS to ↑SCLK Setup Time Full IV 1.9 ns tHSF SDFS to ↑SCLK Hold Time Full IV 0.7 ns tSSI SDI to ↓SCLK Setup Time Full IV 2.4 ns tHSI SDI to ↓SCLK Hold Time Full IV 2.0 ns NOTES 2CLOAD = 40 pF on all outputs unless otherwise specified. 3The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port ’s (SCLK) operating frequency is limited to 62.5 MHz. Specifications subject to change without notice.

REV. B –5– AD6624 MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2 Test AD6624AS Parameter (Conditions) Temp Level Min Typ Max Unit MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing : tSC Control3 to ↑CLK Setup Time Full IV 5.5 ns tHC Control3 to ↑CLK Hold Time Full IV 1.0 ns tHWR WR(RW) to RDY(DTACK) Hold Time Full IV 8.0 ns tSAM Address/Data to WR(RW) Setup Time Full IV –0.5 ns tHAM Address/Data to RDY(DTACK) Hold Time Full IV 7.0 ns tDRDY WR(RW) to RDY(DTACK) Delay Full IV 4.0 ns tACC WR(RW) to RDY(DTACK) High Delay Full IV 4 × tCLK 5 × tCLK 9 × tCLK ns MODE INM Read Timing: tSC Control3 to ↑CLK Setup Time Full IV 4.0 ns tHC Control3 to ↑CLK Hold Time Full IV 2.0 ns tSAM Address to RD(DS) Setup Time Full IV 0.0 ns tHAM Address to Data Hold Time Full IV 7.0 ns tDRDY RD(DS) to RDY(DTACK) Delay Full IV 4.0 ns tACC RD(DS) to RDY(DTACK) High Delay Full IV 8 × tCLK 10 × tCLK 13 × tCLK ns MICROPROCESSOR PORT, MODE MNM (MODE = 1) MODE MNM Write Timing : tSC Control3 to ↑CLK Setup Time Full IV 5.5 ns tHC Control3 to ↑CLK Hold Time Full IV 1.0 ns tHDS DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns tHRW RW(WR) to DTACK(RDY) Hold Time Full IV 8.0 ns tSAM Address/Data to RW(WR) Setup Time Full IV –0.5 ns tHAM Address/Data to RW(WR) Hold Time Full IV 7.0 ns tACC RW(WR) to DTACK(RDY) Low Delay Full IV 4 × tCLK 5 × tCLK 9 × tCLK ns MODE MNM Read Timing: tSC Control3 to ↑CLK Setup Time Full IV 4.0 ns tHC Control3 to ↑CLK Hold Time Full IV 2.0 ns tSAM Address to DS(RD) Setup Time Full IV 8.0 ns tHAM Address to Data Hold Time Full IV 0.0 ns tZD Data Three-State Delay Full IV 7.0 ns tACC DS(RD) to DTACK(RDY) Low Delay Full IV 8 × tCLK 10 × tCLK 13 × tCLK ns NOTES 2CLOAD = 40 pF on all outputs unless otherwise specified. 3Specification pertains to control signals: RW, ( WR), DS, (RD), CS. Specifications subject to change without notice.

REV. B AD6624 –9– ABSOLUTE MAXIMUM RATINGS * *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics 128-Lead Plastic Quad Flatpack: θJA = 41°C/W, No Airflow θJA = 39°C/W, 200 LFPM Airflow θJA = 37°C/W, 400 LFPM Airflow Thermal measurements made in the horizontal position on a 4-layer board. EXPLANATION OF TEST LEVELS I. 100% Production Tested. II. 100% Production Tested at 25 °C, and Sample Tested at Specified Temperatures. III. Sample Tested Only. IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at 25 °C, and Sample Tested at Temperature Extremes. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6624 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Package Model Temperature Range Package Description Option AD6624AS –40 °C to +70°C (Ambient) 128-Lead MQFP (Plastic Quad Flatpack) S-128-1 AD6624S/PCB Evaluation Board with AD6624 and Software

REV. B AD6624 –10– PIN CONFIGURATION 101 102 100 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) VSSIO INB6 INB7 INB8 INB9 VDDIO INB10 INB11 INB12 INB13 VDD EXPB2 EXPB1 EXPB0 DR3 VSS SDFE3 SDIN3 SDO3 SDFS3 SYNCD SYNCC SYNCB SYNCA VDD RESET VSS VDD DS(RD) DTACK/RDY RW(WR) VSS SDO2 SDFS2 SCLK2 DR1 SDFE1 VDD SDIN1 SDO1 SDFS1 SCLK1 VSSIO DR0 SDIV2 SDIV3 SBM0 CHIP_ID0 VSS CHIP_ID1 CHIP_ID2 CHIP_ID3 VSS INB5 INB4 INB3 INB2 INB1 VDD INB0 IENB LIB-B LIB-A VSS CLK EXPA0 EXPA1 EXPA2 VDD INA13 INA12 INA11 INA10 VDDIO INA9 INA8 INA7 INA6 VSSIO INA5 INA4 INA3 INA2 LIA-A VDDIO MODE VSSIO VSSIO TDI VDDIO VDDIO SCLK3 DR2 SDFE2 SDIN2 VSSIO SDFE0 SDIN0 SDO0 VDDIO SDFS0 SCLK0 SDIV0 SDIV1 VDD AD6624 INA1 INA0 IENA LIA-B VDD VSS TDO TMS TCLK TRST CS VSS

REV. B AD6624 –11– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Function 1, 12, 38, 50, 65, 76, 102, 113 VSS G Ground 2–6 INB[5:1] 1 IB Input Data (Mantissa) 7, 17, 32, 44, 54, 81, 96, 118 VDD P 2.5 V Supply 8I NB01 IB Input Data (Mantissa)—LSB

9 IENB2 I Input Enable—Input B

10 LIB-B O Level Indicator—Input B, Interleaved—Data B

11 LIB-A O Level Indicator—Input B, Interleaved—Data A

13 CLK I Input Clock

14–16 EXPA[0:2]

1 IA Input Data (Exponent)

18–21 INA[13:10] 1 IA Input Data (Mantissa) 22, 59, 71, 86, 108, 123 VDDIO P 3.3 V Supply 23–26 INA[9:6]

1 IA Input Data (Mantissa)

27, 39, 64, 91, 103, 128 VSSIO G Ground 28–31 INA[5:2] 1 IA Input Data (Mantissa) 33–34 INA[1:0] 1 IA Input Data (Mantissa)

35 IENA 2 I Input Enable—Input A

36 LIA-B O Level Indicator—Input A, Interleaved—Data B

37 LIA-A O Level Indicator—Input A, Interleaved—Data A

40 SYNCD

1 IA ll Sync Pins Go to All Four Output Channels

41 SYNCC 1 IA ll Sync Pins Go to All Four Output Channels

42 SYNCB 1 IA ll Sync Pins Go to All Four Output Channels

43 SYNCA 1 IA ll Sync Pins Go to All Four Output Channels

45 RESET IA ctive Low Reset Pin

46–49 D[7:4] I/O/T Bidirectional Microport Data 51–53 D[3:1] I/O/T Bidirectional Microport Data

55 D0 I/O/T Bidirectional Microport Data—LSB

56 DS(RD)I Active Low Data Strobe (Active Low Read)

57 DTACK(RDY)

2 O/T Active Low Data Acknowledge (Microport Status Bit)

58 RW( WR)I Read Write (Active Low Write)

60 MODE I Intel or Motorola Mode Select

61–63 A[2:0] I Microport Address Bus 66 CS

1 IC hip Select

67 TRST2 IT est Reset Pin

68 TCLK 1 IT est Clock Input

69 TMS 2 IT est Mode Select Input

70 TDO O/T Test Data Output

72 TDI 2 IT est Data Input

73–75 CHIP_ID[3:1] 1 IC hip ID Selector

77 CHIP_ID0 1 IC hip ID Selector—LSB

78 SBM0 1 I Serial Bus Master—Channel 0 Only

79–80 SDIV[3:2] 1 I Serial Clock Divisor—Channel 0 82–83 SDIV[1:0] 1 I Serial Clock Divisor—Channel 0

84 SCLK0 1 I/O Bidirectional Serial Clock—Channel 0

85 SDFS0 1 I/O Bidirectional Serial Data Frame Sync—Channel 0

87 SDO0 1 O/T Serial Data Output—Channel 0

88 SDIN0 1 I Serial Data Input—Channel 0

89 SDFE0 O Serial Data Frame End—Channel 0

90 DR0 O Output Data Ready Indicator—Channel 0

REV. B AD6624 –12– PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type Function

92 SCLK1 1 I/O Bidirectional Serial Clock—Channel 1

93 SDFS1 1 I/O Bidirectional Serial Data Frame Sync—Channel 1

94 SDO1 1 O/T Serial Data Output—Channel 1

95 SDIN1 1 I Serial Data Input—Channel 1

97 SDFE1 O Serial Data Frame End—Channel 1

98 DR1 O Output Data Ready Indicator—Channel 1

99 SCLK2 1 I/O Bidirectional Serial Clock—Channel 2

100 SDFS2 1 I/O Bidirectional Serial Data Frame Sync—Channel 2

101 SDO2 1 O/T Serial Data Output—Channel 2

104 SDIN2 1 I Serial Data Input—Channel 2

105 SDFE2 O Serial Data Frame End—Channel 2

106 DR2 O Output Data Ready Indicator—Channel 3

107 SCLK3 1 I/O Bidirectional Serial Clock—Channel 3

109 SDFS3 1 I/O Bidirectional Serial Data Frame Sync—Channel 3

110 SDO3 1 O/T Serial Data Output—Channel 3

111 SDIN3 1 I Serial Data Input—Channel 3

112 SDFE3 O Serial Data Frame End—Channel 3

114 DR3 O Output Data Ready Indicator—Channel 3

115–117 EXPB[0:2] 1 IB Input Data (Exponent) 119–122 INB[13:10] 1 IB Input Data (Mantissa) 124–127 INB[9:6] 1 IB Input Data (Mantissa) NOTES 1Pins with a pull-down resistor of nominal 70 k Ω. 2Pins with a pull-up resistor of nominal 70 k Ω. Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-State.

nels to be configured to emulate that AD6620 in diversity mode. taps can be computed. This naturally provides better filtering. duce a new filter computation pair. is about to reach full-scale with a particular input condition. quickly insert an attenuator that would prevent ADC overdrive. essary switching between states. Figure 23. Threshold Settings for LI the ADC and the switching time of the gain control element. Together, these two features provide seamless gain switching. hibit internal gain ranging from occurring in some instances. cause unnecessary gain changes. and four when the inputs are time-multiplexed). switching between gain settings.

to make the AD6624 exponent agree with the AD6600 RSSI. bit should always be set high for use with the AD6600. reducing the signal of interest relative to the quantization noise floor. the case when Exponent Offset is set to 6 since mod(8,8) = 0. to interface with gain-ranging ADCs other than the AD6600. RSSI(EXP) ranges to be used as opposed to the AD6600’s five. and the Input Enable (IEN). Both inputs are clocked by CLK. justified and the unused LSBs should be tied low. the 5-bit scale values stored in register 0x92, Bits 4–0 or Bits 9–5. tenuated input signal range. Exponent Invert bit should be 0. and no input scaling is used in the AD6624. Figure 24. Typical Interconnection of the AD6640 Fixed the AD6600. See the AD6600 data sheet for additional details. and rCIC2 is the rCIC scale register value (0x92 Bits 9–5 and 4–0).

RSSI = 4 correspond to the 0 dB point of the AD6624. Figure 25. Typical Interconnection of the AD6600 Gain- is better than –100 dBc for all output frequencies. calculated using the equation below. CLK* is the AD6624 master clock rate (CLK). *See NCO Mode Control section. the frequency hopping feature of this chip. and steady phase difference. basis. These are described below. The NCO in the front end of the AD6624 can be bypassed. pass band in prior analog stages or by other digital preprocessing. subsequent stages, phase dither is not needed. mance of the NCO. Amplitude dither is enabled by setting Bit 2. phase dither can be used together, separately, or not at all. ter will be the initiating point for the new frequency. There are four different modes of operation for the input enable. either of the two A or B Input Ports (see WB Input Select section). be configured to process the IEN signal in one of four modes.

for time division multiplexed applications. rate four times faster than the data. Figure 26. Fractional Rate Input Timing (4 × CLK) in and not once for each input clock. and not once for each input clock. connected to the selected filter channel. Channel B, 10 is Channel C, and 11 is Channel D. is not a multiple of the data rate to be used. equal to one. This implies that the rCIC2 decimates by 1 or more. by the fractional rate change (L/M). 80 MHz. The output rate of this stage is given by Equation 4. setting the decimation to 1/1. The frequency response of the rCIC2 filter is given by Equation 5. lowest attenuation) without creating an overflow condition.

REV. B AD6624 –19– where input_level is the largest fraction of full-scale possible at the input to the AD6624 (normally 1). The rCIC2 scale factor is always used whether or not the rCIC2 is bypassed. Moreover, there are two scale registers (rCIC2_LOUD[4:0] Bits 4–0 in x92), and (rCIC2_QUIET[4:0] Bits 9–5 in 0x92) that are used in conjunction with the computed S rCIC2 which determines the overall rCIC2 scaling. The S rCIC2 value must be summed w ith the values in each respective scale register and ExpOff, to determine the scale value that must be placed in the rCIC2 scale register. This number must be less than 32 or the interpolation and decimation rates must be adjusted to validate this equation. The ceil function denotes the next whole integer and the floor function denotes the previous whole integer. For example, the ceil(4.5) is 5 while the floor(4.5) is 4. The gain and passband droop of the rCIC2 should be calculated by the equations above, as well as the filter transfer equations that follow. Excessive passband droop can be compensated for in the RCF stage by peaking the passband by the inverse of the roll-off. scaled input IN ExpInv scaled input IN ExpInv Exp rCIC Exp rCIC mod( , ) mod( , ) =× = =× = −− + 72 8 (7) where: IN is the value of IN[15:0], Exp is the value of EXP[2:0], and rCIC2 is the value of the 0x92 (rCIC2_QUIET[4:0] and rCIC2_LOUD[4:0]) scale register. rCIC2 Rejection Table III illustrates the amount of bandwidth in percent of the data rate into the rCIC2 stage. The data in this table may be scaled to any other allowable sample rate up to 80 MHz in Single Channel Mode or 40 MHz in Diversity Channel Mode. The table can be used as a tool to decide how to distribute the decimation between rCIC2, CIC5, and the RCF. Table III. SSB rCIC2 Alias Rejection Table (f SAMP = 1) Bandwidth Shown in Percentage of fSAMP MCIC5/ LrCIC2 –50 dB –60 dB –70 dB –80 dB –90 dB –100 dB Example Calculations Goal: Implement a filter with an Input Sample Rate of 10 MHz requiring 100 dB of alias rejection for a ±7 kHz pass band. Solution: First determine the percentage of the sample rate that is represented by the passband. BW kHz MHz FRACTION =× =100 7 10 00 7. (8) Find the –100 dB column in Table III and look down this column for a value greater than or equal to your passband percentage of the clock rate. Then look across to the extreme left column and find the corresponding rate-change factor (MrCIC2/LrCIC2). Refer- ring to the table, notice that for a MrCIC2/LrCIC2 of 4, the frequency having –100 dB of alias rejection is 0.071 percent, which is slightly greater than the 0.07 percent calculated. Therefore, for this example, the maximum bound on r CIC2 rate change is 4. A higher chosen M rCIC2/LrCIC2 means less alias rejection than the 100 dB required. An MrCIC2/LrCIC2 of less than four would still yield the required rejection; however, the power consumption can be minimized by decimating as much as possible in this rCIC2 stage. Decima- tion in rCIC2 lowers the data rate, and thus reduces power consumed in subsequent stages. It should also be noted that there is more than one way to determine the decimation by 4. A decimation of 4 is the same as an L/M ratio of 0.25. Thus any integer combination of L/M that yields 0.25 will work (1/4, 2/8, or 4/16). However, for the best dynamic range, the simplest ratio should be used. For example, 1/4 gives better performance than 4/16. Decimation and Interpolation Registers rCIC2 decimation values are stored in register 0x90. This is a 12-bit register and contains the decimation portion less 1. The interpolation portion is stored in register 0x91. This 9-bit value holds the in terpolation less one. rCIC2 Scale Register 0x92 contains the scaling information for this section of the circuit. The primary function is to store the scale value computed in the sections above. Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to con- tain the scaling factor for the rCIC2 during conditions of strong signals. These five bits represent the rCIC2 scalar calculated above plus any external signal scaling with an attenuator. Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to con- tain the scaling factor for the rCIC2 during conditions of weak signals. In this register, no external attenuator would be used and is not included. Only the value computed above is stored in these bits. Bit 10 of this register is used to indicate the value of the external exponent. If this bit is set LOW, each external exponent repre- sents 6 dB per step as in the AD6600. If this bit is set to HIGH, each exponent represents a 12 dB step. S ceil M floor M L ML floor M L OL M L input level rCIC rCIC rCIC rCIC rCIC rCIC rCIC rCIC CIC rCIC rCIC SrCIC 22 2 2 2 =+  = × × log () _ (6)

REV. B AD6624 –20– Bit 11 of this register is used to invert the external exponent before internal calculation. This bit should be set HIGH for gain-ranging ADCs that use an increasing exponent to represent an increasing signal level. This bit should be set LOW for gain- ranging ADCs that use a decreasing exponent for representing an increasing signal level. In applications that do not require the features of the rCIC2, it may be bypassed by setting the L/M ratio to 1/1. This effectively bypasses all circuitry of the rCIC2 except the scaling, w hich is still effectual. FIFTH ORDER CASCADED INTEGRATOR COMB FILTER The third signal processing stage, CIC5, implements a sharper, fixed-coefficient, decimating filter than CIC2. The input rate to this filter is fSAMP2. The maximum input rate is given by Equa- tion 9. NCH equals two for Diversity Channel Real input mode; otherwise NCH equals one. In order to satisfy this equation, MCIC2 can be increased, NCH can be reduced, or f CLK can be increased (reference fractional rate input timing described in the Input Timing section). f f N SAMP CLK CH 2 ≤ (9) The decimation ratio, M CIC5, may be programmed from 2 to 32 (all integer values). The frequency response of the filter is given by Equation 10. The gain and passband droop of CIC5 should be calculated by these equations. Both parameters may be com- pensated for in the RCF stage. Hz z zS M CIC CIC () – –=× + (10) Hf Mf f f f S CIC SAMP SAMP CIC sin sin 2 5 5 π π The scale factor, SCIC5 is a programmable unsigned integer between 0 and 20. It serves to control the attenuation of the data into the CIC5 stage in 6 dB increments. For the best dynamic range, SCIC5 should be set to the smallest value possible (lowest attenuation) without creating an overflow condition. This can be safely accomplished using Equation 11, where OLrCIC2 is the largest fraction of full scale possible at the input to this filter stage. This value is output from the rCIC2 stage, then pipelined into the CIC5. S ceil M OL OL M OL CIC CIC rCIC CIC CIC S rCICCIC 52 5 5 2 2 5 =× () = () ×+ log ( ) – (11) The output rate of this stage is given by Equation 12. f f M SAMP SAMP CIC ≤ (12) CIC5 Rejection Table IV illustrates the amount of bandwidth in percentage of the clock rate that can be protected with various decimation rates and alias rejection specifications. The maximum input rate into the CIC5 is 80 MHz when the rC1C2 decimates by one. As in Table III, these are the 1/2 bandwidth characteristics of the CIC5. Note that the CI C5 stage can pr otect a much wider band than the CIC2 for any given rejection. Table IV. SSB CIC5 Alias Rejection Table (f SAMP2 = 1) MCIC5 –50 dB –60 dB –70 dB –80 dB –90 dB –100 dB This table helps to calculate an upper bound on decimation, MCIC5, given the desired filter characteristics. RAM COEFFICIENT FILTER The final signal processing stage is a sum-of-products decimat- ing filter with programmable coefficients (see Figure 27). The data memories I-RAM and Q-RAM store the 160 most recent complex samples from the previous filter stage with 20-bit reso- lution. The coefficient memory, CMEM, stores up to 256 coefficients with 20-bit resolution. On every CLK cycle, one tap for I and one tap for Q are calculated using the same coeffi- cients. The RCF output consists of 24-bit data bits.

Figure 27. RAM Coefficient Filter Block Diagram MRCF-1. The input rate to the RCF is fSAMP5. resources of several filters to be operated in parallel and shared. uses the value stored in this register to preload the RCF counter. stored in 0xA1 as an 8-bit number. the channel register within the AD6624 at address 0xA2. ten into the coefficient RAM. length of the data RAM may be used as the filter length (160 taps). values, the data RAM should be cleared upon initialization. adjustments can be made with the RCF Decimation Phase. the serial port configuration. See Serial Output Data Port section. care), the mode is 12 + 4, or 12-bit mantissa and 4-bit exponent. numbers would represent 0 regardless of the exponent used.

REV. B AD6624 –22– Bit 8 is the RCF bank select bit used to program the register. When this bit is 0, the lowest block of 128 is selected (Taps 0 through 127). When high, the highest block is selected (Taps 128 through 255). It should be noted that while the chip is computing filters, Tap 127 is adjacent to 128 and there are no paging issues. Bit 9 selects the origin of the input to each RCF. If Bit 9 is clear, the RCF input comes from the CIC5 normally associ- ated with the RCF. If, however, the bit is set, the input comes from CIC5 Channel 1. The only exception is Channel 1, which uses the output of CIC5 Channel 0 as its alternate. Using this feature, each RCF can either operate on its own channel data or be paired with the RCF of Channel 1. The RCF of Channel 1 can also be paired with Channel 0. This control bit is used with polyphase distributed filtering. If Bit 10 is clear, the AD6624 channel operates in normal mode. However, if Bit 10 is set, the RCF is bypassed to Channel BIST. See BIST (Built-In Self-Test) section below for more details. USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) The AD6624 includes two built-in test features to test the integ- rity of each channel. The first is a RAM BIST, which is intended to test the integrity of the high-speed random access memory within the AD6624. The second is Channel BIST, which is designed to test the integrity of the main signal paths of the AD6624. Each BIST function is independent of the other, meaning that each channel can be tested independently at the same time. RAM BIST The RAM BIST can be used to validate functionality of the on-chip RAM. This feature provides a simple pass/fail test, which will give confidence that the channel RAM is operational. The following steps should be followed to perform this test.

• The channels to be tested should be put into Sleep mode via the external address register 0x011.
• The RAM BIST Enable bit in the RCF register xA8 should be set high.
• Wait 1600 clock cycles.
• Register 0xA8 should be read back. If Bit 0 is high, the test is not yet complete. If Bit 0 is low, the test is complete and Bits 1 and 2 indicate the condition of the internal RAM. If Bit 1 is high, CMEM is bad. If Bit 2 is high, DMEM is bad. Table VII. BIST Register 0xA8 Register Value Coefficient MEM Data MEM XX1 Test Incomplete Test Incomplete

000 Pass Pass

010 Fail Pass

100 Pass Fail

110 Fail Fail

The Channel BIST is a thorough test of the selected AD6624 signal path. With this test mode, it is possible to use externally supplied vectors or an internal pseudo-random generator. An error signature register in the RCF monitors the output data of the channel and is used to determine if the proper data exits the RCF. If errors are detected, each internal block may be bypassed and another test can be run to debug the fault. The I and Q paths are tested independently. The following steps should be followed to perform this test.

• The channels to be tested should be configured as required for the application setting the decimation rates, scalars, and RCF coefficients.
• The channels should remain in the Sleep mode.
• The Start Hold-Off counter of the channels to be tested should be set to 1.
• Memory location 0xA5 and 0xA6 should be set to 0.
• The Channel BIST located at 0xA7 should be enabled by setting Bits 19–0 to the number of RCF outputs to observe.
• Bit 4 of external address register 5 should be set high to start the soft sync.
• Set the SYNC bits high for the channels to be tested.
• Bit 6 must be set to 0 to allow the user to provide test vectors. The internal pseudo-random number generator may also be used to generate an input sequence by setting Bit 7 high.
• An internal –FS sine can be inserted when Bit 6 is set to 1 and Bit 7 is cleared.
• When the SOFT_SYNC is addressed, the selected channels will come out of the Sleep mode and processing will occur.
• If the user is providing external vectors, the chip may be brought out of Sleep mode by one of the other methods, provided that either of the IEN inputs is inactive until the channel is ready to accept data.
• After a sufficient amount of time, the Channel BIST Signa- ture registers 0xA5 and 0xA6 will contain a numeric value that can be compared to the expected value for a known good AD6624 with the exact same configuration. If the values are the same, there is a very low probability that there is an error in the channel. CHIP SYNCHRONIZATION Two types of synchronization can be achieved with the AD6624. These are Start and Hop. Each is described in detail below. The synchronization is accomplished with the use of a shadow register and a hold-off counter. See Figure 28 for a simplis tic sche- matic of the NCO shadow register and NCO Freq Hold-Off counter to understand basic operation. Enabling the clock (AD6624 CLK) for the hold-off counter can occur with either a Soft_Sync (via the microport), or a Pin Sync (via any of the four AD6624 SYNC Pins A, B, C, and D). The functions that include shadow registers to allow synchronization include: 1. Start 2. Hop (NCO Frequency)

Figure 28. NCO Shadow Register and Hold-Off Counter by writing to the mode register controlling the sleep function.

1. To program a channel, it should first be set to Sleep mode

Counter (0x83) should be set to 1.

1. Set the appropriate Sleep bit low (Ext Address 3). This enables
2. Set the appropriate channels to Sleep mode (a hard reset
3. Note that the time RDY (Pin 57) goes high to when the NCO

Hold-Off Counter(s) (0x83) plus six master clock cycles.

1. Write the Start Update Hold-Off Counter(s) (0x83) to the
2. Write the Start bit and the Sync bit high (Ext Address 5).
3. This starts the Start Update Hold-Off Counter counting

down. The counter is clocked with the AD6624 CLK signal. ate channel(s) is set low to activate the channel(s). used to provide for very accurate synchronization channels. external signals is accomplished with the following method.

1. Set the appropriate channels to Sleep mode (a hard reset
2. Note that the time from when the SYNC pin goes high to
3. Write the Start Update Hold-Off Counter(s) (0x83) to the
4. Set the Start on Pin Sync bit and the appropriate Sync Pin

Enable high (Ext Address 4 ) (A, B, C, or D).

1. When the Sync pin is sampled high by the AD6624 CLK,

appropriate channel(s) is set low to activate the channel(s). (Pin Sync) as described below.

1. Set the NCO Freq Hold-Off counter to 0.
2. Load the appropriate NCO frequency. The new frequency

will be immediately loaded to the NCO. channels via microprocessor control.

REV. B AD6624 –27– Table VIII. Channel Address Memory Map Ch Address Register Bit Width Comments 00–7F Coefficient Memory (CMEM) 20 128 × 20-Bit Memory

80 CHANNEL SLEEP 1 0: SLEEP Bit from EXT_ADDRESS 3

81 Soft_Sync Control Register 2 1: Hop

0: Start

82 Pin_SYNC Control Register 3 2: First SYNC Only

1: Hop_En 0: Start_En

83 Start Hold-Off Counter 16 Start Hold-Off Value

84 NCO Frequency Hold-Off Counter 16 NCO_FREQ Hold-Off Value

85 NCO Frequency Register 0 16 NCO_FREQ[15:0]

86 NCO Frequency Register 1 16 NCO_FREQ[31:16]

87 NCO Phase Offset Register 16 NCO_PHASE[15:0]

88 NCO Control Register 9 8–7: SYNC Input Select[1:0]

6: WB Input Select B/A 5–4: Input Enable Control 11: Clock On IEN Transition to Low 10: Clock On IEN Transition to High 01: Clock On IEN High 00: Mask On IEN Low 3: Clear Phase Accumulator On HOP 2: Amplitude Dither 1: Phase Dither 0: Bypass (A-Input -> I-Path, B -> Q) 89–8F Unused 90 rCIC2 Decimation–1 12 M rCIC2–1 91 rCIC2 Interpolation–1 9 L rCIC2–1 92 rCIC2 Scale 12 11: Exponent Invert 10: Exponent Weight 9–5: rCIC2_QUIET[4:0] 4–0: rCIC2_LOUD[4:0]

93 Reserved 8 Reserved (Must Be Written Low)

94 CIC5 Decimation–1 8 M

CIC5–1

95 CIC5 Scale 5 4–0: CIC5_SCALE[4:0]

96 Reserved 8 Reserved (Must Be Written Low)

97–9F Unused A0 RCF Decimation–1 8 M RCF–1 A1 RCF Decimation Phase 8 P RCF A2 RCF Number of Taps–1 8 N TAPS–1 A3 RCF Coefficient Offset 8 CO RCF A4 RCF Control Register 11 10: RCF Bypass BIST 9: RCF Input Select (Own 0, Other 1) 8: Program RAM Bank 1/0 7: Use Common Exponent 6: Force Output Scale 5–4: Output Format 1x: Floating Point 12 + 4 01: Floating Point 8 + 4 00: Fixed Point 3–0: Output Scale

REV. B AD6624 –29– Regardless of whether the chip is a Serial Bus Master or is in Serial Slave mode, the AD6624 Serial Port functions are identi- cal except for the source of the SCLK and SDFS pins. SCLK SCLK is an output when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3) is high; SCLK is an input when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3) is low in serial slave mode. In either case, the SDIN input is sampled on the falling edge of SCLK and all outputs are switched on the rising edge of SCLK. The SDFS pin is sampled on the falling edge of SCLK. This allows the AD6624 to recognize the SDFS in time to initiate a frame on the very next SCLK rising edge. The maximum speed of this port is 80 MHz. SDIN SDIN is the Serial Data Input. Serial Data is sampled on the falling edge of SCLK. This pin is used in the serial control mode to write the internal control registers of the AD6624. These activities are described later in the Serial Port Control section. The Serial Input Port is self-framing and bears no fixed relationship to either SDFS or SDFE. SDO SDO is the Serial Data Output. Serial output data is shifted on the rising edge of SCLK. On the very next SCLK rising edge after an SDFS, the MSB of the I data from the channel is shifted. On every subsequent SCLK edge, a new piece of data is shifted out on the SDO pin until the last bit of data is shifted out. The last bit of data shifted is the LSB of the Channel’s Q data. SDO is three-stated when the serial port is outside its time-slot. This allows the AD6624 to share the SDIN of a DSP with other AD6624s or other devices. SDFS SDFS is the Serial Data Frame Sync signal. SDFS is an output when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3) is high in the Master mode. SDFS is an input when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3) is low in the Slave mode. SDFS is sampled on the falling edge of SCLK. When SBM is sampled low, the AD6624 serial port will func- tion as a serial slave. In this mode, the port is silent until the DSP issues a frame sync. When the AD6624 detects an SDFS on the falling edge of a DSP-generated serial clock, on the next rising edge of the serial clock, the AD6624 enables the output driver and shifts the MSB of the I word. Data is shifted until the LSB of the Q word has been sent. On the LSB of the Q word, the AD6624 generates an SDFE, which can be cascaded to the next SDFS on a TDM serial chain or to the DSP to indicate that the last bit has been sent. When SBM is sampled high, the chip functions as a serial bus master. In this mode, the AD6624 is responsible for generating serial control data. Three modes of that operation are set via channel address 0xA9 Bits 8–7. Each behaves a little differently, as detailed below. In the first mode (0xA9 Bits 8–7:00), the SDFS is valid for one complete clock cycle prior to the data shift. On the next clock cycle, the AD6624 begins shifting serial data. In the second mode, (0xA9 Bits 8–7:01), the SDFS is high for the entire time that valid bits are being shifted. The SDFS bit goes high co ncurrent with the first bit shifted out of the AD6624 and returns low after the last bit is shifted out of the AD6624. In the third mode (0xA9 Bits 8–7:10), the SDFS bit goes high as in the first mode, one clock cycle prior to the actual data. However, a second SDFS is inserted one clock cycle prior to the shift of the first Q bit. In this manner, each word out of the AD6624 is accom- panied by an SDFS. SDFE SDFE is the Serial Data Frame End output. SDFE will go high during the last SCLK cycle (LSB of the Q word) of an active time-slot. The SDFE output of a master AD6624 channel can be tied to the input SDFS of an AD6624 channel in Serial Slave mode in order to provide a hard-wired time-slot scenario. When the last bit of SDO data is shifted out of the Master AD6624, the SDFE signal will be driven high by the same SCLK rising edge on which this bit is clocked out. On the falling edge of this SCLK cycle, the slaved serial port will sample its SDFS signal, which is hard-wired to the SDFE of the master. On the very next SCLK rising edge, data of the slave will start shifting. There will be no rest between the time slots of the master and slave. Serial Word Length Bits 6–5 of register 0xA9 determine the length of the serial word (I or Q). If these bits are set to ‘00,’ each word is 12 bits (12 bits for I and 12 more bits for Q). If set to ‘01,’ the serial words are 16 bits wide, and if set to ‘1x’ (x is don’t care), the word length is 24 bits. SDFS Mode Bits 8–7 of register 0xA9 determine how the SFDS behaves in Serial Bus Master mode. In Serial Slave mode, the frame sync must be formatted by programming Bits 8–7 to ‘00.’ The first mode is set by programming Bits 8–7 to ‘00’. In this mode, the SDFS is valid for one complete clock cycle prior to the data shift. On the next clock cycle, the AD6624 begins shift- ing out the digitally processed data stream. Depending on the bit precision of the serial configuration, either 12, 16, or 24 bits of I data are shifted out, followed by 12, 16, or 24 bits of Q data. The second mode is set by programming Bits 8–7 to ‘01.’ In this mode, the SDFS is high for the entire time that valid bits are being shifted. The SDFS bit goes high concurrent with the first bit shifted out of the AD6624 and goes low after the last bit has been shifted. The third mode is set by programming Bits 8–7 to ‘1x’ (x is don’t care). In this mode, the SDFS bit goes high as in the first mode, one clock cycle prior to the actual data. However, a sec- ond SDFS is inserted one clock cycle prior to the shift of the first Q bit. In this manner, each word out of the AD6624 is accompa- nied by an SDFS. Mapping RCF Data to the BIST Registers If Bit 9 of 0xA9 is set, RCF data is routed to the BIST registers. This allows the filter results to be read from the mi croprocessor port. This can be useful when the data must be accessed via a parallel port and the decimation rate is sufficiently high that throughput does not become an issue. 0x00–0x7F: Coefficient Memory (CMEM) This is the Coefficient Memory (CMEM) used by the RCF. It is memory mapped as 128 words by 20 bits. A second 128 words of RAM may be accessed via this same location by writing Bit 8 of the RCF control register high at channel address 0xA4. The filter calculated will always use the same coefficients for I and Q. By using memory from both of these 128 blocks, a filter up to 160 taps can be calculated. Mul tiple filters can be l oaded and selected with a single internal access to the Coefficient Offset Register at channel address 0xA3.

REV. B AD6624 –30– 0x80: Channel Sleep Register This register contains the SLEEP bit for the channel. When this bit is high, the channel is placed in a low power state. When this bit is low, the channel processes data. Note that in serial slave mode, the RESET pin needs to be held low for several SCLK cycles to ensure that it will program this bit high. This bit can also be set by accessing the SLEEP register at external address 3. When the external SLEEP register is accessed, all four channels are accessed simultaneously and the SLEEP bits of the channels are set appropriately. 0x81: Soft_SYNC Register This register is used to initiate SYNC events through the micro- port. If the Hop bit is written high, the Hop Hold-Off Counter at address 0x84 is loaded and begins to count down. When this value reaches one, the NCO Frequency register used by the NCO accumulator is loaded with the data from channel addresses 0x85 and 0x86. When the Start bit is set high, the S tart Hold-Off Counter is loaded with the value at address 0x83 and begins to count down. When this value hits one, the Sleep bit in address 0x80 is dropped low and the channel is started. 0x82: Pin_SYNC Register This register is used to control the functionality of the SYNC pins. Any of the four SYNC pins can be chosen and monitored by the channel. The channel can be configured to initiate either a Start or Hop SYNC event by setting the Hop or Start bit high. These bits function as enables so that when a SYNC pulse occurs either the Start or Hop Hold-Off Counters are activated in the same manner as with a Soft_SYNC. 0x83: Start Hold-Off Counter The Start Hold-Off Counter is loaded with the value written to this address when a Start_Sync is initiated. It can be initiated by either a Soft_SYNC or Pin_SYNC. The counter begins dec- rementing and when it reaches a value of one, the chan nel is brought out of SLEEP and begins processing data. If the chan- nel is already running, the phase of the filters is adjusted such that multiple AD6624s can be synchronized. A periodic pulse on the SYNC pin can be used in this way to adjust the timing of the filters with the resolution of the ADC sample clock. If this register is written to a one, the Start will occur immediately when the SYNC comes into the channel. If it is written to a zero, no SYNC will occur. 0x84: NCO Frequency Hold-Off Counter The NCO Frequency Hold-Off Counter is loaded with the value written to this address when either a Soft_SYNC or Pin_SYNC comes into the channel. The counter begins counting down so that when it reaches one, the NCO Frequency word is updated with the values of addresses 0x85 and 0x86. This is known as a Hop or Hop_SYNC. If this register is written to a one, the NCO Frequency will be updated immediately when the SYNC comes into the channel. If it is written to a zero, no HOP will occur. NCO HOPs can be either phase continuous or nonphase con- tinuous, depending upon the state of Bit 3 of the NCO control register at channel address 0x88. When this bit is low, the Phase Accumulator of the NCO is not cleared, but starts to add the new NCO Frequency word to the accumulator as soon as the SYNC occurs. If this bit is high, the Phase Accumulator of the NCO is cleared to zero and the new word is then accumulated. 0x85: NCO Frequency Register 0 This register represents the 16 LSBs of the NCO Frequency word. These bits are shadowed and are not updated to the regis- ter used for the processing until the channel is either brought out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued. In the latter two cases, the register is updated when the Fre- quency Hold-Off Counter hits a value of one. If the Frequency Hold-Off Counter is set to one, the register will be updated as soon as the shadow is written. 0x86: NCO Frequency Register 1 This register represents the 16 MSBs of the NCO Frequency word. These bits are shadowed and are not updated to the register used for the processing until the channel is either brought out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued. In the latter two cases, the register is updated only when the Frequency Hold-Off Counter hits a value of one. If the Fre quency Hold- Off Counter is set to one, the register will be updated as soon as the shadow is written. 0x87: NCO Phase Offset Register This register represents a 16-bit phase offset to the NCO. It can be interpreted as values ranging from 0 to just under 2 π. 0x88: NCO Control Register This 9-bit register controls features of the NCO and the channel. The bits are defined below. For more detail, the NCO section should be consulted. Bits 8–7 of this register choose which of the four SYNC pins are used by the channel. The SYNC pin selected can be used to initiate a START, HOP, or timing adjustment to the channel. The Synchronization section of this data sheet provides more details on this. Bit 6 of this register defines whether the A or B Input Port is used by the channel. If this bit is low, the A Input Port is selected; if this bit is high, the B Input Port is selected. Each input port consists of a 14-bit input mantissa (INx[ 13:0]), a 3-bit exponent (EXPx[2:0]), and an input enable pin, IENx. The x represents either A or B. Bits 5–4 determine how the sample clock for the channel is derived from the high-speed CLK signal. There are four pos- sible choices. Each is defined below but for further detail, the NCO section of the data sheet should be consulted. When these bits are 00, the input sample rate (f SAMP) of the channel is equal to the rate of the high-speed CLK signal. When IEN is low, the data going into the channel is masked to 0. This is an appropriate mode for TDD systems where the receiver may wish to mask off the transmitted data yet still remain in the proper phase for the next receive burst. When these bits are 01, the input sample rate is determined by the fraction of the rising edges of CLK on which the IEN i nput is high. For example, if IEN toggles on every rising edge of CLK, then the IEN signal will only be sampled high on one out of every two rising edges of CLK. This means that the input sample rate f SAMP will be 1/2 the CLK rate. When these bits are 10, the input sample rate is determined by the rate at which the IEN pin toggles. The data that is captured on the rising edge of CLK after IEN transitions from low to

REV. B AD6624 –31– high is processed. When these bits are 11, the accumulator and sample CLK are determined by the rate at which the IEN pin toggles. The data that is captured on the rising edge of CLK after IEN transitions from high to low is processed. For example, Control Modes 10 and 11 can be used to allow interleaved data from either the A or B Input Ports and then assigned to the respec- tive channel. The IEN pin selects the data such that a channel could be configured in Mode 10 and another could be config- ured in Mode 11. Bit 3 determines whether or not the phase accumulator of the NCO is cleared when a Hop occurs. The Hop can originate from either the Pin_SYNC or Soft_SYNC. When this bit is set to 0, the Hop is phase continuous and the accumulator is not cleared. When this bit is set to 1, the accumulator is cleared to 0 before it begins accumulating the new frequency word. This is appropriate when multiple channels are hopping from different frequencies to a common frequency. Bits 2–1 control whether or not the dithers of the NCO are acti- vated. The use of these features is heavily determined by the system constraints. Consult the NCO section of the data sheet for more detailed information on the use of dither. Bit 0 of this register allows the NCO Frequency translation stage to be bypassed. When this occurs, the data from the A Input Port is passed down the I path of the channel and the data from the B Input Port is passed down the Q path of the channel. This allows a real filter to be performed on baseband I and Q data. 0x90: rCIC2 Decimation–1 (M rCIC2–1) This register is used to set the decimation in the rCIC2 filter. The value written to this register is the decimation minus one. The rCIC2 decimation can range from 1 to 4096 depending upon the interpolation of the channel. The decimation must always be greater than the interpolation. M rCIC2 must be chosen larger than LrCIC2 and both must be chosen such that a suitable rCIC2 Scalar can be chosen. For more details, consult the rCIC2 section. 0x91: rCIC2 Interpolation–1 (L rCIC2–1) This register is used to set the interpolation in the rCIC2 filter. The value written to this register is the interpolation minus one. The rCIC2 interpolation can range from 1 to 512 depending upon the decimation of the rCIC2. There is no timing error associated with this interpolation. See the rCIC2 section of the data sheet for further details. 0x92: rCIC2 Scale The rCIC2 scale register is used to provide attenuation to com- pensate for the gain of the rCIC2 and to adjust the linearization of the data from the floating- point input. The use of this scale register is influenced by both the rCIC2 growth and floating- point input port considerations. The rCIC2 section should be consulted for details. The rCIC2 scalar has been combined with the Exponent Offset and will need to be handled appropriately in both the Input Port and rCIC2 sections. Bit 11 determines the polarity of the exponent. Normally, this bit will be cleared unless an ADC such as the AD6600 is used, in which case, this bit will be set. Bit 10 determines the weight of the exponent word associated with the input port. When this bit is low, each exponent step is considered to be worth 6.02 dB. When this bit is high, each exponent step is considered to be worth 12.02 dB. Bits 9–5 are the actual scale values used when the Level Indica- tor, LI pin associated with this channel is active. Bits 4–0 are the actual scale values used when the Level Indica- tor, LI pin associated with this channel is inactive. 0x93: Reserved. (Must be written low.) 0x94: CIC5 Decimation–1 (M CIC5–1) This register is used to set the decimation in the CIC5 filter. The value written to this register is the decimation minus one. Although this is an 8-bit register, the decimation is usually lim- ited to values between 1 and 32. Decimations higher than 32 would require more scaling than the CIC5’s capability. 0x95: CIC5 Scale The CIC5 scale factor is used to compensate for the growth of the CIC5 filter. Consult the CIC5 section for details. 0x96: Reserved. (Must be written low.) 0xA0: RCF Decimation–1 (M RCF–1) This register is used to set the decimation of the RCF stage. The value written is the decimation minus one. Although this is an 8-bit register that allows decimation up to 256 for most filtering sce- narios, the decimation should be limited to values between 1 and 32. Higher decimations are allowed, but the alias protection of the RCF may not be acceptable for some applications. 0xA1: RCF Decimation Phase (P RCF) This register allows any one of the M RCF phases of the filter to be used and can be adjusted dynamically. Each time a filter is started, this phase is updated. When a channel is synchronized, it will retain the phase setting chosen here. This can be used as part of a timing recovery loop with an external processor or can allow multiple RCFs to work together while using a single RCF pair. The RCF section of the data sheet should be consulted for further details. 0xA2: RCF Number of Taps Minus One (N RCF–1) The number of taps for the RCF filter minus one is written here. 0xA3: RCF Coefficient Offset (CO RCF) This register is used to specify which section of the 256-word coefficient memory is used for a filter. It can be used to select among multiple filters that are loaded into memory and refer- enced by this pointer. This register is shadowed and the filter pointer is updated every time a new filter is started. This allows the Coefficient Offset to be written even while a filter is being computed with disturbing operation. The next sample that comes out of the RCF will be with the new filter. 0xA4: RCF Control Register The RCF Control Register is an 11-bit register that controls general features of the RCF as well as output formatting. The bits of this register and their functions are described below. Bit 10 bypasses the RCF filter and sends the CIC5 output data to the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 data can be accessed from this register if Bit 9 of the Serial Control Register at channel address 0xA9 is set. Bit 9 of this register controls the source of the input data to the RCF. If this bit is 0, the RCF processes the output data of its own channel. If this bit is 1, it processes the data from the CIC5 of another channel. The CIC5 that the RCF is connected to when this bit is 1 is shown in Table IX. This can be used to allow multiple RCFs to be used together to process w ider bandwidth channels. See the Multiprocessing section of the data sheet for further details.

REV. B AD6624 –32– Table IX. RCF Input Configurations Channel RCF Input Source when Bit 9 is 1 Bit 8 is used as an extra address to allow a second block of 128 words of CMEM to be addressed by the channel addresses at 0x00–0x7F. If this bit is 0, the first 128 words are written and if this bit is 1, a second 128 words is written. This bit is only used to program the Coefficient Memory. It is not used in any way by the processing and filters longer than 128 taps can be performed. Bit 7 is used to help control the output formatting of the AD6624’s RCF data. This bit is only used when the 8 + 4 or 12 + 4 floating- point modes are chosen. These modes are enabled by Bits 5 and 4 of this register below. When this bit is 0, the I and Q output exponents are determined separately based on their i ndividual magnitudes. When this bit is 1, the I and Q data is a complex floating-point number where I and Q use a single exponent that is determined based on the maximum magnitude of I or Q. Bit 6 is used to force the Output Scale Factor in Bits 3–0 of this register to be used to scale the data even when one of the Float- ing Point Output modes is used. If the number is too large to represent with the Output Scale chosen, the mantissas of the I and Q data clip and do not overflow. Bits 5 and 4 choose the output formatting option used by the RCF data. The options are defined in Table X and are dis- cussed further in the Output Format section of the data sheet. Table X. Output Formats Bit Values Output Option 1x 12-Bit Mantissa and 4-Bit Exponent (12 + 4) 01 8-Bit Mantissa and 4-Bit Exponent (8 + 4)

00 Fixed-Point Mode

Bits 3–0 of this register represent the Output Scale Factor of the RCF. They are used to scale the data when the output format is in fixed-point mode or when the Force Exponent bit is high. 0xA5: BIST Register for I This register serves two purposes. The first is to allow the com- plete functionality of the I data path in the channel to be tested in the system. The BIST section of the data sheet should be consulted for further details. The second function is to provide access to the I output data through the microport. To accom- plish this, the Map RCF data to BIST bit in the Serial Port Control register, 0xA9, should be set high. Sixteen-bits of I data can then be read through the microport in either the 8 + 4, 12 + 4, 12-bit linear or 16-bit linear output modes. This data may come from either the formatted RCF output or the CIC5 output. 0xA6: BIST Register for Q This register serves two purposes. The first is to allow the com- plete functionality of Q data path in the channel to be tested in the system. The BIST section of the data sheet should be con- sulted for further details. The second function is to provide access to the Q output data through the microport. To accomplish this, the Map RCF data to BIST bit in the Serial Port Control regis- ter, 0xA9, should be set high. Sixteen bits of Q data can then be read through the microport in either the 8 + 4, 12 + 4, 12-bit linear, or 16-bit linear output modes. This data may come from either the formatted RCF output or the CIC5 output. 0xA7: BIST Control Register This register controls the number of outputs of the RCF or CIC filter that are observed when a BIST test is performed. The BIST signature registers at addresses 0xA5 and 0xA6 will observe this number of outputs and then terminate. The loading of these registers also starts the BIST engine running. Details of how to utilize the BIST circuitry are defined in the BIST section of the data sheet. 0xA8: RAM BIST Control Register This register is used to test the memories of the AD6624 should they ever be suspected of a failure. Bit 0 of this register is written with a one when the channel is in SLEEP and the user waits for 1600 CLKs and then polls the bits. If Bit 1 is high, the CMEM failed the test; if Bit 2 is high, the data memory used by the RCF failed the test. 0xA9: Serial Port Control Register This register controls the serial port of the AD6624 and, along with the RCF control register, it helps to determine the out- put format. Bit 9 of this register allows the RCF or CIC5 data to be mapped to the BIST registers at addresses 0xA5 and 0xA6. When this bit is 0, the BIST register is in signature mode and ready for a self-test to be run. When this bit is 1, the output data from the RCF after formatting or the CIC5 data is mapped to these registers and can be read through the microport. In addition, when this bit is high, the DR pin for the channel delivers a

1 CLK cycle wide pulse that can be used to synchronize the

host processor with the AD6624. This signal is a 1 SCLK cycle wide pulse when this bit is 0. Bits 8 and 7 control the output format of the SDFS pulse. When these bits are 00, there is a single SCLK cycle wide pulse for the I and Q data. When these bits are 01, the SDFS signal is high for all of the bits shifted during the serial frame. When these bits are 10 or 11, there are two SDFS pulses that are each 1 SCLK cycle wide. One pulse precedes the I word of data and the second precedes the Q word of data. When a serial port is configured as a serial slave, it should be in the first mode with these bits set to 00. Bits 6 and 5 determine the serial word length used by the serial port. If these bits are 00, the serial ports use 12-bit words and shift 12 bits of I followed by 12 bits of Q with each shifted MSB first. If these bits are 01, the serial ports use 16-bit words and shift 16 bits of I followed by 16 bits of Q with each shifted MSB first. If these bits are 1x, the serial ports use 24-bit words and shift 24 bits of I followed by 24 bits of Q with each shifted MSB first. When the fixed point output option is chosen from the RCF control register, these bits also set the rounding correctly in the output formatter of the RCF. Bit 4 of this register controls whether the Serial Port is a master or slave. This register powers up low so that the serial port is a slave in order to avoid contention problems on the output driv- ers. The serial port for channel 0 does not use this bit. The master/slave status of Serial Port 0 is set by the SBM0 pin. Bits 3–0 control the rate of the SCLK signal when the channel is master. This four-bit bus can set the SCLK as a division of the master CLK from 1 to 16 with approximately a 50% duty cycle.

REV. B AD6624 –33– The SCLK can be generated and run up to a maximum of 80 MHz. The serial division bits from this register are not used for serial port 0. The external SDIV [3:0] pins are used to determine this for Serial Port 0. MICROPORT CONTROL The AD6624 has an 8-bit microprocessor port and four serial input ports. The use of each of these ports is described sepa- rately below. The interaction of the ports is then described. The microport interface is a multimode interface that is designed to give flexibility when dealing with the host processor. There are two modes of bus operation: Intel nonmultiplexed mode (INM), and Motorola nonmultiplexed mode (MNM). The mode is selected based on host processor and which mode is best suited to that processor. The microport has an 8-bit data bus (D[ 7:0]), 3-bit address bus (A[2:0]), three control pins lines ( CS, DS or RD, RW or WR), and one status pin ( DTACK or RDY). The functionality of the control signals and status line changes slightly, depending upon the mode that is chosen. Refer to the timing d iagrams and the following descriptions for details on the operation of both modes. External Memory Map The External Memory Map is used to gain access to the Channel Address Space described previously. The 8-bit data and address registers referenced by the external interface registers can be seen in Table XI. (These registers are collectively referred to as the External Interface Registers since they control all accesses to the Channel Address space as well as global chip functions.) The use of each of these individual registers is described below in detail. It should be noted that the Serial Control interface to Chan- nel 0 has the same memory map as the microport interface and can carry out exactly the same functions, although at a slower rate. Access Control Register (ACR) The Access Control Register serves to define the channel or chan- nels that receive an access from the microport or Serial Port 0. Bit 7 of this register is the autoincrement bit. If this bit is a 1, the CAR register described below will increment its value after every access to the channel. This allows blocks of address s pace such as Coefficient Memory to be initialized more efficiently. Bit 6 of the register is the broadcast bit and determines how Bits 5–2 are interpreted. If broadcast is 0, Bits 5–2, which are referred to as instruction bits (Instruction [3:0]), are com pared with the CHIP_ID [3:0] pins. The instruction that matches the CHIP_ID [3:0] pins will determine the access. This allows up to 16 chips to be connected to the same port and memory mapped without external logic. This also allows the same serial port of a host processor to configure up to 16 chips. If the broadcast bit is high, the Instruction [3:0] word allows multiple AD6624 chan- nels and/or chips to be configured simultaneously, inde pendent of the CHIP_ID[3:0] pins. Ten possible instructions are defined in Table XII. This is useful for smart antenna systems where multiple channels listening to a single antenna or carrier can be simultaneously configured. The x(s) in the table represent “don’t cares” in the digital decoding. Table XI. External Memory Map A[2:0] Name Comment

111 Access Control Register (ACR) 7: Auto Increment

6: Broadcast 5–2: Instruction[3:0] 1–0: A[9:8]

110 Channel Address Register (CAR) 7–0: A[7:0]

101 SOFT_SYNC Control Register

(Write Only) 7: PN_EN 6: Test_MUX_Select 5: Hop 4: Start 3: SYNC 3 2: SYNC 2 1: SYNC 1 0: SYNC 0

100 PIN_SYNC Control Register

(Write Only) 7: Toggle IEN for BIST 6: First SYNC Only 5: Hop_En 4: Start_En 3: SYNC_EN 3 2: SYNC_EN 2 1: SYNC_EN 1 0: SYNC_EN 0

011 SLEEP

(Write Only) 7–6: Reserved 5: Access Input Port Control Registers 4: Serial Read 0 3: SLEEP 2: SLEEP 2 1: SLEEP 1 0: SLEEP 0

010 Data Register 2 (DR2) 7–4: Reserved

3–0: D [19:16]

001 Data Register 1 (DR1) 15–8: D [15:8]

000 Data Register 0 (DR0) 7–0: D [7:0]

Table XII. Microport Instructions Instruction Comment 0000 All chips and all channels will get the access. 0001 Channel 0, 1, 2 of all chips will get the access. 0010 Channel 1, 2, 3 of all chips will get the access. 0100 All chips will get the access. *

1000 All chips with Chip_ID[3:0] = xxx0 will get

the access.*

1001 All chips with Chip_ID[3:0] = xxx1 will get

the access.*

1100 All chips with Chip_ID[3:0] = xx00 will get

the access.*

1101 All chips with Chip_ID[3:0] = xx01 will get

the access.*

1110 All chips with Chip_ID[3:0] = xx10 will get

the access.*

1111 All chips with Chip_ID[3:0] = xx11 will get

the access.* *A[9:8] bits control which channel is decoded for the access.

REV. B AD6624 –34– External Memory Map When broadcast is enabled (Bit 6 set high), readback is not valid because of the potential for internal bus contention. Therefore, if readback is subsequently desired, the broadcast bit should be set low. Bits 1–0 of this register are address bits that decode which of the four channels are being accessed. If the Instruction bits decode an access to multiple channels, these bits are ignored. If the Instruction decodes an access to a subset of chips, the A[9:8] bits will otherwise determine the channel being accessed. Channel Address Register (CAR) This register represents the 8-bit internal address of each channel. If the autoincrement bit of the ACR is 1, this value will be incre- mented after every access to the DR0 register, which will in turn access the location pointed to by this address. The Channel Address register cannot be read back while the broadcast bit is set high. SOFT_SYNC Control Register External Address [5] is the SOFT_SYNC control register and is write only. Bits 0–3 of this register are the SOFT_SYNC control bits. These pins may be written to by the controller to initiate the synchro- nization of a selected channel. Although there are four inputs, these do not necessarily go to the channel of the same number. This is fully configurable at the channel level as to which bit to look at. All four channels may be configured to synchronize from a single position, or they may be paired or all independent. Bit 4 determines if the synchronization is to apply to a chip start. If this bit is set, a chip start will be initiated. Bit 5 determines if the synchronization is to apply to a chip hop. If this bit is set, the NCO frequency will be updated when the SOFT_SYNC occurs. Bit 6 configures how the internal databus is configured. If this bit is set low, the internal ADC databuses are configured nor- mally. If this bit is set, the internal test signals are selected. The internal test signals are configured in Bit 7 of this register. Bit 7 if set clear, a negative full-scale signal is generated and made available to the internal databus. If this bit is high, inter- nal pseudo-random sequence generator is enabled and this data is available to the internal databus. The combined functions of Bits 6 and 7 facilitate verification of a given filter design and in conjunction with the MISR registers, allow for detailed in-system chip testing. In conjunction with the JTAG test board, very high levels of chip verification can be done du ring system test, in both the factory and field. PIN_SYNC Control Register External Address [4] is the PIN_SYNC control register and is write only. Bits 0–3 of this register are the SYNC_EN control bits. These pins may be written to by the controller to allow pin synchroni- zation of a selected channel. Although there are four inputs, these do not necessarily go to the channel of the same number. This is fully configurable at the channel level as to which bit to look at. All four channels may be configured to synchronize from a single position, or they may be paired or all independent. Bit 4 determines if the synchronization is to apply to a chip start. If this bit is set, a chip start will be initiated PIN_SYNC occurs. Bit 5 determines if the synchronization is to apply to a chip hop. If this bit is set, the NCO Frequency will be updated when the PIN_SYNC occurs. Bit 6 is used to ignore repetitive synchronization signals. In some applications, this signal may occur periodically. If this bit is clear, each PIN_SYNC will restart/hop the channel. If this bit is set, only the first occurrence will cause the chip to take action. Bit 7 is used with Bits 6 and 7 of external address 5. When this bit is cleared, the data supplied to the internal databus simulates a normal ADC. When this bit is set, the data supplied is in the form of a time-multiplexed ADC such as the AD6600 (this allows the equivalent of testing in the 4-channel input mode). Internally, when set, this bit forces the IEN pin to toggle as if it were driven by the A/B signal of the AD6600. SLEEP Control Register External Address [3] is the sleep register. Bits 3–0 control the state of each of the channels. Each bit corre- sponds to one of the possible RSP channels within the device. If this bit is cleared, the channel operates normally. However, when this bit is set, the indicated channel enters a low-power sleep mode. Table XIII. Memory Map for Input Port Control Registers Ch Address Register Bit Width Comments

00 Lower Threshold A 10 9–0: Lower Threshold for Input A

01 Upper Threshold A 10 9–0: Upper Threshold for Input A

02 Dwell Time A 20 19–0: Minimum Time below Lower Threshold A

03 Gain Range A Control Register 5 4: Output Polarity LIA-A and LIA-B

3: Interleaved Channels 2–0: Linearization Hold-Off Register

04 Lower Threshold B 10 9–0: Lower Threshold for Input B

05 Upper Threshold B 10 9–0: Upper Threshold for Input B

06 Dwell Time B 20 19–0: Minimum Time below Lower Threshold B

07 Gain Range B Control Register 5 4: Output Polarity LIB-A and LIB-B

3: Interleaved Channels 2–0: Linearization Hold-Off Register

REV. B AD6624 –35– Bit 4 causes the normal RSP data on serial channel 0 to be replaced with read access data. This allows reading the internal registers over the serial bus. It should be noted that in the mode, any RSP data will be superceded by internal access data. Bit 5 allows access to the Input Control Port Registers at channel addresses 00-07. When this bit is set low, the normal memory map is accessed. However, when this bit is set, it allows access to the Input Port Control Registers. Access to these registers allows the lower and upper thresholds to be set along with dwell time and other features. When this bit is set, the value in exter- nal address 6 (CAR) points to the memory map for the Input Port Control Registers instead of the normal memory map. See Input Port Control Registers below. Bits 6–7 are reserved and should be set low. Data Address Registers External Address [2-0] form the data registers DR2, DR1, and DR0 respectively. All internal data words have widths that are less than or equal to 20 bits. Accesses to External Address [0] DR0 trigger an internal access to the AD6624 based on the add ress indicated in the ACR and CAR. Thus during writes to the inter- nal registers, External Address [0] DR0 must be written l ast. At this point, data is transferred to the internal memory i ndi- cated in A[9:0]. Reads are performed in the opposite direction. Once the address is set, External Address [0] DR0 must be the first data register read to initiate an internal access. DR2 is only four bits wide. Data written to the upper four bits of this register will be ignored. Likewise reading from this register will produce only four LSBs. Write Sequencing Writing to an internal location is achieved by first writing the upper two bits of the address to Bits 1 through 0 of the ACR. Bits 7:2 may be set to select the channel as indicated above. The CAR is then written with the lower eight bits of the internal address (it does not matter if the CAR is written before the ACR as long as both are written before the internal access). Data R egister 2, (DR2) and Data Register 1 (DR1) must be written first because the write to Data Register DR0 triggers the internal access. Data Register DR0 must always be the last register written to initiate the internal write. Read Sequencing Reading from the microport is accomplished in the same manner. The internal address is set up the same way as the write. A read from Data Register DR0 activates the internal read, thus register DR0 must always be read first to initiate an internal read fol- lowed by DR1 and DR2. This provides the eight LSBs of the internal read through the microport (D[7:0]). Additional data registers can be read to read the balance of the internal memory. Read/Write Chaining The microport of the AD6624 allows for multiple accesses while CS is held low (CS can be tied permanently low if the microport is not shared with additional devices). The user can access multiple locations by pulsing the WR or RD line and changing the contents of the external 3-bit address bus. Exter- nal access to the external registers of Table II is accom plished in one of two modes using the CS, RD, WR, and MODE inputs. The access modes are Intel Nonmultiplexed Mode and Motorola Nonmultiplexed Mode. These modes are controlled by the MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR control the access type for each mode. Intel Nonmultiplexed Mode (INM) MODE must be tied low to operate the AD6624 microprocessor in INM mode. The access type is controlled by the user with the CS, RD (DS), and WR (RW) inputs. The RDY ( DTACK) signal is produced by the microport to communicate to the user that an access has been completed. RDY ( DTACK) goes low at the start of the access and is released when the internal cycle is complete. See the timing diagrams for both the read and write modes in the Specifications. Motorola Nonmultiplexed Mode (MNM) MODE must be tied high to operate the AD6624 microprocessor in MNM mode. The access type is controlled by the user with the CS, DS (RD), and RW(WR) inputs. The DTACK (RDY) signal is produced by the microport to communicate to the user that an access has been completed. DTACK (RDY) goes low when an internal access is complete and then will return high after DS (RD) is deasserted. See the timing diagrams for both the read and write modes in the specifications. Input Port Control Registers The Input Port control register enables various input-related features used primarily for input detection and level control. Depending on the mode of operation, up to four different signal paths can be monitored with these registers. These features are accessed by setting Bit 5 of external address 3 (Sleep Register) and then using the CAR (external address 6) to address the eight available locations. Response to these settings is directed to the LIA-A, LIA-B, LIB-A and LIB-B pins. Address 00 is the lower threshold for Input Channel A. This word is 10 bits wide and maps to the 10 most significant bits of the mantissa. If the upper 10 bits are less than or equal to this value, the lower threshold has been met. In normal chip operation, this starts the dwell time counter. If the input signal i ncreases above this value, the counter is reloaded and awaits the input to drop back to this level. Address 01 is the upper threshold for Input Channel A. This word is 10 bits wide and maps to the 10 most significant bits of the mantissa. If the upper 10 bits are greater than or equal to this value, the upper threshold has been met. In normal chip operation, this will cause the appropriate LI pin (LIA–A or LIA–B) to become active. Address 02 is the dwell time for Input Channel A. This sets the time that the input signal must be at or below the lower thresh- old before the LI pin is deactivated. For the input level detector to work, the dwell time must be set to at least one. If set to zero, the LI functions are disabled. Address 02 has a 20-bit register. When the lower threshold is met following an excursion into the upper threshold, the dwell time counter is loaded and begins to count high-speed clock cycles as long as the input is at or below the lower threshold. If the signal increases above the lower threshold, the counter is reloaded and waits for the signal to fall below the lower thresh- old again. Address 03 configures Input Channel A. Bit 4 determines the polarity of LIA-A and LIA-B. If this bit is cleared, the LI signal is high when the upper threshold has been exceeded. However, if this bit is set, the LI pin is low when active. This allows maximum flexibility when using this function.

the IENA pin is low, the input detection is directed to LIA–A. either case, Bit 4 determines the actual polarity of these signals. of the LIA–A, B signal to be programmed. provide control paths to the internal functions of the AD6624. be used to control the AD6624 over the Serial Port 0 interface. access over the other serial ports and the microport. the SDFS signal has no direct impact on the Serial Input Port. pass along the 8-bit data and 3-bit address to the arbitration block. is done for compatibility with the AD6620 Serial Input Port. MSB first and then the data MSB first. IEEE-1149 publication from IEEE. The AD6624 has five pins associated with the JTAG interface. except for TCLK which has a pull-down. instructions set the mode of the JTAG interface. IDCODE instruction and has the following format. Devices, Inc. for more information. Figure 45. Serial Port Control Timing

REV. B AD6624 –37– EXTEST (3’b000) Places the IC into an external boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO. During this, the boundary-scan regis- ter is accessed to drive test data off-chip via boundary outputs and receive test data off-chip from boundary inputs. IDCODE (3’b001) Allows the IC to remain in its functional mode and selects device ID register to be connected between TDI and TDO. Accessing the ID register does not interfere with the operation of the IC. SAMPLE/PRELOAD (3’b010) Allows the IC to remain in normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. The boundary-scan register can be accessed by a scan operation to take a sample of the functional data entering and leaving the IC. Also, test data can be preloaded into the boundary scan register before an EXTEST instruction. HIGHZ (3’b011) Sets all outputs to high impedance state. Selects the 1-bit bypass register to be connected between TDI and TDO. CLAMP (3’b100) Sets the outputs of the IC to logic levels determined by the boundary-scan register and selects the 1-bit bypass register to be connected between TDI and TDO. Before this instruction, boundary-scan data can be preloaded with the SAMPLE/PRELOAD instruction. BYPASS (3’b111) Allows the IC to remain in normal functional mode and selects 1-bit bypass register between TDI and TDO. During this instruction, serial data is transferred from TDI to TDO without affecting operation of the IC. INTERNAL WRITE ACCESS Up to 20 bits of data (as needed) can be written by the process described below. Any high order bytes that are needed are writ- ten to the corresponding data registers defined in the external 3-bit address space. The least significant byte is then written to DR0 at address (000). When a write to DR0 is detected, the internal microprocessor port state machine then moves the data in DR2-DR0 to the internal address pointed to by the address in the LAR and AMR. Write Pseudocode void write_micro(ext_address, int data); main(); /* This code shows the programming of the NCO phase offset register using the write_micro function as defined above. The variable address is the External Address A[2:0] and data is the value to be placed in the external interface register. Internal Address = 0x087 // holding registers for NCO phase byte wide access data int d1, d0; // NCO frequency word (16-bits wide) NCO_PHASE = 0xCBEF; // write ACR write_micro(7, 0x03); // write CAR write_micro(6, 0x03); // write DR1 with D[15:8] d1 = (NCO_PHASE & 0xFF00) >> 8; write_micro(1, d1); // write DR0 with D[7:0] // On this write all data is transferred to the internal address d0 = NCO_FREQ & 0xFF; write_micro(0, d0); } // end of main INTERNAL READ ACCESS A read is performed by first writing the CAR and AMR as with a write. The data registers (DR2–DR0) are then read in the reverse order that they were written. First, the least significant byte of the data (D[7:0]) is read from DR0. On this transaction, the high bytes of the data are moved from the internal address pointed to by the CAR and AMR into the remaining data regis- ters (DR2–DR1). This data can then be read from the data registers using the appropriate 3-bit addresses. The number of data registers used depends solely on the amount of data to be read or written. Any unused bit in a data register should be masked out for a read. Read Pseudocode int read_micro(ext_address); main(); /* This code shows the reading of the first RCF coefficient using the read_micro function as defined above. The variable address is the External Address A[2..0]. Internal Address = 0x000 // holding registers for the coefficient int d2, d1, d0; // coefficient (20-bits wide) long coefficient; // write AMR write_micro(7, 0x00); // write LAR write_micro(6, 0x00); /* read D[7:0] from DR0, All data is moved from the Internal Registers to the interface registers on this access */ d0 = read_micro(0) & 0xFF; // read D[15:8] from DR1 d1 = read_micro(1) & 0xFF; // read D[23:16] from DR2 d2 = read_micro(2) & 0x0F; coefficient = d0 + (d1 << 8) + (d2 << 16); } // end of main

REV. B AD6624 –38– OUTLINE DIMENSIONS 128-Lead Metric Quad Flat Package [MQFP] (S-128-1) Dimensions shown in millimeters TOP VIEW (PINS DOWN) 102 128 103 0.27 0.17 0.50 BSC 1.03 0.88 0.73 SEATING PLANE 3.40 MAX COPLANARITY

0.10 MAX

0.50 0.25 2.90 2.70 2.50 17.45 17.20 16.95 14.20 14.00 13.80 20.20 20.00 19.80 23.45 23.20 22.95

REV. B AD6624 –39–

Revision History

3/04—Data Sheet changed from REV. A to REV. B. 9/02—Data Sheet changed from REV. 0 to REV. A.

–40– C02395–0–3/04(B)