AD6622

REV.0

Document overview

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Technical content

REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD6622 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 Four-Channel, 75 MSPS Digital Transmit Signal Processor (TSP) FUNCTIONAL BLOCK DIAGRAM CH A CH B CH C CH D RCF NCO 18 /H9262PORT CIC FILTERSPORT SPORT SPORT SPORT RCF RCF RCF CIC FILTER CIC FILTER CIC FILTER NCO NCO NCO JTAG SUMMATION

FEATURES

Wideband Digital IF Parallel Output Wideband Digital IF Parallel Input Allows Cascade of Chips for Additional Channels Programmable IF and Modulation for Each Channel Programmable Interpolating RAM Coefficient Filter High-Speed CIC Interpolating Filter NCO Frequency Translation Worst Spur Better than 100 dBc Tuning Resolution Better than 0.02 Hz Real or Complex Outputs Digital Summation of Channels Clipped or Wrapped Overrange Two’s Complement or Offset Binary Output Separate 3-Wire Serial Data Input for Each Channel Microprocessor Control JTAG Boundary Scan

APPLICATIONS

Cellular/PCS Base Stations Micro/Pico Cell Base Stations WBCDMA Wireless Local Loop Base Stations Phase Array Beam Forming Antennas PRODUCT DESCRIPTION The AD6622 comprises four identical digital Transmit Signal Processors (TSPs) complete with synchronization circuitry and cascadable wideband channel summation. An external digital- to-analog converter (DAC) is all that is required to complete a wide band digital up-converter. On-chip tuners allow the relative phase and frequency for each RF carrier to be independently controlled. Each TSP has three cascaded signal processing elements: a RAM-programmable Coefficient interpolating Filter (RCF), a programmable Cascaded Integrator Comb (CIC) interpolating filter, and a Numerically Controlled Oscillator/tuner (NCO). The outputs of the four TSPs are summed and scaled on-chip. In multichannel wideband transmitters, multiple AD6622s may be combined using the chip’s cascadable output summation stage. Each channel provides independent serial data inputs that may be directly connected to the serial port of DSP chips. User pro- grammable FIR filters can be used to filter linear inputs. All control registers and coefficient values are programmed through a generic microprocessor interface. Two microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible.

–2– REV. 0 AD6622–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Test AD6622AS Parameter Level Min Typ Max Unit VDD IV 2.4 3.0 3.3 V TAMBIENT IV –40 +25 +70 °C

ELECTRICAL CHARACTERISTICS

Parameter (Conditions) Temp Level Min Typ Max Unit LOGIC INPUTS (5 V TOLERANT) 3.0 V CMOS Logic Compatibility Full Logic “1” Voltage Full IV 2.0 VDD + 0.3 V Logic “0” Voltage Full IV –0.3 +0.8 V Logic “1” Current Full IV 1 10 µA Logic “0” Current Full IV 1 10 µA Input Capacitance 25 °CV 4 p F LOGIC OUTPUTS Logic Compatibility Full Logic “1” Voltage (IOH = 0.25 mA) Full IV VDD – 0.05 VDD – 0.035 V Logic “0” Voltage (IOL = 0.25 mA) Full IV 0.02 0.05 V IDD SUPPLY CURRENT CLK = 60 MHz, 3.3 V1 Full IV 506 566 1 mA CLK = GSM Example V 297 2 mA CLK = IS-136 Example V 240 2 mA CLK = WBCDMA Example V 209 2 mA Sleep Mode Full IV 0.1 0.5 mA POWER DISSIPATION CLK = 60 MHz, 3.3 V1 Full IV 1.77 1.87 W CLK = GSM Example V 0.89 2 W CLK = IS-136 Example V 0.72 2 W CLK = WBCDMA Example V 0.627 2 W Sleep Mode Full IV 0.33 1.65 mW NOTES 1This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimu m interpolation in both CIC stages, maximum switching of input data, and maximum VDD of 3.3 V. In an actual application the power will be less; see the Thermal Management section of the data sheet for further details. 2GSM interpolation = 120 at 65 MHz, 4 channels active, IS-136 interpolation = 2560 at 62.208 MHz, 4 channels active. WBCDMA inte rpolation = 64, 4 channels interleaved at 61.44 MHz. Specifications subject to change without notice.

–3–REV. 0 TIMING CHARACTERISTICS1 Test AD6622AS Name Parameter (Conditions) Temp Level Min Typ Max Unit CLK Timing Requirements : tCLK CLK Period Full IV 13.3 ns tCLKL CLK Width Low Full IV 5.5 0.5 × tCLK ns tCLKH CLK Width High Full IV 5.5 0.5 × tCLK ns RESET Timing Requirements: tRESL RESET Width Low Full IV 30.0 ns Input Wideband Data Timing Requirements : tSI Input to CLK Setup Time Full IV 0.5 ns tHI Input to CLK Hold Time Full IV 3.5 ns Parallel Output Switching Characteristics : tSO CLK to Output Setup Time Full IV 12 ns tHO CLK to Output Hold Time Full IV 4.1 ns tZO Output Three-State Time Full V 5 ns SYNC Timing Requirements : tSS SYNC to CLK Setup Time Full IV 2.6 ns tHS SYNC to CLK Hold Time Full IV 1.5 ns Serial Port Timing Requirements : tDSCLK CLK to SCLK Delay Full V 8.5 ns tDSDFS SCLK to SDFS Delay Full IV –1.2 +2.4 ns tSSI SDI to SCLK Setup Time Full IV 8.5 ns tHSI SDI to SCLK Hold Time Full IV 5.5 ns tSCS Serial Clock Skew Full IV 7 ns MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing : tHWR WR(R/W) to RDY(DTACK) Hold Time Full IV 0 ns tSAM Address/Data to WR(R/W) Setup Time Full IV 0 ns tHAM Address/Data to RDY(DTACK) Hold Time Full IV 0 ns tDRDY WR(R/W) to RDY(DTACK) Delay Full IV 10.2 ns tACCFAST WR(R/W) to RDY(DTACK) High Delay Full IV 2 × tCLK 3 × tCLK ns tACCMEDIUM WR(R/W) to RDY(DTACK) High Delay Full IV 3 × tCLK 4 × tCLK ns tACCSLOW WR(R/W) to RDY(DTACK) High Delay Full IV 4 × tCLK 5 × tCLK ns MODE INM Read Timing: tSAM Address to RD(DS) Setup Time Full IV 0 ns tHA Address to Data Hold Time Full IV 0 ns tZD Data Three-State Delay Full IV 3.4 7 10.5 ns tDD RDY(DTACK) to Data Delay Full IV t CLK – 10 ns tDRDY RD(DS) to RDY(DTACK) Delay Full IV 10.2 ns tACCFAST RD(DS) to RDY(DTACK) High Delay Full IV 2 × tCLK 3 × tCLK ns tACCMEDIUM RD(DS) to RDY(DTACK) High Delay Full IV 3 × tCLK 4 × tCLK ns tACCSLOW RD(DS) to RDY(DTACK) High Delay Full IV 4 × tCLK 5 × tCLK ns (CLOAD = 40 pF, all outputs unless specified)

–7–REV. 0 ABSOLUTE MAXIMUM RATINGS * IN[17:0], QIN, OEN CLK, RESET, DS, R/W, MODE, A[2:0], D[7:0], SYNC, TRST, TCK, TMS, TDI, SDINA, SDINB, SDINC, SDIND *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 128-Lead MQFP: θJA = 33°C/W, No Airflow θJA = 27°C/W, 200 LFPM Airflow θJA = 24°C/W, 400 LFPM Airflow θJC = 5.5°C/W Thermal measurements made in the horizontal po sition on a 2-layer board. EXPLANATION OF TEST LEVELS I. 100% Production Tested. II. 100% Production Tested at 25 °C, and Sample Tested at Specified Temperatures. III. Sample Tested Only. IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at 25 °C, and Sample Tested at Temperature Extremes. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6622AS –40 °C to +70°C (Ambient) 128-Lead MQFP (Metric Quad Flatpack) S-128A AD6622S/PCB Evaluation Board with AD6622 and Software CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6622 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–8– REV. 0 PIN CONFIGURATION GND TMS TDO TDI SCLKA SDFSA SDINA SCLKB SDFSB GND GND GND SDINB SCLKC SDFSC SDINC VDD GND VDD VDD SCLKD SDFSD SDIND GND VDD GND GND TCK TRST GND GND IN0 GND GND IN1 IN2 IN3 IN4 VDD IN5 IN6 IN7 IN8 GND GND IN16 GND GND IN17 QIN GND GND CLK VDD GND GND IN9 IN10 IN11 IN12 VDD IN13 IN14 IN15 GND GND GND GND GND SYNC RESET CS VDD MODE GND GND VDD GND R/W(WR) DTACK(RDY) DS(RD) GND VDD GND GND GND OEN GND GND GND OUT0 OUT1 OUT2 GND OUT3 OUT4 OUT5 OUT6 VDD OUT7 OUT8 OUT9 OUT10 GND GND GND OUT11 OUT12 OUT13 OUT14 VDD OUT15 OUT16 OUT17 QOUT GND GND 101 102 100 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD6622 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 DENOTES I/O POWER PIN DENOTES CORE POWER PIN

–9–REV. 0 PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1, 3–5, 9, 19–21, 31, 32, GND P Ground Connection 95, 96, 98, 99, 102, 103, 105, 115–117, 126, 128

2 OEN I Active High Output Enable Pin (Actively Pulled Down If Not Conn ected)

(Not 5 V Tolerant) 27–29, 22–25, 15–18, 10–13, OUT[17:0] O/T Wideband Output Data 6–8 14, 26, 41, 47, 122 VDD P +3.0 V Supply (I/O Supply) 59, 66, 78, 90, 104, 110, 127 VDD P +3.0 V Supply (Core Supply)

30 QOUT O/T Indicates Q Output Data (Complex Output Mode)

33, 37, 40, 43–46, 48 D[7:0] I/O/T Microprocessor Interface Data

49 DS (RD) I INM Mode: Read Signal, MNM Mode: Data Strobe Signal

50 DTACK (RDY) O Acknowledgment of a Completed Transaction (Signals when µP Port

Is Ready for an Access) Open Drain, Must Be Pulled Up Externally

51 R/ W (WR) I Read/Write Line (Write Signal)

55 MODE I Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0, INM Mode

56–58 A[2:0] I Microprocessor Interface Address

60 CS I Chip Select, Enable the Chip for µP Access

61 RESET I Active Low Reset Pin (Actively Pulled Up If Not Connected)

62 SYNC I SYNC Signal for Synchronizing Multiple AD6622s (Actively Pulled

Down If Not Connected)

67 CLK I Input Clock (Actively Pulled Down If Not Connected)

70 QIN I Indicates Q Input Data (Complex Input Mode) (Actively Pulled Down

If Not Connected) (Not 5 V Tolerant) 71, 74–77, 79–82, 86–89, IN[17:0] I Wideband Input Data (Allows Cascade of Multiple AD6622 Chips In 91–94, 97 a System) (Actively Pulled Down If Not Connected) (Not 5 V Tolerant)

100 TRST I Test Reset Pin (Actively Pulled Up If Not Connected)

101 TCK I Test Clock Input (Actively Pulled Down If Not Connected)

106 TMS I Test Mode Select (Actively Pulled Up If Not Connected)

107 TDO O Test Data Output

108 TDI I Test Data Input (Actively Pulled Down If Not Connected)

109 SCLKA O Serial Clock Output Channel A

111 SDFSA O Serial Data Frame Sync Output Channel A

112 SDINA I Serial Data Input Channel A (Actively Pulled Down If Not Connected)

113 SCLKB O Serial Clock Output Channel B

114 SDFSB O Serial Data Frame Sync Output Channel B

118 SDINB I Serial Data Input Channel B (Actively Pulled Down If Not Connected)

119 SCLKC O Serial Clock Output Channel C

120 SDFSC O Serial Data Frame Sync Output Channel C

121 SDINC I S erial Data Input Channel C (Actively Pulled Down If Not Connected)

123 SCLKD O Serial Clock Output Channel D

124 SDFSD O Serial Data Frame Sync Output Channel D

125 SDIND I Serial Data Input Channel D ( Actively Pulled Down If Not Connected)

than comparable high-dynamic-range analog designs. designed to bridge the gap between DSPs and high-speed DACs. ture allows easy reconfiguration for multimode applications. to be combined in a single, cost-effective filter. minimize clipping at the DAC. entire system is based on the DAC clock rate (up to 75 MSPS). to half the master clock rate on the shared output bus. AD6622 serial ports to meet an external timing requirement. SCLK frequency is 1/64 of the master clock frequency. Figure 9. Functional Block Diagram

–12– REV. 0 1. Select the Impulse Response Length (N RCF) and the Inter- polation Factor (L RCF ). The Impulse Response Length (NRCF) is limited in three ways: by the available calculation time, by the data memory size (DMEM), and by the coef fi- cient memory size (CMEM). The equation below shows that N RCF is limited to the minimum of these three conditions. Time CMEM Restriction Restriction N L LRCF RCF≤×  DMEM Restriction where: L = LRCF × LCIC5 × LCIC2 2. The interpolation rate (L RCF) may be any integer of N RCF ranging from 1 to 128, while meeting the above equation. Most filter designs can be optimized by choosing the small- est LRCF that does not compromise the image rejection of the subsequent CIC filter. The quality of an interpolating filter is a strong function of the N RCF/LRCF ratio and a weaker function of N RCF. The best filters are usually achieved by maximizing NRCF/LRCF (no larger than 16) and then increasing both NRCF and LRCF by the same ratio until the filter becomes time or CMEM limited. 3. Once N RCF and LRCF are selected, Channel Register 0x0A is programmed to NRCF – 1, and Channel Register 0x0C is programmed to NRCF/LRCF – 1. 4. Determine the Impulse Response. The impulse response relative to the RCF output rate can be calculated using ordi- nary FIR design techniques. In most cases, it is desirable to precompensate the inband frequency roll-off of the CIC fil- ter that follows. There are no symmetry requirements, so the RCF can also be used for static phase equalization. The impulse response must be quantized to 16-bit two ’s comple- ment numbers for the CMEM. The channel center gain and worst-case peak can be calculated for each of the LRCF phases (p) according to the equations below. A RCF coarse scale factor (g) that ranges between 0 and 3 is provided to limit the gain without excessive loss of resolution in the CMEM. The coarse scale factor is located in Channel Register 0x0D. ChannelCenterGain h k L pp g RCF k N L RCF RCF =× × + ∑− (7) 5. The channel center gain is the response to a constant full- scale input at every output phase. The summ ation is split into phases because the interpolation of the data insures that only NRCF/LRCF coefficients can be active for any single output. For LRCF = 1, there is only one phase and the channel center gain is the simple sum of all the coef ficients, scaled by 2–g. If the channel center gain is not the same for every value of p, some or all of the images of the channel center will be imperfectly rejected by the RCF. WorstCasePeak h k L pp g RCF k N L RCF RCF =× × + ∑− |[ ] | (8) 6. The worst-case peak is calculated similarly to the channel center gain, except that the input sequence swings from full- scale positive to full-scale negative to match the polarity of the coefficient by which it will be multiplied, so that each prod- uct is positive. This results in a maximal that must be less than one to guarantee no possibility of wrapping. Note that when L RCF is greater than one, each phase may produce its worst-case peak in response to a different input sequence. 7. Programming DMEM and CMEM. The DMEM must be initialized to all zeros to avoid any unpredictable start-up transients since a reset does not c lear the memory. The impulse response h[n] must be reordered by phase for the CMEM as shown in the code below. Several filters with impulse lengths that total less than 128 can be programmed into the CMEM simultaneously and selected later using the RCF offset pointer (O RCF) which is set by Channel Register 0x0B. /* Reorder Fir Coefficients for AD6622 CMEM */ for (p=0; p<L_RCF; p++) for (k=0; k<N_RCF/L_RCF; k++) CMEM[O_RCF + p*N_RCF/L_RCF + k] = C[k*L_RCF +p]; /* End of routine */ Table I. RCF Control Registers Channel Bit Address Width Description 0x0A 8 7: Reserved (Must Be Written to 0) 6–0: N RCF–1 0x0B 8 7: Reserved (Must Be Written to 0) 6–0: O RCF 0x0C 8 7 –6: Reserved 5–4: Reserved (Must Be Written to 0) 3–0: N RCF/LRCF–1 0x0D 8 7 –6: RCF Coarse Scale: 00 = 0 dB 01 = –6 dB 10 = –12 dB 11 = –18 dB 5: Reserved (Must Be Written to 0) 4–0: Serial Clock Divider 0x0E 16 15 –0: Reserved 0x0F 16 15 –0: Reserved 0x10 16 15 –0: Reserved (Must Be Written to 0) 0x11 16 15 –0: Reserved (Must Be Written to 0) 0x20–0x3F 16 15 –0: Data Memory (DMEM) 0x80–0xFF 16 15 –0: Coef ficient Memory (CMEM)

–14– REV. 0 Table II lists maximum bandwidth that will be rejected to various levels for CIC5 interpolation factors from 1 to 32. Figure 15 corresponds to the listing in the –110 dB column and the LCIC5 = 5 row. It is worth noting that the rejection of the CIC5 improves as the interpolation factor increases. Table II. CIC5 Alias Protection –110 dB –100 dB –90 dB –80 dB –70 dB

1 Full Full Full Full Full

The CIC2 is a second-order interpolating cascaded integrator comb whose impulse response is completely de fined by its inter- polation factor, L CIC2. The value LCIC2–1 can be independently programmed for each channel at location 0x08. While this con- trol register is 8 bits wide, LCIC2 should be confined to the ranges shown by the table below according to the interpolation factor of the CIC5. Exceeding the recommended guidelines may result in overflow for input sequences at or near full scale. While relatively small values of L CIC5 allow for the larger overall interpolation factors with minimal power consumption, L CIC5 should be maxi- mized to achieve the best overall image rejection. Table III. Maximum L CIC2 Limits LCIC5 Max LCIC2 1–19 256 20 209 21 172 22 143 23 119 24 101 25 85 26 73 27 63 28 54 29 47 30 41 31 36 32 32 The transfer function of the CIC2 is given by the following equations with respect to the CIC2 output sample rate, f OUT. CIC z z z LCIC 2 1 () –  (14) This polynomial fraction can be completely reduced as follows, demonstrating a finite impulse response with perfect phase lin- earity for all values of LCIC2. CIC z z z e k k L j k L k LCIC CIC CIC 1 2 2 1 2 1  =− π (15) The frequency response of the CIC2 can be expressed as follows. The maximum gain is L CIC2 at baseband. The initial 1/L CIC2 factor normalizes for the increased rate, which is appropriate when the samples are destined for a DAC with a zero order hold output. CIC f L Lf f f f CIC CIC OUT OUT 2 1 sin sin π π (16) As an example, we will consider an input from the CIC5 whose bandwidth is 0.0033 of the CIC5 rate, centered at baseband. Interpolation by a factor of five reveals five images, as shown below.

Figure 16. Unfiltered CIC2 Interpolation Images image. All other image frequencies have better rejection. Figure 17. Filtered CIC2 Interpolation Images CIC2 improves as the interpolation factor increases.

quency (IF), and passes the result to a shared summa tion block. from the NCO is better than –100 dBc for all output frequencies. frequencies solely by spectral inversion. The digital IF is calculated using Equation 17 below. tion in total error energy will occur. dither can reduce spurs due to truncation at the input to the QAM. be large and amplitude dither will spread these spurs effectively. from 0 to nearly 2 π radians with a resolution of π/32768 radians. duce sine waves with a known phase relationship. taneously, resulting in a 3 dB input magnitude. Figure 18. NCO Block Diagram

puts of each channel to create a composite multicarrier signal. the AD6622 OEN, thus eliminating extra circuitry. of the Summation Mode Control Register at ad dress 0x000. the DAC in this manner gives the summation block a gain of 0 dB. bit, then the summation block will have a gain of –6.02 dB. second is when driving another AD6622 in cascade mode. more negative than the output can express. lated, this is usu ally not necessary. signal if this port is unused (not connected). If complex data is desired, there are two ways this can be obtained. signal that toggles on every rising edge of the high-speed clock. AD6622 would be connected to the QIN of the following part. put bus represents valid complex data samples. Figure 19. Cascade Operation of Two AD6622s Three types of synchronization can be achieved with the AD6622. These are Start, Hop, and Beam. Each is described in detail below.

Figure 20. NCO Shadow Register and Hold-Off Counter

1. To program a channel, it must first be set to the Program
2. Set the ap propriate program and sleep bits low (External

Program and Sleep Mode low to activate a channel.

1. Set the appropriate channels to sleep mode (a hard reset
2. Write the Start Update Hold-Off Counter(s) (0x00) to the
3. Write the Start bit and the SyncX(s) bit high (External
4. This starts the Start Update Hold-Off Counter counting

down. The counter is clocked with the AD6622 CLK signal. ate channel(s) is set low to activate the channel(s). accurate synchronization, especially between multiple AD6622s.

1. Set the appropriate channels to sleep mode (a hard reset to
2. Write the Start Update Hold-Off Counter(s) (0x00) to the
3. Set the start on pin sync bit and the appropriate sync pin
4. When the sync pin is sampled high by the AD6622 CLK, it

enables the countdown of the Start Update Hold-Off Counter. channel(s) is set low to activate the channel(s). Hop is a jump from one NCO frequency to a new NCO frequency. sor control or an external sync signal as described below.

1. Set the NCO Freq Hold-Off Counter to 0.
2. Load the appropriate NCO frequency. The new frequency

will immediately be loaded to the NCO. nels via microprocessor control.

–19–REV. 0 1. Write the NCO Freq Hold-Off (0x03) Counter to the appro- priate value (greater than 1 and less then 2 16–1). 2. Write the NCO Frequency Register(s) to the new desired frequency. 3. Write the hop bit and the sync(s) bit high (Ext Address 5). 4. This starts the NCO Freq Hold-Off Counter counting down. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the new frequency is loaded into the NCO. Hop with Pin Sync A sync pin is provided on the AD6622 to provide the most accurate synchronization, especially between multiple AD6622s. Synchronization of hopping to a new NCO frequency with an external signal is accomplished with the following method. 1. Write the NCO Freq Hold-Off Counter(s) (0x03) to the appropriate value (greater than 1 and less than 2 16–1). 2. Write the NCO Frequency register(s) to the new desired frequency. 3. Set the hop on pin sync bit and the appropriate sync pin enable high (0x001). 4. When the sync pin is sampled high by the AD6622 CLK this enables the countdown of the NCO Freq Hold-Off Counter. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one the new frequency is loaded into the NCO. Beam is a change in phase for a particular channel and can be synchronized with respect to other channels or AD6622s. This change in phase can be synchronized via microprocessor control or an external sync signal as described below. To set the amplitude without synchronization the following method should be used. Set Phase No Beam 1. Set the NCO Phase Offset Update Hold-Off Counter (0x05) to 0. 2. Load the appropriate NCO Phase Offset (0x04). The NCO Phase Offset will be immediately loaded. Beam with Soft Sync The AD6622 includes the ability to synchronize a change in NCO phase of multiple channels or chips under microprocessor control. The NCO Phase Offset Update Hold-Off Counter, in conjunction with the beam bit and the sync bit (Ext Address 5), allow this synchronization. Basically the NCO Phase Offset Update Hold-Off Counter delays the new phase from being loaded into the NCO/RCF by its value (number of AD6622 CLKs). The following method is used to synchronize a beam-in phase of multiple channels via microprocessor control. 1. Write the NCO Phase offset Update Hold-Off Counter (0x05) to the appropriate value (greater than 1 and less then 2 16–1). 2. Write the NCO Phase Offset Register(s) to the new desired phase and amplitude. 3. Write the beam bit and the sync(s) bit high (External Address 5). 4. This starts the NCO Phase Offset Update Hold-Off counter counting down. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the new phase is loaded into the NCO. Beam with Pin Sync A sync pin is provided on the AD6622 to provide the most accurate synchronization, especially between multiple AD6622s. Synchronization of beaming to a new NCO Phase Offset with an external signal is accomplished with the following method. 1. Write the NCO Phase Offset Hold-Off (0x05) counter(s) to the appropriate value (greater than 1 and less than 2 16–1). 2. Write the NCO Phase Offset register(s) to the new desired phase and amplitude. 3. Set the beam on pin sync bit and the appropriate sync pin enable high (0x001). 4. When the sync pin is sampled high by the AD6622 CLK, it enables the countdown of the NCO Phase Offset Hold-Off Counter. The counter is clocked with the AD6622 CLK sig- nal. When it reaches a count of one, the new phase is loaded into the NCO registers. JTAG INTERFACE The AD6622 supports a subset of IEEE Standard 1149.1 specifications. For additional details of the standard, please see “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE-1149 publication from IEEE. The AD6622 has five pins associated with the JTAG interface. These pins are used to access the on-chip Test Access Port and are listed in Table VIII. Table VIII. JTAG Pin List Name Pin Number Description TRST 100 Test Access Port Reset TCK 101 Test Clock TMS 106 Test Access Port Mode Select TDI 108 Test Data Input TDO 107 Test Data Output The AD6622 supports four op codes as shown in Table IX. These i nstructions set the mode of the JTAG interface. Table IX. JTAG Op Codes Instruction Op Code IDCODE 10 BYPASS 11 SAMPLE/PRELOAD 01 EXTEST 00 The Vendor Identi fication Code can be accessed through the IDCODE instruction and has the following format. Table X. JTAG ID String MSB Part Manufacturing LSB Version Number ID # Mandatory 000 0010 000 1110 0101 1 0111 1000 0000 A BSDL file for this device is available from Analog Devices, Inc. Contact Analog Devices Inc. for more information.

–20– REV. 0 SCALING Proper scaling of the wideband output is critical to maximize the spurious and noise performance of the AD6622. A relatively small overflow anywhere in the data path can cause the spurious free dynamic range to drop precipitously. Scaling down the output levels also reduces dynamic range relative to an approximately constant noise floor. A well-balanced scaling plan at each point in the signal path will be rewarded with optimum performance. The scaling plan can be separated into two parts: multicarrier scaling and single-carrier scaling. Multicarrier Scaling An arbitrary number of AD6622s can be cascaded to create a composite digital IF with many carriers. As the number of carriers increases, the peak-to-rms ratio of the composite digital IF will increase as well. It is possible and bene ficial to limit the peak-to- rms ratio through careful frequency planning and controlled phase offsets. Nevertheless, in most cases with a large number of carriers, the worst-case peak is an unlikely event. The AD6622 immediately preceding the DAC can be programmed to clip rather than wrap around (see the Summation Block descrip- tion). For a large number of carriers, a rare but finite chance of clipping at the AD6622 wideband output will result in superior dynamic range compared to lowering each carrier level until clipping is impossible. This will also be the case for most DACs. Through analysis or experimentation, an optimal output level of individual carriers can be determined for any particular DAC. Single-Carrier Scaling Once the optimal power level is determined for each carrier, one must determine the best way to achieve that level. The maximum SNR can be achieved by maximizing the intermediate power level at each processing stage. This can be done by assuming the proper level at the output and working backwards along the signal path: Summation, NCO, CIC, and finally, RCF. The summation block is intended to combine multiple carriers, with each carrier at least 6 dB below full scale. For this con figu- ration, the AD6622 driving the DAC should have clip detection enable. OUT17 becomes a clip indicator that reports clipping in both polarities. If the DAC requires offset binary outputs, the internal offset binary conversion should be enabled as well. Any preceding cascaded AD6622s should disable clip detection and offset binary conversion. The IN17–IN0 of the first AD6622 in the cascade should be grounded. See the Summation Block section for details. In this con figuration, intermediate OUT17s will serve as guard bits that allow intermediate sums to exceed full scale. As long as the final output does not exceed 6 dB over full scale, the clip detector will perform correctly. If a single carrier needs to exceed –6 dB full scale, hardwired scaling can be accomplished according to the table below. This is most useful when the AD6622 is processing a Single Wide- band Carrier such as UMTS or CDMA 2000. Table XI. Output Bit Scaling Max Single- Connect to Clip Offset Binary Carrier Level DAC MSB Detect Compensation –12.04 dB OUT17 N/A Internal –6.02 dB OUT16 ± Internal 0 dB OUT15 +Only 0x18000 +6.02 dB OUT14 +Only 0x1C000 +12.04 dB OUT13 +Only 0x1E000 +18.06 dB OUT12 +Only 0x1F000 +24.08 dB OUT11 +Only 0x1F800 The NCO/Tuner is equipped with an output scalar that ranges from –6.02 dB to –24.08 dB below full scale, in 6.02 dB steps. See the NCO/Tuner section for details. The best SNR will be achieved by m aximizing the input level to the NCO and using the largest possible NCO attenuation. For example, to achieve an output level –20 dB below full scale, one should set the CIC output level to –1.94 dB below full scale and attenuate by –18.06 dB in the NCO. The CIC is equipped with an output scalar that ranges from 0 dB to –150.51 dB below full scale in 6.02 dB steps. This large attenuation is necessary to compensate for the potentia lly large gains associated with CIC interpolation. See the CIC section for details. For example to achieve an output level of –1.94 dB below full scale, with a CIC5 interpolation of 27 (114.51 dB gain) and a CIC2 interpolation of 3 (9.54 dB gain), one should set the CIC_Scale to 20 and the RCF output level to –5.59 dB below full scale. The RCF is equipped with an output scalar that ranges from 0 dB to –18.06 dB below full scale in 6.02 dB steps. This attenua tion can be used to compensate for filter gain in the RCF. For example, if the desired RCF output is –5.59 dB and the maxim gain of the RCF coefficients is 11.04 dB, then the RCF_Coarse_Scale should be set to two and the coef ficients should be scaled so that the largest coefficient is –4.59 dB below full scale. The largest pos- sible gain of the RCF coef ficients is when the largest coef ficient of the impulse response is normalized to one. This means that all of the coef ficients are as large as possible so the sum of the coefficients are as large as possible. This maximum gain will determine the RCF_Coarse_Scale, which should be used to make the total RCF gain between 0 dB and –6.02 dB. After the RCF_Coarse_Scale is chosen, the coefficients can be rescaled, as in the example, to set the total RCF gain to a desired level. See the RCF section for additional information. Finally, as described in the RCF section, there may be a worst- case peak of a phase that is larger than the channel center gain. In the preceding example, if the worst-case to channel center ratio is larger than 4.59 dB (potentially overflowing the RCF), the RCF_Coarse_Scale should be reduced by one and the CIC_Scale should be increased by one. In the preceding example, if the worst- case to channel center ratio is larger than 5.59 dB (potentially overflowing the RCF and CIC), the RCF_Coarse_Scale should be reduced by one and the NCO_Output_Scale should be increased by one. MICROPORT INTERFACE The Microport interface is the communications port between the AD6622 and the host controller. There are two modes of bus operation: Intel Nonmultiplexed Mode (INM), and Motorola Nonmultiplexed Mode (MNM), which is set by hard wiring the MODE pin to either ground or supply. The mode is selected based on the use of the Microport control lines ( DS or RD, DTACK or RDY, R/W or WR) and the capabilities of the host processor. See the timing diagrams for details on the operation of both modes. The External Memory Map provides data and address registers to read and write the extensive control registers in the Internal Memory Map. The control registers access global chip functions and multiple control functions for each independent channel.

–21–REV. 0 Microport Control All accesses to the internal registers and memory of the AD6622 are accomplished indirectly through the use of the microproces- sor port external registers shown in Table XII. Accesses to the External Registers are accomplished through the 3-bit address bus (A[2:0]) and the 8-bit data bus (D[7:0]) of the AD6622 (Microport). External Address [3:0] provides access to data read from or written to the internal memory (up to 32 bits). External Address [0] is the least signi ficant byte and External Address [3] is the most signi ficant byte. External Address [4] controls the resets of each channel. External Address [5] controls the sync status of each channel. External Address [7:6] determines the Internal Address selected and whether this address is incremented after subsequent reads and/or writes to the internal registers. EXTERNAL MEMORY MAP The External Memory Map is used to gain access to the Inter- nal Memory Map described below. External Address [7:6] sets the Internal Address to which subsequent reads or writes will be performed. The top two bits of External Address [7] allow the user to set the address to autoincrement after reads, writes, or both. All internal data words have widths that are less than or equal to 32 bits. Accesses to External Address [0] trigger accesses to the AD6622’s internal memory map. Thus during writes to the internal registers, External Address [0] must be written last to ensure all data is transferred. Reads are the oppo- site in that External Address [0] must be the first data register read (after setting the appropriate internal address) to initiate an internal access. External Address [5:4] reads and writes are immediately trans- ferred to internal control registers. External Address [4] is the reset register. The reset bits can be set collectively by the address. The reset bits can be cleared by operation of start syncs (described below). External Address [5] is the sync register. These bits are write only. There are three types of syncs: start, hop, and beam. Each of these can be sent to any or all of the four channels. For example, a write of X0010100 would issue a start sync to Channel C only. A write of X1101111 would issue a beam sync and a hop sync to all channels. The internal address bus is 11 bits wide and the internal data bus is 32 bits wide. External Address 7 is the Chan (C hannel) and stores the upper three bits of the address space in Chan[2:0]. Chan[7:6] define the autoincrement feature. If Bit 6 is high, the internal address in incremented after an internal read. If Bit 7 is high, the internal address is incremented after an internal write. If both bits are high, the internal address in incremented after either a write or a read. This feature is designed for sequential access to internal locations. External Address 6 is the Addr (Address) and stores the lower eight bits of the internal address. External Addresses 3 through 0 store the 32 bits of the internal data. All internal accesses are two clock cycles long. Writing to an internal location with a data width of 16 bits is achieved by first writing the upper three bits of the address to Bits 2 through 0 of the Chan. (Bits 7 and 6 of the Chan are written to determine whether or not the auto increment fea- ture is enabled.) The Addr is then written with the lower eight bits of the internal address (it does not matter if the Addr is written before the Chan as long as both are written before the internal access). Since the data width of the internal address is 16 bits, only Data Register 1 and Data Register 0 are needed. Data Register 1 must be written first because the write to Data Register 0 triggers the internal access. Data Register 0 must always be the last register written to initiate the internal write. Reading from the Microport is accomplished in a similar manner. The internal address is first written. A read from Data Register 0 activates the internal read, thus register 0 must always be read first to initiate an internal read. This provides the 8 LSBs of the internal read through the Microport (D[7:0]). Additional bytes are then read by changing the external address (A[2:0]) and performing additional reads. If Data Register 3 (or any other) is read before Data Register 0, incorrect data will be read. Data Register 0 must be read first in order to transfer data from the core memory to the external memory locations. Once data register is read, the remaining locations may be examined in any order. The Microport of the AD6622 allows for multiple accesses while CS is held low ( CS can be tied permanently low if the Microport is not shared with additional devices). The user can access multiple locations by pulsing the WR or RD line and changing the contents of the external 3-bit address bus. A ccess to the external registers of Table XII is accomplished in one of two modes using the CS, RD, WR, and MODE inputs. The access modes are Intel Nonmultiplexed Mode and Motorola Nonmultiplexed Mode. These modes are controlled by the MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR control the access type for each mode. Intel Nonmultiplexed Mode (INM) MODE must be tied low to operate the AD6622 Microport in INM Mode. The access type is controlled by the user with the CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK) signal is produced by the Microport to communicate to the user the M icroport is ready for an access. RDY ( DTACK) goes low at the start of the access and is released when the internal cycle is complete. See the timing diagrams for both the read and write modes in the speci fications. Motorola Nonmultiplexed Mode (MNM) MODE must be tied high to operate the AD6622 microprocessor in MNM mode. The access type is controlled by the user with the CS, DS (RD), and R/W (WR) inputs. The DTACK (RDY) signal is produced by the Microport to acknowledge the comple- tion of an access to the user. DTACK (RDY) goes low when an internal access is complete and then will return high after DS (RD) is deasserted. See the timing diagrams for both the read and write modes in the Speci fications. The DTACK pin is configured as an open drain so that multiple devices may be tied together at the microprocessor/microcontroller without contention.

–22– REV. 0 External Address 7 Upper Address Register (Chan) Sets the three most signi ficant bits of the internal address, effec- tively selecting channels 1, 2, 3, or 4 (D2:D0). The autoincrement of read and write are also set (D7:D6). External Address 6 Lower Address Register (Addr) Sets the internal address 8 LSBs (D7:D0). External Address 5 Sync This register is read only. Bits in this address control the synchroni- zation of the AD6622 channels. If the user intends to bring up channels with no synchronization requirements, then all bits of this register should be written low. Two types of sync signals are available with the AD6622. The first is Soft Sync. Soft Sync is software synchronization enabled through the Microport. The second synchronization method is Pin Sync. Pin Sync is enabled by a signal applied to the sync pin (Pin 62). See the Synchroni- zation section of the data sheet for detailed explanations of the different modes. External Address 4 Reset Bits in this register determine how the chip is programmed and enables the channels. The program bits (D7:D4) must be set high to allow programming of CMEM and DMEM for each channel. Sleep bits (D3:D0) are used to activate or sleep channels. These can be used manually by the user to bring up a channel by simply writing the required channel high. These bits can also be used in conjunction with the Start and Sync signals avail- able in External Address 5 to synchronize the channels. See the Sy nchronization section of the data sheet for detailed expla- nation of different modes. External Address 3:0 (Data Bytes) These bits set the internal address to be accessed for a read or write. Table XII. External Memory Map External External Data Address D7 D6 D5 D4 D3 D2 D1 D0 7: Chan Wrinc Rdinc IA10 IA9 IA8 6: Addr IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 5: Sync Beam Hop Start Sync D Sync C Sync B Sync A 4: Reset Prog D Prog C Prog B Prog A Sleep D Sleep C Sleep B Sleep A 3: Byte3 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 2: Byte2 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 1: Byte1 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 0: Byte0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

–23–REV. 0 INTERNAL CONTROL REGISTERS AND ON-CHIP RAM Listed below is the mapping of internal AD6622 registers. Table XIII. Internal Memory Map Address Bit Width Name Notation Description Common Function Registers (Not Associated with a Particular Channel) 0x000 8 Summation MODE Control 0: Clip Wideband Output 1: Offset Binary Wideband Output 2: Reserved, Must Be Set High 3–7: Reserved, Should Be Set Low 0x001 8 Sync MODE Control 0: Ch. A Sync Pin Enable 1: Ch. B Sync Pin Enable 2: Ch. C Sync Pin Enable 3: Ch. D Sync Pin Enable 4: Start on Pin Sync 5: Hop on Pin Sync 6: Beam Steer on Pin Sync 7: First Sync Only Channel Function Registers (0x1XX = Ch. A, 0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D ) 0x100 16 Start Update Hold-Off Counter Start Update Hold Off Counter 0x101 8 NCO Control 1-0: Ch. A NCO Output Scale 2: Ch. A NCO Clear Phase Accum on Sync 3: Ch. A NCO Phase Dither Enable 4: Ch. A NCO Amp Dither Enable 7–5: Reserved 0x102 32 NCO Frequency Ch. A NCO Frequency Value 0x103 16 NCO Freq Hold Off Ch. A NCO Frequency Update Hold-Off Ctr 0x104 16 NCO Phase Offset Ch. A NCO Phase Offset 0x105 16 NCO Phase Hold Off Ch. A NCO Phase Offset Update Hold-Off Ctr 0x106 8 CIC Scale 4 –0: Ch. A CIC Scale 7–5: Reserved 0x107 8 Reserved 7 –0: Reserved 0x108 8 CIC2 Interpolation-1 Ch. A CIC2 Interpolation Factor-1 0x109 8 CIC5 Interpolation-1 Ch. A CIC5 Interpolation Factor-1 0x10A 8 RCF Coef ficient Count N RCF-1 6 –0: Ch. A RCF Coef ficient Count, N RCF–1 7: Reserved 0x10B 8 RCF Coef ficient Offset O RCF 6–0: Ch. A RCF Coef ficient Offset 7: Reserved 0x10C 8 Channel MODE Control 1 N RCF/LRCF-1 3 –0: Ch. A NRCF/LRCF–1 5–4: Ch. A Input Format: 00 = FIR 6: Reserved 7: Reserved 0x10D 8 Channel MODE Control 2 4 –0: Ch. A Serial Clock Divider 5: Ch. A Phase EQ Enable 7–6: Ch. A RCF Coarse Scale: 00 = 0 dB 01 = –6 dB 10 = –12 dB 11 = –18 dB 0x10E 16 15 –0: Reserved 0x10F 16 15 –0: Reserved 0x110 16 Reserved Reserved 0x111 16 Reserved Reserved 0x112–0x11F Reserved Reserved 0x120–0x13F 16 Data Memory Ch. A Data Memory 0x140–0x17F 16 Reserved Reserved 0x180–0x1FF 16 Coef ficient Memory Ch. A Coef ficient Memory Additional Channels 0x200–0x2FF Various Channel B Ch. B Registers (Organized as Ch. A Above) 0x300–0x3FF Various Channel C Ch. C Registers (Organized as Ch. A Above) 0x400-0x4FF Various Channel D Ch. D Registers (Organized as Ch. A Above)

–24– REV. 0 (0x000) Summation Mode Control Controls functions in the summation block of the AD6622. When set high, Bit 0 causes the output data to be clipped (no wrap- around) when overrange of the output occurs. When Bit 0 is low, overrange will result in wraparound. When set low, Bit 1 formats the output data as two's complement. Bit 1 set high will for- mat output data as offset binary. (0x001) Sync Mode Control Bits 3 –0 when high enable synchronization of these channels. See the Synchronization section of the data sheet for detailed explanation. Channel Function Registers The following registers are channel-speci fic. “0x” denotes that these values are represented as hexadecimal numbers. “n” repre- sents the specified channel. Valid channels are n = 1, 2, 3, and 4. (0xn00) Start Update Hold-Off Counter The Start Update Hold-Off Counter is used to synchronize start up of AD6622 channels and can be used to synchronize multiple chips. The Start Update Hold-Off Counter is clocked by the AD6622 CLK (master clock). See the Synchronization section of the data sheet for detailed explanation. If no synchronization is required, this register should be set to 0. (0xn01) NCO Control Bit 1:0 set the NCO scaling per the Table XIV. Table XIV. Control Scale 0x01 Bit 1 0x01 Bit 0 NCO Output Level 00 –6 dB 01 –12 dB 10 –18 dB 11 –24 dB Bit 2, when high, clears the NCO phase accumulator to 0 on either a Soft Sync or Pin Sync (see Synchronization for details). Bit 3, when high, enables NCO phase dither. Bit 4, when high, enables NCO amplitude dither. Bits 7:5 are reserved and should be written low. (0xn02) NCO Frequency This register is a 32-bit unsigned integer that sets the NCO Frequency. The NCO Frequency contains a shadow register for synchronization purposes. The shadow can be read back directly, the NCO Frequency cannot. NCO f CLK Frequency channel=×  232 (20) (0xn03) NCO Frequency Update Hold-Off Counter The Hold-Off Counter is used to synchronize the change of NCO frequencies. See the Synchronization section of the data sheet for detailed explanation. If no synchronization is required, this register should be set to 0. (0xn04) NCO Phase Offset This register is a 16-bit unsigned integer that is added to the phase accumulator of the NCO. This allows phase synchronization of multiple channels of the AD6622(s). See the Synchronization section of the data sheet for details. The NCO Phase Offset con- tains a shadow register for synchroni zation purposes. The shadow can be read back directly, the NCO Phase Offset cannot. (0xn05) NCO Phase Offset Update Hold-Off Counter The Hold-Off Counter is used to synchronize the change of NCO phases. See the Synchronization section of the data sh eet for detailed explanation. If no synchronization is required, this register should be set to 0. (0xn06) CIC Scale Bits 5:0 set the CIC scaling per the equation below. CIC Scale ceil L L CIC CIC_ (log ( ))=× 25 2 (21) See CIC section of the data sheet for details. Bits 7:6 are reserved and should be set to 0. (0xn07) Reserved This register is reserved and should be set to 0. (0xn08) CIC2 Interpolation – 1 This register sets the interpolation rate for the CIC2 filter stage (unsigned integer). The programmed value is the CIC2 Interpo- lation – 1. Maximum interpolation is limited by the CIC scaling available (See CIC section of the data sheet). (0xn09) CIC5 Interpolation – 1 This register sets the interpolation rate for the CIC5 filter stage (unsigned integer). The programmed value is the CIC5 Interpolation – 1. Maximum interpolation is limited by the CIC scaling available (See CIC section of the data sheet). (0xn0A) Number of RCF Coefficients – 1 This register sets the number of RCF Coef ficients and is limited to a maximum of 128. The programmed value is the number of RCF Coefficients – 1. (0xn0B) RCF Coefficient Offset This register sets the offset for RCF Coef ficients and is normally set to 0. It can be viewed as a pointer that selects the portion of the CMEM used when computing the RCF filter. This allows multiple filters to be stored in the coef ficient memory space, selecting the appropriate filter by setting the offset. (0xn0C) Channel Mode Control 1 Bits 3:0 set NRCF/LRCF-1. Bits 5:4 set the channel input format as shown below. Table XV. Filter Mode Bit 5 Bit 4 Input Mode 0 0 FIR 0 1 Reserved 1 0 Reserved 1 1 Reserved Bit 6 Reserved. Bit 7 Reserved. (0xn0D) Channel Mode Control 2 Bits 4:0 set the SCLK DIVIDER which determines the serial clock frequency based on the following equation. f CLK SCLK SCLK DIVIDER = ×+21 () (22)

–25–REV. 0 Bit 5 Reserved. Must be set low. Bits 7:6 set the RCF Coarse Scale as shown below. Table XVI. RCF Scaling Bit 7 Bit 6 RCF Coarse Scale 0 0 0 dB 01 –6 dB 10 –12 dB 11 –18 dB (0xn0E) Reserved (0xn0F) Reserved (0xn10) Reserved (Must Be Written to 0) (0xn11) Reserved (Must Be written to 0) (0xn12–0xn1F) Reserved (0xn20–0xn3F) Data Memory This group of registers contain the RCF Filter Data. See the RCF section of the data sheet for additional detail. (0xn40–0xn7F) Reserved (0xn80–0xnFF) Coefficient Memory This group of registers contain the RCF Filter Coef ficients. See the RCF section of the data sheet for additional detail. WRITE PSEUDOCODE Void Write_Micro(ext_address, int data); Main() /* This code shows the programming of the NCO frequency register using the Write_Micro function de fined above. The variable address is the External Address A[2:0] and data is the value to be placed in the external interface register. Internal Address = 0x102, channel 1 /*Holding registers for NCO byte wide access data */ int d3, d2, d1, d0; /*NCO frequency word (32 bits wide) */ NCO_FREQ=0x1BEFEFFF; /*write Chan */ Write_Micro(7, 0x01); /*write Addr */ Write_Micro(6,0x02); /*write Byte 3*/ d3=(NCO_FREQ & 0xFF000000)>>24; Write_Micro(3,d3); /*write Byte 2*/ d2=(NCO_FREQ & 0xFF0000)>>16; Write_Micro(2,d2); /*write Byte 1*/ d1=(NCO_FREQ & 0xFF00)>>8; Write_Micro(1,d1); /*write Byte 0, Byte 0 is written last and causes an internal write to occur*/ d0=NCO_FREQ & 0xFF; Write_Micro(0,d0); READ PSEUDOCODE Void Read_Micro(ext_address); Main() /* This code shows the reading of the NCO frequency register using the Read_Micro function de fined above. The variable address is the External Address A[2:0] Internal Address = 0x102, channel 1 /*Holding registers for NCO byte wide access data */ int d3, d2, d1, d0; /*NCO frequency word (32 bits wide) */ /*write Chan */ Write_Micro(7, 0x01); /*write Addr*/ Write_Micro(6,0x02); /*read Byte 0, all data is moved from the Internal Registers to the interface registers on this access, thus Byte 0 must be accessed first for the other Bytes to be valid */ d0=Read_Micro(0) & 0xFF; /*read Byte 1*/ d1=Read_Micro(1) & 0xFF; /*read Byte 2*/ d2=Read_Micro(2) & 0xFF; /*read Byte 0 */ d3=Read_Micro(3) & 0xFF; The AD6622 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the individual channel inputs. Implementation of a multichannel transmitter invariably begins with an analysis of the output sp ectrum that must be generated. DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION The selection of a high-performance DAC depends on a number of factors. The dynamic range of the DAC must be considered from a noise and spectral purity perspective. The 14-bit AD9754 and AD9772 are the best choices for overall bandwidth, noise, and spectral purity. In order to minimize the complexity of the analog interpolation filter which must follow the DAC, the sample rate of the master clock is generally set to at least three times the maximum analog frequency of interest. In the case where a 15 MHz band of interest is to be up-converted to RF, the lowest frequency might be 5 MHz and the upper band edge at 20 MHz (offset from dc to afford the best image reject filter after the first digital IF). The minimum sample rate would be set to 75 MSPS. Consideration must also be given to data rate of the incoming data stream, interpolation factors, and the clock rate of the DSP.

–26– REV. 0 MULTIPLE TSP OPERATION Each of the four Transmit Signal Processors (TSPs) of the AD6622 can adequately reject the interpolation images of nar- row bandwidth carriers such as AMPS, IS-136, GSM, EDGE, and PHS. Wider bandwidth carriers such as IS-95 and UMTS require a coordinated effort of multiple processing channels. This section demonstrates how to coordinate multiple TSPs to create wider bandwidth channels without sacri ficing image rejection. As an example, a UMTS carrier is modulated using four TSPs (an entire AD6622). The same principals can be applied to different designs using more or fewer TSPs. This sec- tion does not explore techniques for using multiple TSPs to solve problems other than Serial Port or RCF throughput. Designing filter coefficients and control settings for deint erleaved TSPs is no harder than designing a filter for a single TSP. For example, if four TSPs are to be used, simply divide the input data rate by four and generate the filter as normal. For any design, a better filter can always be realized by incrementing the number of TSPs to be used. When it is time to program the TSPs, only two small differences must be programmed. First each channel is con figured with exactly the same filter, scalars, modes and NCO frequency. Since each channel receives data at 1/4 the data rate and in a staggered fashion, the Start Hold-Off Counters must also be staggered (see Programming Multiple TSPs section below). Second, the phase offset of each NCO must be set to match the demultiplexed ratio (1/4 in this example). Thus the phase offset should be set to 90 degrees (16384, which is 1/4 of a 16-bit register). Determining the Number of TSPs to Use There are three limitations of a single TSP that can be over- come by deinterleaving an input stream into multiple TSPs: Serial Port bandwidth, the time restriction to the RCF impulse response length (N RCF), and the DMEM restriction to N RCF. If the input sample rate is faster than the Serial Port can accept data, the data can be deinterleaved into multiple Serial Ports. Recalling from the Serial Port description, the SCLK frequency SCLK) is determined by the equation below. To minimize the number of processing channels, SCLK DIVIDER should be set as low as possible to get the highest f SCLK that the serial data source can accept. f f SCLK SCLK CLK DIVIDER = ×+21 () (23) A minimum of 32 SCLK cycles are required to accept an input sample, so the minimum number of TSPs (N TSP) due to limited Serial Port bandwidth is a function of the input sample rate (fIN), as shown by the equation below. N ceil f f TSP IN SCLK ≥ × (24) For a sample UMTS system, we will assume f CLK = 61.44 MHz, and the serial data source can drive data at 30.72 MBPS (SCLKDIVIDER = 0). To achieve f IN = 3.84 MHz, the mini- mum NTSP is 4. (This is TSP channels, not TSP ICs.) Multiple TSPs are also required if the RCF does not have enough time or DMEM space to calculate the required RCF filter. Recall- ing the maximum NTAPS equation from the RCF description, are three restrictions to the RCF impulse response length, N RCF. Time CMEM Restriction Restriction N L LRCF RCF≤×  DMEM Restriction where: LL L L Nf f RCF CIC CIC TSP CLK IN =×× = × Deinterleaving the input data into multiple TSPs will extend the time restriction and may possibly extend the DMEM restriction, but will not extend the CMEM restriction. Deinterleaving the input stream to multiple TSPs divides the input sample rate to each TSP by the number of TSPs used (N TSP). To keep the out- put rate fixed, L must be increased by a factor of N CH, which extends the time restriction. This increase in L may be achieved by increasing any one or more of L RCF, LCIC5, or LCIC2 within their normal limits. Achieving a larger L by increasing L RCF instead of LCIC5 or LCIC2, will relieve the DMEM restriction as well. In a UMTS example, NTSP = 4, fCLK = 61.44 MHz, and fIN = 3.84 MHz, resulting in L = 64. Factoring L into LRCF = 8, LCIC = 8, and LCIC2 = 1, results in a maximum NRCF = 32 due to the time restriction. Figure 22 shows an example RCF impulse response that has a frequency response as shown in Figure 23 from 0 Hz to 7.68 MHz (f IN × LRCF/NTSP). The composite RCF and CIC frequency response is shown in Figure 24, on the same fre- quency scale. This figure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a pass-band ripple of 0.1 dB, and a stopband ripple better than –65 dB until the lobe of the first image which peaks at –50 dB about 5.6 MHz from the carrier center. This lobe could be reduced by shifting more of the interpolation towards the RCF, but that would sacrifice near-in performance. As shown, the first image can easily be rejected by an analog filter further up the signal path. Scaling must be considered as normal with an interpolation factor of L, to guarantee no overflow in the RCF, CIC, or NCOs. The output level at the summation port should be calculated using an interpolation factor of L/N TSP. Programming Multiple TSPs Configuring the TSPs for deinterleaved operation is straight- forward. All of the Channel Registers and CMEM of each TSP are programmed identically, except the Start Hold-Off Counters and NCO Phase Offset. In order to separate the input timing to each TSP, the Hold- Off Counters must be used to start each TSP successively in response to a common Start SYNC. The Start SYNC may origi- nate from the SYNC pin or the Microport. Each subsequent TSP must have a Hold-Off Counter value L/N TSP larger than its predecessor ’s. If the TSPs are located on cascaded AD6622s, the Hold-Off Counters of the upstream device should be incre- mented by an additional one. In the UMTS example, L = 64 and N TSP = 4, so in order to respond as quickly as possible to a Start SYNC, the Hold-Off Counter values should be 1, 17, 33, and 49.

–28– C3772–8–5/00 (rev. 0) 00968 PRINTED IN U.S.A. AD6622 REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 128-Lead MQFP (Metric Quad Flatpack) (S-128A) TOP VIEW (PINS DOWN) 102 128 103 0.011 (0.27) 0.007 (0.17) 0.020 (0.50) BSC 0.555 (14.10) 0.547 (13.90) 0.685 (17.40) 0.669 (17.00) 0.791 (20.10) 0.783 (19.90) 0.921 (23.40) 0.906 (23.00) 0.041 (1.03) 0.031 (0.78) SEATING PLANE 0.134 (3.40) MAX 0.003 (0.08) MAX 0.010 (0.25) MIN 0.110 (2.80) 0.102 (2.60)