AD660SQ

AD660 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

+10V REF 16-BIT LATCH 51112 15 14 AD660 10k 10.05k 10k SIN/ DB0 DB7 SOUT SPAN/ BIP OFFSET V OUT AGND REF OUT REF IN LDAC SER DGND–VEE +VCC +VLL 1 2 3 4 LBE CS HBE CLR MSB/LSB/ DB1 UNI/BIP CLR/ REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Monolithic 16-Bit Serial/Byte DACPORT AD660

FEATURES

Complete 16-Bit D/A Function On-Chip Output Amplifier On-Chip Buried Zener Voltage Reference

61 LSB Integral Linearity

15-Bit Monotonic over Temperature Microprocessor Compatible Serial or Byte Input Double Buffered Latches Fast (40 ns) Write Pulse Asynchronous Clear (to 0 V) Function Serial Output Pin Facilitates Daisy Chaining Unipolar or Bipolar Output Low Glitch: 15 nV-s Low THD+N: 0.009% Tel: 617/329-4700 Fax: 617/326-8703 PRODUCT DESCRIPTION The AD660 DACPORT is a complete 16-bit monolithic D/A converter with an on-board voltage reference, double buffered latches and output amplifier. It is manufactured on Analog De- vices’ BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high pre- cision bipolar linear circuitry. The AD660’s architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is maintained at ± 0.003% max. The on-chip output amplifier pro- vides a voltage output settling time of 10 µs to within 1/2 LSB for a full-scale step. The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins which have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy chain several AD660s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required to SIN, CS and LDAC. The byte mode input for- mat is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. The AD660 is available in five grades. AN and BN versions are specified from –40°C to +85°C and are packaged in a 24-pin 300 mil plastic DIP. AR and BR versions are also specified from –40°C to +85°C and are packaged in a 24-pin SOIC. The SQ version is packaged in a 24-pin 300 mil cerdip package and is also available compliant to MIL-STD-883. Refer to the AD660/ 883B data sheet for specifications and test conditions. DACPORT is a registered trademark of Analog Devices, Inc. PRODUCT HIGHLIGHTS 1. The AD660 is a complete 16-bit DAC, with a voltage refer- ence, double buffered latches and output amplifier on a sin- gle chip. 2. The internal buried Zener reference is laser trimmed to 10.000 volts with a ± 0.1% maximum error and a tempera- ture drift performance of ± 15 ppm/°C. The reference is available for external applications. 3. The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of –10 V to +10 V. No external com- ponents are required. 4. The AD660 is both dc and ac specified. DC specifications include ± 1 LSB INL and ± 1 LSB DNL errors. AC specifi- cations include 0.009% THD+N and 83 dB SNR. 5. The double buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multi-DAC applications. 6. The CLEAR function can asynchronously set the output to

0 V regardless of whether the DAC is in unipolar or bipolar

mode. 7. The output amplifier settles within 10 µs to ± 1/2 LSB for a full-scale step and within 2.5 µs for a 1 LSB step over tem- perature. The output glitch is typically 15 nV-s when a full- scale step is loaded.

AD660–SPECIFICATIONS (TA = +258C, VCC = +15 V, VEE = –15 V, V LL = +5 V unless otherwise noted) AD660AN/AR/SQ AD660BN/BR Parameter Min Typ Max Min Typ Max Units RESOLUTION 16 16 Bits DIGITAL INPUTS (T MIN to TMAX) VIH (Logic “1”) 2.0 5.5 * * Volts VIL (Logic “0”) 0 0.8 * * Volts IIH (VIH = 5 5 V) ± 10 * µA IIL (VIL = 0 V) ± 10 * µA TRANSFER FUNCTION CHARACTERISTICS 1 Integral Nonlinearity ± 2 ± 1 LSB TMIN to TMAX ± 4 ± 2 LSB Differential Nonlinearity ± 2 ± 1 LSB TMIN to TMAX ± 4 ± 2 LSB Monotonicity Over Temperature 14 15 Bits Gain Error 2, 3 ± 0.10 * % of FSR Gain Drift (TMIN to TMAX) 25 15 ppm/ °C DAC Gain Error 4 ± 0.05 * % of FSR DAC Gain Drift 4 10 * ppm/ °C Unipolar Offset ± 2.5 * mV Unipolar Offset Drift (T MIN to TMAX) 3 * ppm/ °C Bipolar Zero Error ± 7.5 * mV Bipolar Zero Error Drift (T MIN to TMAX) 5 * ppm/ °C REFERENCE INPUT Input Resistance 7 10 13 * * * k Ω Bipolar Offset Input Resistance 7 10 13 * * * k Ω REFERENCE OUTPUT Voltage 9.99 10.00 10.01 * * * Volts Drift 25 15 ppm/ °C External Current 5 24 * * m A Capacitive Load 1000 * pF Short Circuit Current 25 * mA OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration 0 +10 * * Volts Bipolar Configuration –10 +10 * * Volts Output Current 5 * mA Capacitive Load 1000 * pF Short Circuit Current 25 * mA POWER SUPPLIES Voltage VCC VEE VLL +4.5 +5.5 * * Volts Current (No Load) ICC +12 +18 * * mA IEE –12 –18 * * mA ILL @ VIH, VIL = 5, 0 V 0.3 2 * * mA @ VIH, VIL = 2.4, 0.4 V 3 7.5 * * mA Power Supply Sensitivity 1 2 * * ppm/% Power Dissipation (Static, No Load) 365 625 * * mW TEMPERATURE RANGE Specified Performance (A, B) –40 +85 * * °C Specified Performance (S) –55 +125 °C NOTES Full-Scale Range and is 10 V in a Unipolar Mode and 20 V in Bipolar Mode. 2Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660 can be used with a precision external reference such as the AD587, AD586 or AD688. 3Gain Error is measured with fixed 50 Ω resistors as shown in the Application section. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). 4DAC Gain Error and Drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference. 5External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660. 6Operation on ± 12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. *Indicates that the specification is the same as AD660AN/AR/SQ. Specifications subject to change without notice. REV. A–2–

REV. A –3– (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. T MIN ≤ TA ≤ TMAX, VCC = +15 V, VEE = –15 V, V LL = +5 V except where noted.) Parameter Limit Units Test Conditions/Comments Output Settling Time 13 µs max 20 V Step, T A = +25°C (Time to ± 0.0008% FS 8 µs typ 20 V Step, T A = +25°C with 2 kΩ , 1000 pF Load) 10 µs typ 20 V Step, T MIN ≤ TA ≤ TMAX 6 µs typ 10 V Step, T A = +25°C 8 µs typ 10 V Step, T MIN ≤ TA ≤ TMAX 2.5 µs typ 1 LSB Step, T MIN ≤ TA ≤ TMAX Total Harmonic Distortion + Noise A, B, S Grade 0.009 % max 0 dB, 990.5 Hz; Sample Rate = 96 kHz; T A = +25°C A, B, S Grade 0.056 % max –20 dB, 990.5 Hz; Sample Rate = 96 kHz; T A = +25°C A, B, S Grade 5.6 % max –60 dB, 990.5 Hz; Sample Rate = 96 kHz; T A = +25°C Signal-to-Noise Ratio 83 dB min T A = +25°C Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000 H and 7FFFH Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000 H and FFFFH; CS High Output Noise Voltage 120 nV/ √Hz typ Measured at V OUT; 20 V Span; Excludes Reference Density (1 kHz – 1 MHz) Reference Noise 125 nV/ √Hz typ Measured at REF OUT Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* +7.0 V VCC, VEE, and VLL Power Dissipation (Any Package) Lead Temperature Range *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION 6 19 TOP VIEW (Not to Scale) AD660 DB7, 15 SOUT SPAN, BIPOLAR OFFSET VOUT AGND REF OUT REF IN LDAC DGND –VEE +VCC +VLL CS HBE SER CLR DB6, 14 DB5, 13 DB4, 12 DB3, 11 DB2, 10 DB0, 8, SIN DB1, 9, MSB/LSB LBE, UNI/BIP CLEAR

REV. A–4– ORDERING GUIDE Temperature Linearity Error Max Linearity Error Max Gain TC max Package Package Model Range +25 °CT MIN – TMAX ppm/°C Description Option* AD660AN –40 °C to +85°C ± 2 LSB ± 4 LSB 25 Plastic DIP N-24 AD660AR –40 °C to +85°C ± 2 LSB ± 4 LSB 25 SOIC R-24 AD660BN –40 °C to +85°C ± 1 LSB ± 2 LSB 15 Plastic DIP N-24 AD660BR –40 °C to +85°C ± 1 LSB ± 2 LSB 15 SOIC R-24 AD660SQ –55 °C to +125°C ± 2 LSB ± 4 LSB 25 Cerdip Q-24 *N = Plastic DIP; Q = Cerdip; R = SOIC. **Refer to AD660/883B military data sheet. TIMING CHARACTERISTICS VCC = +15 V, VEE = –15 V, V LL = +5 V, VHI = 2.4 V, VLO = 0.4 V Parameter Limit +25 °C Limit –55 °C to +125°C Units (Figure la) tCS 40 50 ns min tDS 40 50 ns min tDH 0 10 ns min tBES 40 50 ns min tBEH 0 10 ns min tLH 80 100 ns min tLW 40 50 ns min (Figure lb) tCLK 80 100 ns min tLO 30 50 ns min tHI 30 50 ns min tSS 0 10 ns min tDS 40 50 ns min tDH 0 10 ns min tSH 0 10 ns min tLH 80 100 ns min tLW 40 50 ns min (Figure lc) tCLR 80 110 ns min tSET 80 110 ns min tHOLD 0 10 ns min (Figure ld) tPROP 50 100 ns min tDS 50 80 ns min Specifications subject to change without notice. tLWtLH tCS tDHtDS BIT 0–7 HBE OR LBE CS LDAC tBES tBEH Figure 1a. AD660 Byte Load Timing

cise biasing for the offset trim resistor R4. Figure 5. Using the AD660 with the AD586 5 V Reference

0 TO +10V

Figure 6. Using the AD660 with the AD688 High Precision ±10 V Reference

the second rank register from the first rank register. Figure 7. Output Characteristics does not care about the status of HBE when in serial mode. loaded into the first rank latch if desired.

REV. A–12– C1813a–15–7/93PRINTED IN U.S.A. GROUNDING The AD660 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the “high quality” ground reference point for the device. Any exter- nal loads on the output of the AD660 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground. If a single AD660 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD660. If multiple AD660s are used or the AD660 shares ana- log supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-24 24-Lead Plastic DIP 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC PIN 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.280 (7.11) 0.240 (6.10) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 1.275 (32.30) 1.125 (28.60) Q-24 24-Lead Cerdip 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15° 1.060 (26.92) MAX 0.200 (5.08) MAX 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.005 (0.13) MIN PIN 1 0.098 (2.49) MAX 0.310 (7.87) 0.220 (5.59) R-24 24-Lead Small Outline (SOIC) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25) x 45° PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 121 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.1043 (2.65) 0.5985 (15.20) 0.0118 (0.30) 0.0040 (0.10)