AD660AR-REEL

AD660_08 AD | Alldatasheet

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Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.

FEATURES

Complete 16-bit digital-to-analog function On-chip output amplifier On-chip buried Zener voltage reference ±1 LSB integral linearity 15-bit monotonic over temperature Microprocessor compatible Serial or byte input Double-buffered latches Fast (40 ns) write pulse Asynchronous clear (to 0 V) function Serial output pin facilitates daisy-chaining Unipolar or bipolar output Low glitch: 15 nV-s Low THD + N: 0.009% FUNCTIONAL BLOCK DIAGRAM HBE CONTROL LOGICSER CLR LDAC REF IN 10kΩ 10kΩ 10.05kΩ REF OUT CS DB7/ DB15 AD660 SOUT VOUT AGND SPAN/ BIPOLAR OFFSET DGND–VEE +VCC +VLL 10V REF 16-BIT LATCH 16-BIT DAC 16-BIT LATCH16 1 2 3 4 121415 01813-001 DB1/DB9/ DATADIR LBE/ CLEAR SELECT DB0/ DB8/ SIN Figure 1. GENERAL DESCRIPTION The AD660 DACPORT® is a complete 16-bit monolithic digital- to-analog converter with an on-board voltage reference, double- buffered latches, and an output amplifier. It is manufactured on the Analog Devices, Inc., BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD660 architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is main- tained at ±0.003% maximum. The on-chip output amplifier provides a voltage output settling time of 10 μs to within ½ LSB for a full-scale step. The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins that have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy- chain several AD660 devices by shifting the data through the input latch into the next DAC, thus minimizing the number of control lines required to SIN, CS and LDAC. The byte mode input format is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multiDAC system. The AD660 is available in five grades. AN and BN versions are specified from −40°C to +85°C and are packaged in a 24-lead 300 mil plastic DIP . AR and BR versions are also specified from −40°C to +85°C and are packaged in a 24-lead SOIC. The SQ version is packaged in a 24-lead 300 mil CERDIP package and is also available compliant to MIL-STD-883. Refer to the AD660SQ/883B military data sheet for specifications and test conditions. PRODUCT HIGHLIGHTS 1. The AD660 is a complete 16-bit DAC, with a voltage reference, double-buffered latches, and an output amplifier on a single chip. 2. The internal buried Zener reference is laser trimmed to 10.000 V with a ±0.1% maximum error and a temperature drift performance of ±15 ppm/°C. The reference is available for external applications. 3. The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to 10 V or a bipolar output range of −10 V to +10 V . No external components are required. 4. The AD660 is both dc and ac specified. DC specifications include ±1 LSB INL and ±1 LSB DNL errors. AC specifica- tions include 0.009% THD + N and 83 dB SNR. 5. The double-buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multiDAC applications. 6. The clear function can asynchronously set the output to 0 V regardless of whether the DAC is in unipolar or bipolar mode. 7. The output amplifier settles within 10 μs to ±½ LSB for a full-scale step and within 2.5 μs for a 1 LSB step over tempera- ture. The output glitch is typically 15 nV-s when a full-scale step is loaded.

Rev. B | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

6/08—Rev. A to Rev. B Updated Pin Name UNI/BIP CLEAR to CLEAR SELECT Added Pin Configuration and Function Descriptions Section ... 8

Rev. B | Page 3 of 20 SPECIFICATIONS TA = 25°C, +VCC = 15 V , −VEE = −15 V , +VLL = 5 V unless otherwise noted. Table 1. Parameter AD660AN/AR/SQ AD660BN/BR Unit Min Typ Max Min Typ Max RESOLUTION 16 16 Bits DIGITAL INPUTS (TMIN to TMAX) VIH (Logic 1) 2.0 5.5 2.0 5.5 V VIL (Logic 0) 0 0.8 0 0.8 V IIH (VIH = 5.5 V) −10 +10 −10 +10 μA IIL (VIL = 0 V) −10 +10 −10 +10 μA TRANSFER FUNCTION CHARACTERISTICS1 Integral Nonlinearity Bipolar Operation −2 +2 −1 +1 LSB TMIN to TMAX −4 +4 −2 +2 LSB Unipolar Operation −2 +2 −1 +1.5 LSB TMIN to TMAX −4 +4 −2 +2 LSB Differential Nonlinearity −2 +2 −1 +1 LSB TMIN to TMAX −4 +4 −2 +2 LSB Monotonicity Over Temperature 14 15 Bits Gain Error2, 3 −0.1 +0.1 −0.1 +0.1 % of FSR Gain Drift (TMIN to TMAX) 25 15 ppm/°C DAC Gain Error4 −0.05 +0.05 −0.05 +0.05 % of FSR DAC Gain Drift4 10 10 ppm/°C Unipolar Offset −2.5 +2.5 −2.5 +2.5 mV Unipolar Offset Drift (TMIN to TMAX) 3 3 ppm/°C Bipolar Zero Error −7.5 +7.5 −7.5 +7.5 mV Bipolar Zero Error Drift (TMIN to TMAX) 5 5 ppm/°C REFERENCE INPUT Input Resistance 7 10 13 7 10 13 kΩ Bipolar Offset Input Resistance 7 10 13 7 10 13 kΩ REFERENCE OUTPUT Drift 25 15 ppm/°C External Current5 2 4 2 4 mA Capacitive Load 1000 1000 pF Short-Circuit Current 25 25 mA OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration 0 +10 0 +10 V Bipolar Configuration −10 +10 −10 +10 V Output Current 5 5 mA Capacitive Load 1000 1000 pF Short-Circuit Current 25 25 mA

Rev. B | Page 4 of 20 Parameter AD660AN/AR/SQ AD660BN/BR Unit Min Typ Max Min Typ Max POWER SUPPLIES Voltage Current (No Load) ICC +12 +18 +12 +18 mA IEE −12 −18 −12 −18 mA ILL @ VIH = 5 V, VIL = 0 V 0.3 2 0.3 2 mA @ VIH = 2.4 V, VIL = 0.4 V 3 7.5 3 7.5 mA Power Supply Sensitivity 1 2 1 2 ppm/% Power Dissipation (Static, No Load) 365 625 365 625 mW TEMPERATURE RANGE Specified Performance (A, B) −40 +85 −40 +85 °C Specified Performance (S) −55 +125 °C and is 10 V in a unipolar mode and 20 V in bipolar mode. 2 Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660 can be used with a precision external reference such as the AD587, AD586, or AD688. 3 Gain error is measured with fixed 50 Ω resistors as shown in the Theory of Operation section. Eliminating these resistors increases the gain error by 0.25% of FSR (unipolar mode) or 0.50% of FSR (bipolar mode). 4 DAC gain error and drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference. 5 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660. 6 Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference Use section. AC PERFORMANCE CHARACTERISTICS With the exception of total harmonic distortion + noise (THD + N) and signal-to-noise (SNR) ratio, these characteristics are included for design guidance only and are not subject to test. THD + N and SNR are 100% tested. TMIN ≤ TA ≤ TMAX, +VCC = 15 V , −VEE = −15 V , +VLL = 5 V except where noted. Table 2. Parameter Limit Unit Test Conditions/Comments OUTPUT SETTLING TIME 13 μs max 20 V step, T A = 25°C (Time to ±0.0008% FS 8 μs typ 20 V step, T A = 25°C with 2 kΩ, 1000 pF Load) 10 μs typ 20 V step, T MIN ≤ TA ≤ TMAX 6 μs typ 10 V step, T A = 25°C 8 μs typ 10 V step, T MIN ≤ TA ≤ TMAX 2.5 μs typ 1 LSB step, T MIN ≤ TA ≤ TMAX TOTAL HARMONIC DISTORTION + NOISE A, B, S Grade 0.009 % max 0 dB, 990.5 Hz, sample rate = 96 kHz, T A = 25°C A, B, S Grade 0.056 % max −20 dB, 990.5 Hz, sample rate = 96 kHz, T A = 25°C A, B, S Grade 5.6 % max −60 dB, 990.5 Hz, sample rate = 96 kHz, T A = 25°C SIGNAL-TO-NOISE RATIO 83 dB min T A = 25°C DIGITAL-TO-ANALOG GLITCH IMPULSE 15 nV-s typ DAC alternately loaded with 0x8000 and 0x7FFF DIGITAL FEEDTHROUGH 2 nV-s typ DAC alternately loaded with 0x0000 and 0xFFFF, CS high OUTPUT NOISE VOLTAGE Density (1 kHz to 1 MHz) 120 nV/√Hz typ Measured at V OUT, 20 V span, excludes reference REFERENCE NOISE 125 nV/√Hz typ Measured at REF OUT

Figure 2. AD660 Byte Load Timing

Rev. B | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating +VCC to AGND −0.3 V to +17.0 V −VEE to AGND +0.3 V to −17.0 V +VLL to DGND −0.3 V to +7 V AGND to DGND ±1 V Digital Inputs (Pin 5 through Pin 23) to DGND −1.0 V to +7.0 V REF IN to AGND ±10.5 V SPAN/BIPOLAR OFFSET to AGND ±10.5 V REF OUT, VOUT Indefinite short to AGND, DGND, +VCC, −VEE, and +VLL Power Dissipation (Any Package) To +60°C 1000 mW Derates Above +60°C 8.7 mW/°C Storage Temperature −65°C to +150°C Lead Temperature JEDEC industry standard Soldering J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 6. Pin Configuration Table 5. Pin Function Descriptions

4 DGND Digital Ground Reference Pin

5 DB7/DB15 DB7 and DB15 Byte Load Data Input Pin

6 DB6/DB14 DB6 and DB14 Byte Load Data Input Pin

7 DB5/DB13 DB5 and DB13 Byte Load Data Input Pin

8 DB4/DB12 DB4 and DB12 Byte Load Data Input Pin

9 DB3/DB11 DB3 and DB11 Byte Load Data Input Pin

10 DB2/DB10 DB2 and DB10 Byte Load Data Input Pin

12 DB0/DB8/SIN DB0 and DB8 Byte Load Data Input Pin/Serial Data Input Pin

13 S OUT Serial Data Output Pin

14 CS Chip Select Pin

15 LBE/CLEAR SELECT Low Byte Enable Pin/Unipolar or Bipolar Clear Select Pin

16 HBE High Byte Enable Pin

17 SER Serial Input Enable Pin

18 CLR Output Clear Pin

19 LDAC Load DAC Pin

20 AGND Analog Ground Reference Pin

21 V OUT Voltage Output Pin

22 SPAN/BIPOLAR OFFSET Output Span Configuration Pin

23 REF IN External Reference Voltage Input Pin

24 REF OUT Internal Reference Voltage Output Pin

Rev. B | Page 9 of 20 TERMINOLOGY Integral Nonlinearity Integral nonlinearity is the maximum deviation of the actual, adj usted DAC output from the ideal analog output (a straight line drawn from 0 to FS − 1 LSB) for any bit combination. This is also referred to as relative accuracy. Differential Nonlinearity Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than or equal to −1 LSB over the temperature range of interest. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output is always a single-valued function of the input. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Offset Error Offset error is a combination of the offset errors of the voltage- mode DAC and the output amplifier and is measured with all 0s loaded in the DAC. Bipolar Zero Error When the AD660 is connected for bipolar output and 10…000 is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. Drift Drift is the change in a parameter (such as gain, offset, and bipolar zero) over a specified temperature range. The drift temperature coefficient, specified in ppm/°C, is calculated by measuring the parameter at T MIN, 25°C, and TMAX, and dividing the change in the parameter by the corresponding temperature change. Total Harmonic Distortion + Noise Total harmonic distortion + noise (THD + N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%). THD + N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error, and noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, to be the most useful, THD + N should be specified for both large and small signal amplitudes. Signal-To-Noise Ratio The signal-to-noise ratio is the ratio of the amplitude of the output when a full-scale signal is present to the output with no signal present. The signal-to-noise ratio is measured in decibels (dB). Digital-To-Analog Glitch Impulse Digital-to-analog glitch impulse is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is measured at half scale when the DAC switches around the MSB and as many as possible switches change state, that is, from 011…111 to 100…000. Digital Feedthrough When the DAC is not selected (that is, CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.

Rev. B | Page 14 of 20 DIGITAL CIRCUIT DETAILS The AD660 has several dual-use pins that allow flexible opera- tion while maintaining the lowest possible pin count and consequently the smallest package size. The user should, therefore, pay careful attention to the following information when applying the AD660. Data can be loaded into the AD660 in serial or byte mode, described as follows. Serial mode operation is enabled by bringing SER (Pin 17) low. This changes the function of DB0 (Pin 12) to that of the serial input pin, SIN. It also changes the function of DB1 (Pin 11) to a control input that tells the AD660 whether the serial data is going to be loaded MSB or LSB first. In serial mode, HBE and LBE are effectively disabled except for the dual function of LBE, which is to control whether the asynchronous clear function goes to unipolar or bipolar zero. (A low on LBE , when CLR is strobed, sends the DAC output to unipolar zero, a high to bipolar zero.) The AD660 does not recognize the status of HBE when in serial mode. Data is clocked into the input register on the rising edge of CS, as shown in Figure 3. The data then resides in the first rank latch and can be loaded into the DAC latch by taking LDAC high. This causes the DAC to change to the appropriate output value. It should be noted that the CLR function clears the DAC latch but does not clear the first rank latch. Therefore, the data that was previously residing in the first rank latch can be reloaded simply by bringing LDAC high after the event that necessitated CLR to be strobed has ended. Alternatively, new data can be loaded into the first rank latch if desired. The serial out pin (SOUT) can be used to daisy-chain several DACs together in multiDAC applications to minimize the number of isolators being used to cross an intrinsic safety barrier. The first rank latch acts like a 16-bit shift register, and repeated strobing of CS shifts the data out through SOUT and into the next DAC. Each DAC in the chain requires its own LDAC signal unless all of the DACs are to be updated simultaneously. Byte mode operation is enabled simply by keeping SER high, which configures DB0 to DB7 as data inputs. In this mode, HBE and LBE are used to identify the data as either the high byte or the low byte of the 16-bit input word. (The user can load the data, in any order, into the first rank latch.) As in the serial mode case, the status of LBE, when CLR is strobed, determines whether the AD660 clears to unipolar or bipolar zero. Therefore, when in byte mode, the user must take care to set LBE to the desired status before strobing CLR. (In serial mode the user can simply hardware LBE to the desired state.) Note that CS is edge triggered. HBE, LBE, and LDAC are level triggered.

Rev. B | Page 17 of 20 BOARD LAYOUT Designing with high resolution data converters requires careful attention to board layout. Trace impedance is the first issue. A 306 μA current through a 0.5 Ω trace develops a voltage drop of 153 μV , which is 1 LSB at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. One feature that the AD660 incorporates to help the user layout is that the analog pins (+V CC, −VEE, REF OUT, REF IN, SPAN/ BIPOLAR OFFSET, VOUT and AGND) are adjacent to help isolate analog signals from digital signals. SUPPLY DECOUPLING The AD660 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate spikes, which can induce noise in the analog system. Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, while VLL should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD660, associated analog circuitry, and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD660 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. GROUNDING The AD660 has two ground pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the high quality ground reference point for the device. Any external loads on the output of the AD660 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground. If a single AD660 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD660. If multiple AD660 devices are used or the AD660 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 24-Lead Standard Small Outline Package [SOIC_W] 2 For further details, refer to the AD660SQ/883B military data sheet.

Rev. B | Page 20 of 20 NOTES ©1993–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D01813-0-6/08(B)