AD652KPZ-REEL AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
Voltage-to-Frequency Converter AD652 Rev. C Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Full-scale frequency (up to 2 MHz) set by external system clock Extremely low linearity error (0.005% max at 1 MHz FS, 0.02% max at 2 MHz FS) No critical external components required Accurate 5 V reference voltage Low drift (25 ppm/°C max) Dual- or single-supply operation Voltage or current input MIL-STD-883 compliant versions available PRODUCT DESCRIPTION The AD652 synchronous voltage-to-frequency converter (SVFC) is a powerful building block for precision analog-to- digital conversion, offering typical nonlinearity of 0.002% (0.005% maximum) at a 100 kHz output frequency. The inher- ent monotonicity of the transfer function and wide range of clock frequencies allow the conversion time and resolution to be optimized for specific applications. The AD652 uses a variation of the charge-balancing technique to perform the conversion function. The AD652 uses an external clock to define the full-scale output frequency, rather than relying on the stability of an external capacitor. The result is a more stable, more linear transfer function, with significant application benefits in both single- and multichannel systems. Gain drift is minimized using a precision low drift reference and low TC, on-chip, thin-film scaling resistors. Furthermore, initial gain error is reduced to less than 0.5% by the use of laser- wafer-trimming. The analog and digital sections of the AD652 have been designed to allow operation from a single-ended power source, simplifying its use with isolated power supplies. The AD652 is available in five performance grades. The 20-lead PLCC-packaged JP and KP grades are specified for operation over the 0°C to +70°C commercial temperature range. The 16-lead CERDIP-packaged AQ and BQ grades are specified for operation over the −40°C to +85°C industrial temperature range. The AD652SQ is available for operation over the full −55°C to +125°C extended temperature range. PRODUCT HIGHLIGHTS 1. The use of an external clock to set the full-scale frequency allows the AD652 to achieve linearity and stability far superior to other monolithic VFCs. By using the same clock to drive the AD652 and set the counting period (through a suitable divider), conversion accuracy is maintained independent of variations in clock frequency. 2. The AD652 synchronous VFC requires only one external component (a noncritical integrator capacitor) for operation. 3. The AD652 includes a buffered, accurate 5 V reference. 4. The AD652’s clock input is TTL and CMOS compatible and can also be driven by sources referred to the negative power supply. The flexible open-collector output stage provides sufficient current sinking capability for TTL and CMOS logic, as well as for optical couplers and pulse transformers. A capacitor-programmable one-shot is provided for selec- tion of optimum output pulse width for power reduction. 5. The AD652 can also be configured for use as a synchronous F/V converter for isolated analog signal transmission. 6. The AD652 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD652/883B data sheet for detailed specifications. FUNCTIONAL BLOCK DIAGRAM COMPARATOR AND CK QD G Q D Q D FLOP LATCH CLOCK IN ONE SHOT COS CINT RIN INTEGRATOR HL 1mA –VS VIN 00798-001 Figure 1.
Rev. C | Page 2 of 28 TABLE OF CONTENTS SVFC Connection for Dual Supply, Positive Input Voltages .. 9
REVISION HISTORY
5/04—Data Sheet Changed from Rev. B to Rev. C 2/00—Data Sheet Changed from Rev. A to Rev. B
Rev. C | Page 3 of 28 SPECIFICATIONS Typical @ TA = 25°C, VS = ±15 V , unless otherwise noted. Specifications in boldface are 100% tested at final test and are used to measure outgoing quality levels. Table 1. AD652JP/AQ/SQ AD652KP/BQ Parameter Min Typ Max Min Typ Max Unit VOLTAGE-TO-FREQUENCY MODE Gain Error fCLOCK= 200 kHz ±0.5 ±1 ±0.25 ±0.5 % fCLOCK = 1 MHz ±0.5 ±1 ±0.25 ±0.5 % Gain Temperature Coefficient fCLOCK = 200 kHz ±25 ±50 ±15 ±25 ppm/°C fCLOCK = 1 MHz ±25 ±50 ±15 ±25 ppm/°C fCLOCK = 4 MHz ±25 ±75 ±15 ±50 ppm/°C Power Supply Rejection Ratio 0.001 0.01 0.001 0.01 %/V Linearity Error fCLOCK = 200 kHz ±0.002 ±0.02 ±0.002 ±0.005 % fCLOCK = 1 MHz ±0.002 ±0.02 ±0.002 ±0.005 % fCLOCK = 2 MHz ±0.01 ±0.02 ±0.002 ±0.005 % fCLOCK = 4 MHz ±0.02 ±0.05 ±0.01 ±0.02 % Offset (Transfer Function, RTI) ± 1 ±3 ±1 ±2 mV Offset Temperature Coefficient ±10 ±50 ±10 ±25 µV/°C Response Time One Period of New Output Frequency Plus One Clock Period. FREQUENCY-TO-VOLTAGE MODE Gain Error, fIN = 100 kHz FS ±0.5 ±1 ±0.25 ±0.5 % Linearity Error, fIN = 100 kHz FS ±0.002 ±0.02 ±0.002 ±0.01 % INPUT RESISTORS CERDIP (Figure 2)(0 to 10 V FS Range) 19.8 20 20.2 19.8 20 20.2 kΩ PLCC (Figure 3) Pin 8 to Pin 7 9.9 10 10.1 9.9 10 10.1 kΩ Pin 7 to Pin 5 (0 V to 5 V FS Range) 9.9 10 10.1 9.9 10 10.1 kΩ Pin 8 to Pin 5 (0 V to 10 V FS Range) 19.8 20 20.2 19.8 20 20.2 kΩ Pin 9 to Pin 5 (0 V to 8 V FS Range) 15.8 16 16.2 15.8 16 16.2 kΩ Pin 10 to Pin 5 (Auxiliary Input) 19.8 20 20.2 19.8 20 20.2 kΩ Temperature Coefficient (All) ±50 ±100 ±50 ±100 ppm/°C INTEGRATOR OP AMP Input Bias Current Inverting Input (Pin 5) ±5 ±20 ±5 ±20 nA Noninverting Input (Pin 6) 20 50 20 50 nA Input Offset Current 20 70 20 70 nA Input Offset Current Drift 1 3 1 2 nA/°C Input Offset Voltage ±1 ±3 ±1 ±2 mV Input Offset Voltage Drift ±10 ±25 ±10 ±15 µV/°C Open-Loop Gain 86 86 dB Common-Mode Input Range –VS + 5 +VS – 5 –VS + 5 +VS – 5 V CMRR 80 80 dB Bandwidth 14 95 14 95 MHz Output Voltage Range −1 (+VS − 4) −1 (+VS − 4) V (Referred to Pin 6, R1 > = 5 kΩ)
Rev. C | Page 4 of 28 AD652JP/AQ/SQ AD652KP/BQ Parameter Min Typ Max Min Typ Max Unit COMPARATOR Input Bias Current 0.5 5 0.5 5 µA Common-Mode Voltage −VS + 4 + VS − 4 −VS + 4 +VS − 4 V CLOCK INPUT Maximum Frequency 4 5 4 5 MHz Threshold Voltage (Referred to Pin 12) 1.2 1.2 V TMIN to TMAX 0.8 2.0 0.8 2.0 V Input Current (−VS < VCLK < +VS) 5 20 5 20 µA Voltage Range −VS +VS −VS +VS V Rise Time 2 2 µs OUTPUT STAGE VOL (IOUT = 10 mA) 0.4 0.4 V IOL VOL < 0.8 V 15 15 mA VOL < 0.4 V, TMIN to TMAX 8 8 mA IOH (Off Leakage) 0.01 10 0.01 10 µA Delay Time, Positive Clock Edge to Output Pulse 150 200 250 150 200 250 ns Fall Time (Load = 500 pF and ISINK = 5 mA) 100 100 ns Output Capacitance 5 5 pF OUTPUT ONE-SHOT Pulse Width, tOS COS = 300 pF 1 1.5 2 1 1.5 2 µs COS = 1000 pF 4 5 6 4 5 6 µs REFERENCE OUTPUT Drift 100 50 ppm/°C Output Current Source TMIN to TMAX 10 10 mA Sink 100 500 100 500 µA Power Supply Rejection Supply Range = ±12.5 V to ±17.5 V 0.015 0.015 %/V Output Impedance (Sourcing Current) 0.3 2 0.3 2 Ω POWER SUPPLY Rated Voltage ±15 ±15 V Operating Range Dual Supply ±6 ±15 ±18 ±6 ±15 ±18 V Single Supply (−VS = 0) +12 +36 +12 +36 V Quiescent Current ±11 ±15 ±11 ±15 mA Digital Common −VS +VS − 4 –VS +VS − 4 V Analog Common −VS +VS −VS +VS V TEMPERATURE RANGE Specified Performance JP , KP Grade 0 +70 0 +70 °C AQ, BQ Grade −40 +85 −40 +85 °C SQ Grade −55 +125 °C 1 Referred to internal VREF. In PLCC package, tested on 10 V input range only.
degradation or loss of functionality. endpoints of the transfer function. Table 3. Pin Configurations
2 TRIM +VS
3 TRIM NC
4 OP AMP OUT OP AMP OUT
6 OP AMP “+” OP AMP “+”
9 COS 8 VOLT INPUT
10 CLOCK INPUT OPTIONAL 10 V INPUT
11 FREQ OUT −VS
12 DIGITAL GND COS
13 ANALOG GND CLOCK INPUT
14 COMP “−“ FREQ OUT
15 COMP “+” DIGITAL GND
16 COMP REF ANALOG GND
17 COMP “−“
18 COMP “+”
20 COMP REF
balance of the input signal with an internal reference current. crystal oscillator may also be used if desired. two signals are performed simultaneously.
10 VOLT INPUT 7
Figure 2. CERDIP Pin Configuration Figure 3. A block diagram of the device configured as an SVFC, along with various system waveforms, is shown in Figure 4. Figure 3. PLCC Pin Configuration same time, the latch drives the AND gate to a low output state. of the AND gate is transferred to the output of the D FLOP. to be influenced by the length of time since the last reset.
adjustment until the exact proper scale factor was achieved. Thus, the gain adjustment should be done with a 9 V input. is reduced by increasing the clock frequency. Figure 16. Gain vs. Clock Input ical output impedance changes the reference voltage by 0.06%. Ground at Pin 12 (approximately 1.2 V at room temperature). When the clock input is low, 5 µA to 10 µA flows out of this pin. When the clock input is high, no current flows. be as high as 36 V above digital ground.
0.1 V) and the clock frequency is less than 500 kHz, an
polypropylene, or polystyrene capacitors should be used. is being driven must also be taken into consideration.
that an input pulse of either polarity may be applied to the F/V. integrator summing junction and ramps up the voltage at Pin 4. capacitor; the −3 dB frequency is simply the RC time constant. response is needed, a small capacitor is used (1 nF minimum). extra resistor only increases the total gain error to 0.75% max. shown never calls for a negative voltage at the output. put voltage may be driven to within 6 V of the positive supply. Figure 22. Frequency-to-Voltage Converter
Rev. C | Page 16 of 28 DECOUPLING AND GROUNDING It is good engineering practice to use bypass capacitors on the supply-voltage pins, and to insert small valued resistors (10 Ω to 100 Ω) in the supply lines to provide a measure of decoupling between the various circuits in a system. Ceramic capacitors of 0.1 µF to 1.0 µF should be applied between the supply voltage pins and analog signal ground for proper bypassing on the AD652. Additionally, a larger board-level decoupling capacitor of 1 µF to 10 µF should be located relatively close to the AD652 on each power supply line. Such precautions are imperative in high resolution data acquisition applications where one expects to exploit the full linearity and dynamic range of the AD652. Separate digital and analog grounds are provided on the AD652. Only the emitter of the open-collector frequency output transistor and the clock input threshold are returned to the digital ground. Only the 5 V reference is connected to analog ground. The purpose of the two separate grounds is to allow isolation between the high precision analog signals and the digital section of the circuitry. Much noise can be tolerated on the digital ground without affecting the accuracy of the VFC. Such ground noise is inevitable when switching the large currents associated with the frequency output signal. At high full-scale frequencies, it is necessary to use a pull-up resistor of about 500 Ω in order to get the rise time fast enough to provide well-defined output pulses. This means that from a
5 V logic supply, for example, the open collector output draws
10 mA. This much current being switched causes ringing on long ground runs due to the self-inductance of the wires. For instance, 20-gauge wire has an inductance of about 20 nH per inch; a current of 10 mA being switched in 50 ns at the end of 12 inches of 20-gauge wire produces a voltage spike of 50 mV . The separate digital ground of the AD652 easily handles these types of switching transients. A problem remains from interference caused by radiation of electromagnetic energy from these fast transients. Typically, a voltage spike is produced by inductive switching transients; these spikes can capacitively couple into other sections of the circuit. Another problem is ringing of ground lines and power supply lines due to the distributed capacitance and inductance of the wires. Such ringing can also couple interference into sensitive analog circuits. The best solution to these problems is proper bypassing of the logic supply at the AD652 package. A 1 µF to 10 µF tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to the digital ground, Pin 12. The pull-up resistor should be connected directly to the frequency output, Pin 11. The lead lengths on the bypass capacitor and the pull-up resistor should be as short as possible. The capacitor supplies (or absorbs) the current transients, and large ac signals flow in a physically small loop through the capacitor, pull-up resistor, and frequency output transistor. It is important that the loop be physically small for two reasons: first, there is less inductance if the wires are short, and second, the loop does not radiate RFI efficiently. The digital ground (Pin 12) should be separately connected to the power supply ground. Note that the leads to the digital power supply are only carrying dc current. There may be a dc ground drop due to the difference in currents returned on the analog and digital grounds. This does not cause a problem; these features greatly ease power distribution and ground manage-ment in large systems. The proper technique for grounding requires separate digital and analog ground returns to the power supply. Also, the signal ground must be referred directly to the analog ground (Pin 6) at the package. More information on proper grounding and reduction of interference can be found in Noise Reduction Techniques in Electronic Systems, by H.W . Ort, (John Wiley, 1976).
Figure 23. Frequency Output Multiplier output frequency from 0 kHz–500 kHz to 0 MHz–1 MHz. which is proportional to the product of V1 and V2.
Figure 26. SVFC Multiplexer
500 FEET
Figure 27. RS-422 Standard Data Transmission
end of the one-shot period. See Figure 29. Figure 28. Multiplexer Waveforms Figure 29. Demultiplexer Waveforms
4 PHASE CLOCK
Figure 30. SVFC Demultiplexers
Figure 31. Demultiplexer Frequency-to-Voltage Conversion
24 TURNS
Figure 32. Isolated Synchronous VFC edge of the clock signal and shifted out on the next rising edge. available at the frequency output pin of each FVC.
transformer, and is regulated to 15 V . drive on each half cycle, and thus prevent saturation of the core. current drawn from the 5 V supply. Where N is the total number of codes for a given resolution. Figure 33. Block Diagram of SVFC A-to-D Converter type flip flops or another 4020B with the counter.
60 Hz, or 400 Hz, normal mode rejection (NMR) of those line
simplifying the scaling for the part’s calibrated 10 V input range.
- RF SHOULD BE BETWEEN 10kΩ AND 20kΩ.
- RPU NEEDED IF RBRIDGE 600Ω
- S1 IN POSITION 1 FOR UNIPOLAR SIGNALS
AND POSITION 2 FOR BIPOLAR SIGNALS. Figure 38. Bridge Transducer Interface
Rev. C | Page 26 of 28 ORDERING GUIDE Model Gain Drift, 100 kHz 1 MHz Linearity (%) Specified Temperature Range Package Options 1 AD652JP 50 ppm/°C max 0.02 max 0°C to +70°C PLCC (P-20A) AD652JP-REEL 50 ppm/°C max 0.02 max 0°C to +70°C PLCC (P-20A) AD652JP-REEL7 50 ppm/°C max 0.02 max 0°C to +70°C PLCC (P-20A) AD652KP 25 ppm/°C max 0.005 max 0°C to +70°C PLCC (P-20A) AD652KP-REEL 25 ppm/°C max 0.005 max 0°C to +70°C PLCC (P-20A) AD652AQ2 50 ppm/°C max 0.02 max −40°C to +85°C CERDIP (Q-16) AD652BQ2 25 ppm/°C max 0.005 max −40°C to +85°C CERDIP (Q-16) AD652SE/883B2 50 ppm/°C max 0.02 max −55°C to +125°C LCC (E-20A) AD652SQ2 50 ppm/°C max 0.02 max −55°C to +125°C CERDIP (Q-16) AD652SQ/883B2 50 ppm/°C max 0.02 max −55°C to +125°C CERDIP (Q-16) 1 P = Plastic Leaded Chip Carrier; Q = CERDIP , E = Leadless Chip Carrier. 2 For details on grade and package offerings screened in accordance with MILSTD-883, refer to the Analog Devices Military Products Databook or current AD652/883 data sheet.
Rev. C | Page 27 of 28 NOTES
Rev. C | Page 28 of 28 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . C00798–0–5/04(C)