AD651 AD | Alldatasheet
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Technical content
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FEATURES
Full-Scale Frequency (Up to 2MHz) Set by External System Clock No Critical External Components Required Extremely Low Linearity Error (0.005% max at 100kHz FS, 0.02% max at 2MHz FS) 40, Low Drift (25ppm/°C max) eases ag Dual or Single Supply Operation - ‘Sa Voltage or Current Input i Sy Low Cost ($7.95, AQ, 100's) re. % a q 1 2 AP ee PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS ‘The AD651 Synchronous Voltage-to-Frequency Converter (SVFC) 1. The use of an external clock to set the full-scale frequency uses a variation of the popular charge-balancing technique to allows the AD651 to achieve linearity and stability far superior : perform the conversion function. The AD651 uses an external to any other monolithic VFC. By using the same clock to clock to define the full-scale output frequency, rather than drive the AD651 and (through a suitable divider) also set the : relying on the stability of an external one-shot capacitor. The counting period, conversion accuracy is maintained indepen- result is a more stable, more linear transfer function, with sig- dent of variations in clock frequency. nificant application benefits in both single- and multi-channel 2. The AD651 Synchronous VFC requires only a single external systems, component (a noncritical integrator capacitor) for operation. : The AD651 is a powerful building block for precision analog-to- 3. “The clock im ; . ‘oi . " " 3 put of the AD651 is TTL and CMOS compatible digital conversion, offering typical nonlinearity of 0.002% (0.005% and can also be driven by sources referred to the negative maximum) at a 100kHz output frequency. The inherent power supply. The flexible open-collector output stage provides , monotonicity of the transfer function and wide range of clock sufficient current sinking capability for TTL and CMOS frequencies allows the conversion time and resolution to be logic, as well as optical couplers and pulse transformers, A optimized for specific applications. capacitor-programmable one-shot is provided for selection of Gain drift is minimized using a precision low-drift buried zener optimum output pulse width for power reduction. reference and low-TC on-chip thin-film scaling resistors. Fur- 4. ‘The AD6S1 can also be confi 5 ow oF . gured for use as a synchronous thermore, the initial gain error is reduced to less than 0.5% by FIV converter for isolated analog signal transmission, the use of laser-wafer-trimming. The analog and digital sections of the AD651 have been designed to allow operation from a single-ended power source, simplifying its use with isolated power supplies. The AD651 is available in three performance grades. The 16-pin cerdip-packaged AQ and BQ grades are specified for operation a over the — 25°C to +85°C industrial temperature range, and the )27 VES Ow" AD651SQ is available for operation over the full — 55°C to 002338 + 125°C extended temperature range. 1416 Baer ANT Information furnished by Analog Devices is believed to be accurate Qne Technology Way: P.O. Box 9106; Norwood, MA 02062-9106 and reliable. However, no responsibility is assumed by Analog Devices Tel: 617/329-4700 TWX: 710/394-6577 for its use: nor for any infringements of patents or other rights of third d . Parties which may result from its use. No license is granted by implica- WestCoast Mid-West Texas tion or otherwise under any patent or patent rights of Analog Devices. 714/641-9391 312/350-9399 214/231-5094 ~|- - rod
Min Typ = Max Min Typ) = Max Units VOLTAGE-TO-FREQUENCY MODE 1 Gain Error four = 100kHz £05 41 £0.25 +05 % four = 500kHz £05 41 40,25 £05 % four= 2MHz £05 +15 +025 +£0.75 % Gain Drift! four = 100kHz £25 +50 +15 +25 | ppm/°C four = 500kHz +250 £50, +15) £25 ppm/°C four=2MHz 1 +25 +75 +15 £50 ppm*C Power Supply Rejection 1 0.001 © 0.01 0.001 0.01 WV Linearity Ercor | four = 100kHz i 0.002 +0.02 +0,002 +0.005 % four = 500kHz i +0002 +0.02 £0,002 +0.005 % Offset? #1 £45 +1 £25 mV (Transfer Function, RTI) Offset Drift +10 +50 +10 #30 pyre FREQUENCY-TO-VOLTAGEMODE Gain Error f= 100KHz FS £05 0 +1 £0.25 £05 % Linearity Error fia= 100kKHz FS +0.002 +0.02 0.002 £0.01 % ‘Temperature Coefficient +20 +50 +20 +50 ppm*C INTEGRATOR OP AMP i Input Bias Current i | Inverting Input (Pin 5) +8 +20 +8 +20 nA Noninverting Input (Pin 6) 40 100 40 100 nA Input Offset Current 40 120 40 120 nA Input Offset Voltage +1 +4 +1 #2 mV ‘Open Loop Gain 86 86 | dB ‘Common-Mode Input Range -10 10 -10 10 iv Output Voltage Range -1 (+Vs—-4) -1 (FV5-4)) V (Referred to Pin 6, R,> =5k) COMPARATOR | Input Bias Current 0.5 5 0.5 5 pA Common Mode Voltage -V5+4 +Vs-4 0 -Vs+4 +Vs-4 VN CLOCK INPUT | ‘Maximum Frequency 4 5 4 5 | MHz ‘Threshold Voltage 1.4 14 iv Trine Tmax 08 2.0 0.8 20 iv (Referred to Pin 12) Input Current | (=Vs<Veix< + Vs) 5 20 5 20 nA Voltage Range -Vs +Vs5 -Vs +Vs | V OUTPUT STAGE | Vou Tour = 8mA) 04 04 iv Jou Vor<0.8V 15 15 mA Vor.<0.4V, Tanin-Trnax 6.4 64 | mA Ton (Off Leakage) 0.01 10 0.01 10 pA Delay Time, Positive Clock Edge to 150 200 250 150 200 250 ns Output Pulse Fall Time (Load = S00pF and Isiyx = 5mA) 100 100 ns Output Capacitance 5 5 pF OUTPUT ONE-SHOT Pulse Width Cos = 300pF 1 15 2 1 15 2 bs Cos = 1000pF 4 5 6 4 5 6 [ps -2-
AD6SIAQ/SQ | AD651BQ Min Typ = Max | Min’ Typ) Max Units REFERENCE OUTPUT a = _Drift _ : 50 30 + ppmeG POWER SUPPLY i ~~ Rated Voltage +15 #15 v Operating Range ‘Dual Supplies +6 +15 £18 +6 15 #18 | Vv Single Supply (— V,~0) +R +36 +12 +3600) V Quiescent Current +9 +15 +9 +1500) mA Digital Common -Vs +Vs-4 Ve +Vs-4-V Analog Common i =Vg +Vs | = Vg +Vs OV TEMPERATURE RANGE. an ee Specified Performance “AQ”, “BQ” Grade 328 +85 -25 +85 °C “SQ” Grade =58 +15 | uc NOTES ‘Gain Driftis theaverage drift from Tig Trex, andis measured at +25°C, Twin ad Trax Offset is guaranteed adjustable to zero using a 20K potentiometer on pins 2and 3 with the wiper ; connected to + Vs through a 250k resistor. ‘Specifications in boldface are 100% tested at final test and are used to measure outgoing quality levels. ‘Specifications subject 10 change withaut notice. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Maximum Output Current (Open Collector Output) . . 5O0mA Part ppm°C 1MHz Temperature : AD651BQ 25max 0.005max ~25t0 +85 Cerdip $15.60 AD651SQ SOmax 0.02max -55t0 +125 Cerdip $13.65 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) “Q” PACKAGE 16-Pin CERDIP 1.025 (0.935) 8 ~— a roewitiens 9.288: 9.002 tearcoon) 780: 0.008, . 48 0315 {asso =. fi reset “te . rir > ay Low ‘ ge | L a_i 200 ner LeA0 No. oenTiFio.8v DoT oRNOTEH DEFINITIONS OF SPECIFICATIONS ; GAIN ERROR - The gain of a voltage-to-frequency converter LINEARITY ERROR - The “linearity error” of a V-F is the . is that scale factor setting that provides the nominal conversion deviation of the actual transfer function from a straight line : relationship, e.g. 1MHz full scale. The “gain error” is the dif- passing through the endpoints of the transfer function. ference in slope between the actual and ideal transfer functions for the V-F converter. + : Tt E
signal starts to drift downward. As the integrator sawtooth drifts of the sawtooth phase modulation is 2. the cycle is lost, the Integrate Phase lasts for two periods of the SVC. ig imi ! . Because of this, it is very difficult to observe the waveform on . . an oscilloscope. During all of this time, the signal at the output of 2MHz. Thus, the resolution is 13 bits. “ i" full-scale output frequency is equal to one-half the clock frequency. ee will then simply settle into a “divide-by-two” of the clock state.
1 Lock IN
Figure 4. Integrator Output for ln Slightly Greater dual supply, positive input mode of operation. The + Vs range ata certain rate. However, since the SVFC is running at exactly _reference will be set by the 250A current and this resistor. The output frequency is then a steady carrier which has been injection. Figure 6. Standard V/F Connection for Positive Input Voltage Figure 5. Phase Modulation with Dual Supply
Figure 13. Digital GND at —Vs ct 3 + : In Figure 14, the comparator reference is used as a derived . to place a pull up resistor between pin 16 and + Vs to provide The AD651 SVFC also works as a frequency-to-voltage converter. this results in a full-scale output voltage of 10V at pin 4.
4 The frequency response of the circuit is determined by the
B) i | FN ts | *_ resistor as shown. Since the 50 resistor is 0.25% of the full . Qs Aa oh | ‘AE, SI Jase scale, and the specified gain error with the 20K0 resistor is :. SouRCE py Qiu WG mcs Con to +0.75% max. amp, rather it has been optimized for simplicity and high speed. Figure 14. Single Supply Positive Voltage Input .
we mean +5v Separate digital and analog grounds are provided on the AD651. Von gy mt oe py) omen V 3 the digital ground without affecting the accuracy of the VFC. v Vital PoP ci0cx associated with the frequency output signal. supply, for example, the open collector output will draw 10mA. Figure 16. Frequency-to-Voltage Converter circuit. Another problem is ringing of ground lines and power = it is internally protected by current limiting. The output of the __the loop will not radiate RFI efficiently. 0.1,F to 1.04F should be applied between the supply-voltage reduction of interference can be found in reference 1. exploit the full linearity and dynamic range of the AD651. (ohn Wiley, 1976).
Applications
FREQUENCY OUTPUT MULTIPLIER This can be shown in equation form, where fc is the AD654 The AD651 can serve as a frequency output multiplier when output frequency and four is the AD651 output frequency: used in conjunction with a standard voltage-to-frequency con- MHz verter. Figure 17 shows the low cost AD654 VFC being used as fe = Vinoy the clock input to the AD651. Also shown is a second AD651 in the FV mode. The AD654 is set up to produce an output frequency en of 0-500kHz for an input voltage (V,) range of 0-10V. The use four = V2 (<2) of R4, Cl, and the KOR gate doubles this output frequency u from 0-500kHz to 0-IMHz. fan = WW IMHe av oT 12 \\210V) (10V), k four = V, + V2 + SkHz/V? O—_ Ba Apes4 0, The scope photo in Figure 18 shows V, and V2 (top two traces) , @ ue > and the output of the F-V (bottom trace). eee a Eee E[ sSipr | [rasee —_ @) a = Ot. | 41a aa ? ; ANANAAAANANANAAAS t i ANNAN 2otF | i f vw — ree ei {= NN AR a AVE atl aN Ft eh <P WAN AVE Wy oF aves: Us} 2v tov 2mS rH on ce oust 2 el a Poy] } (25 de me Figure 18. Multiplier Waveforms a ee LE ow yo V heal mf tae SINGLE-LINE MULTIPLEXED DATA TRANSMISSION 4... It is often necessary to measure several different signals and a ae} PI Lk, relay the information to some remote location using a minimum amount of cable. Multiple AD651 SVFC devices may be used t at | with a multiphase clock to combine these measurements for ~15v serial transmission and demultiplexing. Figure 19 shows a block oy oy diagram of a single-line multiplexed data transmission system [ = with high noise immunity. Figures 20, 21 and 22 show the io o— x ps) 2 SVFC multiplexer, a representative means of data transmission, ey v (=) 1 and an SVFC demultiplexer respectively. ese | ty wee Multiplexer ; ; YAN Beaune PT Figure 20 shows the SVFC multiplexer. The clock inputs for rH ; re =f the several SVFC channels are generated by a TIM9904A four ra EN Fy phase clock driver, and the frequency outputs are combined by V fel i = atte, strapping all the frequency output pins together (a “wire or” ¥ o I iweuT connection). The one-shot in the AD651 sets the pulse width of igo ft, | [?] the frequency output pulses to be slightly shorter than one bv quarter of the clock period. Synchronization is achieved by applying one of the four available phases to a fixed TTL one-shot C121) and combining the output with an external transistor. ‘The width of this sync pulse is shorter than the width of the Figure 17. Frequency Output Multiplier frequency output pulses to facilitate decoding the signal. The is one-half the clock frequency, the IMHz FS clock frequency edge of the clock and the output pulse.
125kHz, with the clock signal being relayed to the SVFC through _ Sinusoidal and the clock frequency will be relayed to the SVFC. is generated from an AD654 VFC and is frequency divided by current drawn from the 5 volt supply. Figure 26. Isolated Synchronous VFC