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Frequency-to-Voltage Converter Data Sheet AD650 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Reliable monolithic construction Very low nonlinearity 0.002% typ at 10 kHz 0.005% typ at 100 kHz 0.07% typ at 1 MHz Input offset trimmable to zero CMOS- or TTL-compatible Unipolar, bipolar, or differential V/F V/F or F/V conversion Available in surface mount MIL-STD-883 compliant versions available FUNCTIONAL BLOCK DIAGRAM 00797-001 OP AMP COMP IN FREQ OUT OUTONE SHOT

8 FOUTPUT

9 COMPARATOR

10 DIGITAL

11 ANALOG

13 OFFSET

5–VS BIPOLAR OFFSET CURRENT 3–IN 2+IN 1VOUT 14 OFFSET NULLINPUT OFFSET TRIM –0.6V AD650 –VS –VS 1mA NC = NO CONNECT Figure 1. PRODUCT DESCRIPTION The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. The inherent monotonicity of the V/F transfer function makes the AD650 useful as a high-resolution analog-to-digital converter. A flexible input configuration allows a wide variety of input voltage and current formats to be used, and an open-collector output with separate digital ground allows simple interfacing to either standard logic families or opto-couplers. The linearity error of the AD650 is typically 20 ppm (0.002% of full scale) and 50 ppm (0.005%) maximum at 10 kHz full scale. This corresponds to approximately 14-bit linearity in an analog- to-digital converter circuit. Higher full-scale frequencies or longer count intervals can be used for higher resolution conversions. The AD650 has a useful dynamic range of six decades allowing extremely high resolution measurements. Even at 1 MHz full scale, linearity is guaranteed less than 1000 ppm (0.1%) on the AD650KN, BD, and SD grades. In addition to analog-to-digital conversion, the AD650 can be used in isolated analog signal transmission applications, phased-locked loop circuits, and precision stepper motor speed controllers. In the F/V mode, the AD650 can be used in precision tachometer and FM demodulator circuits. The input signal range and full-scale output frequency are user- programmable with two external capacitors and one resistor. Input offset voltage can be trimmed to zero with an external potentiometer. The AD650JN and AD650KN are offered in plastic 14-lead DIP packages. The AD650JP is available in a 20-lead plastic leaded chip carrier (PLCC). Both plastic packaged versions of the AD650 are specified for the commercial temperature range (0°C to 70°C). For industrial temperature range (−25°C to +85°C) applications, the AD650AD and AD650BD are offered in ceramic packages. The AD650SD is specified for the full −55°C to +125°C extended temperature range. PRODUCT HIGHLIGHTS 1. Can operate at full-scale output frequencies up to 1 MHz (in addition to having very high linearity). 2. Can be configured to accommodate bipolar, unipolar, or differential input voltages, or unipolar input currents. 3. TTL or CMOS compatibility is achieved by using an open collector frequency output. The pull-up resistor can be connected to voltages up to 30 V. 4. The same components used for V/F conversion can also be used for F/V conversion by adding a simple logic biasing network and reconfiguring the AD650. 5. Separate analog and digital grounds prevent ground loops in real-world applications. 6. Available in versions compliant with MIL-STD-883.

AD650* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes

• AN-276: Analog to Digital Conversion by Using V/F Converters
• AN-279: Using the AD650 Voltage-to-Frequency Converter As a Frequency-to-Voltage Converter
• AN-361: Ask the Applications Engineer (V/F Converters) Data Sheet
• AD650: Voltage-to-Frequency and Frequency-to-Voltage Converter Data Sheet TOOLS AND SIMULATIONS
• AD650 Component Selection Calculator REFERENCE MATERIALS Technical Articles
• DDS IC Plus Frequency-To-Voltage Converter Make Low- Cost DAC DESIGN RESOURCES
• AD650 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD650 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. E | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

3/13—Rev. D to Rev. E 3/06—Rev. C to Rev. D

Rev. E | Page 3 of 20 SPECIFICATIONS T = 25°C, VS = ±15 V , unless otherwise noted. Table 1. AD650J/AD650A AD650K/AD650B AD650S Model Min Typ Max Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE Full-Scale Frequency Range 1 1 1 MHz Nonlinearity1 Full-Scale Calibration Error2 100 kHz ± 5 ± 5 ± 5 %

1 MHz ± 10 ± 10 ± 10 %

% of FSR/V vs. Temperature A, B, and S Grades at 10 kHz ±75 ±75 ±75 ppm/°C at 100 kHz ±150 ±150 ±200 ppm/°C J and K Grades at 10 kHz ±75 ±75 ppm/°C at 100 kHz ±150 ±150 ppm/°C BIPOLAR OFFSET CURRENT Activated by 1.24 kΩ Between DYNAMIC RESPONSE Maximum Settling Time for Full-Scale Step Input 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs Overload Recovery Time Step Input 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs ANALOG INPUT AMPLIFIER (V/F CONVERSION) Current Input Range (Figure 4) 0 +0.6 0 +0.6 0 +0.6 mA Voltage Input Range (Figure 12) −10 0 −10 0 −10 0 V Differential Impedance 2 MΩ||10 pF 2 MΩ||10 pF 2 MΩ||10 pF Common-Mode Impedance 1000 MΩ||10 pF 1000 MΩ||10 pF 1000 MΩ||10 pF Input Bias Current Noninverting Input 40 100 40 100 40 100 nA Inverting Input ±8 ±20 ±8 ±20 ±8 ±20 nA Input Offset Voltage (Trimmable to Zero) ±4 ±4 ±4 mV vs. Temperature (TMIN to TMAX) ±30 ±30 ±30 µV/°C Safe Input Voltage ±VS ±VS ±VS V COMPARATOR (F/V CONVERSION) Logic 0 Level −VS −1 −VS −1 −VS −1 V Logic 1 Level 0 +VS 0 +VS 0 +VS V Input Impedance 250 250 250 kΩ OPEN COLLECTOR OUTPUT (V/F CONVERSION) Output Voltage in Logic 0 ISINK ≤ 8 mA, TMIN to TMAX 0.4 0.4 0.4 V Output Leakage Current in Logic 1 100 100 100 nA Voltage Range5 0 36 0 36 0 36 V

Rev. E | Page 4 of 20 AD650J/AD650A AD650K/AD650B AD650S Model Min Typ Max Min Typ Max Min Typ Max Units AMPLIFIER OUTPUT (F/V CONVERSION) Voltage Range (1500 Ω Min Load Resistance) 0 10 0 10 0 10 V Source Current (750 Ω Max Load Resistance) 10 10 10 mA Capacitive Load (Without Oscillation) 100 100 100 pF POWER SUPPLY Voltage, Rated Performance ±9 ±18 ±9 ±18 ±9 ±18 V Quiescent Current 8 8 8 mA TEMPERATURE RANGE Rated Performance N Package 0 +70 0 +70 °C D Package −25 +85 −25 +85 −55 +125 °C 1 Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale. 2 Full-scale calibration error adjustable to zero. 3 Measured at full-scale output frequency of 100 kHz. 4 Refer to F/V conversion section of the text. 5 Referred to digital ground. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Rev. E | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Parameter Rating Total Supply Voltage 36 V Storage Temperature Range −55°C to +150°C Differential Input Voltage ±10 V Maximum Input Voltage ±VS Open Collector Output Voltage Above Digital GND 36 V Current 50 mA Amplifier Short Circuit to Ground Indefinite Comparator Input Voltage ±VS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. E | Page 8 of 20 The positive input voltage develops a current (IIN = VIN/RIN) that charges the integrator capacitor CINT. As charge builds up on CINT, the output voltage of the integrator ramps downward towards ground. When the integrator output voltage (Pin 1) crosses the comparator threshold (–0.6 V) the comparator triggers the one shot, whose time period, tOS is determined by the one-shot capacitor COS. Specifically, the one-shot time period is sec100.3F/sec108.6 73 −×+××= OSOS Ct (1) The reset period is initiated as soon as the integrator output voltage crosses the comparator threshold, and the integrator ramps upward by an amount ( )IN INT OS OS IC t dt dVtV −=×=∆ mA1 (2) After the reset period has ended, the device starts another integration period, as shown in Figure 8, and starts ramping downward again. The amount of time required to reach the comparator threshold is given as ( )  −= =∆= 1mA1mA1 IN OS INT N IN INT OS It C I IC t dt dV VT (3) The output frequency is now given as FC RV A F t I Ttf OS ININ OS IN OS OUT 104.4 /Hz15.0 mA1 −×+ =×=+= (4) Note that CINT, the integration capacitor, has no effect on the transfer relation, but merely determines the amplitude of the sawtooth signal out of the integrator. One-Shot Timing A key part of the preceding analysis is the one-shot time period given in Equation 1. This time period can be broken down into approximately 300 ns of propagation delay and a second time segment dependent linearly on timing capacitor COS. When the one shot is triggered, a voltage switch that holds Pin 6 at analog ground is opened, allowing that voltage to change. An internal 0.5 mA current source connected to Pin 6 then draws its current out of COS, causing the voltage at Pin 6 to decrease linearly. At approximately –3.4 V , the one shot resets itself, thereby ending the timed period and starting the V/F conversion cycle over again. The total one-shot time period can be written mathematically as DELAYGATE DISCHARGE OS OS TI CVt +∆= (5) substituting actual values quoted in Equation 5, sec10300A105.0 V4.3 9 − ×+×− ×−= OS OS Ct (6) This simplifies into the timed period equation (see Equation 1). COMPONENT SELECTION Only four component values must be selected by the user. These are input resistance RIN, timing capacitor COS, logic resistor R2, and integration capacitor CINT. The first two determine the input voltage and full-scale frequency, while the last two are determined by other circuit considerations. Of the four components to be selected, R2 is the easiest to define. As a pull-up resistor, it should be chosen to limit the current through the output transistor to 8 mA if a TTL maximum V OL of 0.4 V is desired. For example, if a 5 V logic supply is used, R2 should be no smaller than 5 V/8 mA or 625 Ω. A larger value can be used if desired. R IN and COS are the only two parameters available to set the full- scale frequency to accommodate the given signal range. The swing variable that is affected by the choice of RIN and COS is nonlinearity. The selection guides of Figure 9 and Figure 10 show this quite graphically. In general, larger values of COS and lower full-scale input currents (higher values of RIN) provide better linearity. In Figure 10, the implications of four different choices of RIN are shown. Although the selection guide is set up for a unipolar configuration with a 0 V to 10 V input signal range, the results can be extended to other configurations and input signal ranges. For a full-scale frequency of 100 kHz (corresponding to 10 V input), among the available choices RIN = 20 kΩ and COS = 620 pF gives the lowest nonlinearity, 0.0038%. In addition, the highest frequency that gives the 20 ppm minimum nonlinearity is approximately 33 kHz (40.2 kΩ and 1000 pF). For input signal spans other than 10 V , the input resistance must be scaled proportionately. For example, if 100 kΩ is called out for a 0 V to 10 V span, 10 kΩ would be used with a 0 V to 1 V span, or 200 kΩ with a ±10 V bipolar connection. The last component to be selected is the integration capacitor CINT. In almost all cases, the best value for CINT can be calculated using the equation ( )minimumpF1000sec/10 4 MAX INT f FC = (7) When the proper value for CINT is used, the charge balance architecture of the AD650 provides continuous integration of the input signal, therefore, large amounts of noise and interference can be rejected. If the output frequency is measured by counting pulses during a constant gate period, the integration provides infinite normal-mode rejection for frequencies corresponding to the gate period and its harmonics. However, if the integrator stage becomes saturated by an excessively large noise pulse, then the continuous integration of the signal is interrupted, allowing the noise to appear at the output.

Rev. E | Page 12 of 20 DECOUPLING AND GROUNDING It is effective engineering practice to use bypass capacitors on the supply-voltage pins and to insert small-valued resistors (10 Ω to 100 Ω) in the supply lines to provide a measure of decoupling between the various circuits in a system. Ceramic capacitors of 0.1 μF to 1.0 μF should be applied between the supply-voltage pins and analog signal ground for proper bypassing on the AD650. In addition, a larger board level decoupling capacitor of 1 μF to 10 μF should be located relatively close to the AD650 on each power supply line. Such precautions are imperative in high resolution, data acquisition applications where users expect to exploit the full linearity and dynamic range of the AD650. Although some types of circuits can operate satisfactorily with power supply decoupling at only one location on each circuit board, such practice is strongly discouraged in high accuracy analog design. Separate digital and analog grounds are provided on the AD650. The emitter of the open collector frequency output transistor is the only node returned to the digital ground. All other signals are referred to analog ground. The purpose of the two separate grounds is to allow isolation between the high precision analog signals and the digital section of the circuitry. As much as several hundred millivolts of noise can be tolerated on the digital ground without affecting the accuracy of the VFC. Such ground noise is inevitable when switching the large currents associated with the frequency output signal. At 1 MHz full scale, it is necessary to use a pull-up resistor of about 500 Ω in order to get the rise time fast enough to provide well defined output pulses. This means that from a 5 V logic supply, for example, the open collector output draws 10 mA. This much current being switched causes ringing on long ground runs due to the self-inductance of the wires. For instance, 20 gauge wire has an inductance of about 20 nH per inch; a current of 10 mA being switched in 50 ns at the end of 12 inches of 20 gauge wire produces a voltage spike of 50 mV . The separate digital ground of the AD650 easily handles these types of switching transients. A problem remains from interference caused by radiation of electromagnetic energy from these fast transients. Typically, a voltage spike is produced by inductive switching transients; these spikes can capacitively couple into other sections of the circuit. Another problem is ringing of ground lines and power supply lines due to the distributed capacitance and inductance of the wires. Such ringing can also couple interference into sensitive analog circuits. The best solution to these problems is proper bypassing of the logic supply at the AD650 package. A 1 μF to 10 μF tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to the digital ground (Pin 10). The pull-up resistor should be connected directly to the frequency output (Pin 8). The lead lengths on the bypass capacitor and the pull-up resistor should be as short as possible. The capacitor supplies (or absorbs) the current transients, and large ac signals flows in a physically small loop through the capacitor, pull-up resistor, and frequency output transistor. It is important that the loop be physically small for two reasons: first, there is less self-inductance if the wires are short, and second, the loop does not radiate RFI efficiently. The digital ground (Pin 10) should be separately connected to the power supply ground. Note that the leads to the digital power supply are only carrying dc current and cannot radiate RFI. There can also be a dc ground drop due to the difference in currents returned on the analog and digital grounds. This does not cause any problem. In fact, the AD650 tolerates as much as

0.25 V dc potential difference between the analog and digital

grounds. These features greatly ease power distribution and ground management in large systems. Proper technique for grounding requires separate digital and analog ground returns to the power supply. Also, the signal ground must be referred directly to analog ground (Pin 11) at the package. All of the signal grounds should be tied directly to Pin 11, especially the one-shot capacitor. More information on proper grounding and reduction of interference can be found in “Noise Reduction Techniques in Electronic Systems, 2 nd edition” by Henry W . Ott, (John Wiley & Sons, Inc., 1988). TEMPERATURE COEFFICIENTS The drift specifications of the AD650 do not include temperature effects of any of the supporting resistors or capacitors. The drift of the input resistors R1 and R3 and the timing capacitor C OS directly affect the overall temperature stability. In the application of Figure 5, a 10 ppm/°C input resistor used with a 100 ppm/°C capacitor can result in a maximum overall circuit gain drift of: 150 ppm/°C (AD650A) + 100 ppm/°C (COS) + 10 ppm/°C (RIN) = 260 ppm/°C In bipolar configuration, the drift of the 1.24 kΩ resistor used to activate the internal bipolar offset current source directly affects the value of this current. This resistor should be matched to the resistor connected to the op amp noninverting input, Pin 2 (see Figure 11). That is, the temperature coefficients of these two resistors should be equal. If this is the case, then the effects of the temperature coefficients of the resistors cancel each other, and the drift of the offset voltage developed at the op amp noninverting input is solely determined by the AD650. Under these conditions, the TC of the bipolar offset voltage is typically −200 ppm/°C and is a maximum of −300 ppm/°C. The offset voltage always decreases in magnitude as temperature is increased.

sawtooth waveform at the output of the integrator. gain TC tends to be more positive and is typically 15 ±50 ppm/°C. This information is presented in a graphical form in Figure 15. the 1 MHz full-scale frequency. Figure 15. Gain TC vs. Temperature change the gain TC from approximately 0 ppm to 310 ppm/°C. and for F/V conversion as well. shaped and the maximum value can be either positive or negative. above this point. This is shown graphically in Figure 17.

Rev. E | Page 16 of 20

APPLICATIONS

DIFFERENTIAL VOLTAGE-TO-FREQUENCY CONVERSION The circuit in Figure 20 accepts a true floating differential input signal. The common-mode input, VCM, can be in the range +15 V to −5 V with respect to analog ground. The signal input, V IN, can be ±5 V with respect to the common-mode input. Both inputs are low impedance; the source that drives the common- mode input must supply the 0.5 mA drawn by the bipolar offset current source, and the source that drives the signal input must supply the integration current. If less common-mode voltage range is required, then a lower voltage Zener can be used. For example, if a 5 V Zener is used, the V CM input can be in the range +10 V to −5 V . If the Zener is not used at all, the common-mode range is ±5 V with respect to analog ground. If no Zener is used, the 10 kΩ pulldown resistor is not needed and the integrator output (Pin 1) is connected directly to the comparator input (Pin 9). AUTOZERO CIRCUIT In order to exploit the full dynamic range of the AD650 VFC, very small input voltages need to be converted. For example, a six decade dynamic range based on a full scale of 10 V requires accurate measurement of signals down to 10 μV . In these situations, a well-controlled input offset voltage is imperative. A constant offset voltage does not affect dynamic range but simply shifts all of the frequency readings by a few hertz. However, if the offset should change, it is not possible to distinguish between a small change in a small input voltage and a drift of the offset voltage. Therefore, the usable dynamic range is less. The circuit shown in Figure 21 provides automatic adjustment of the op amp offset voltage. The circuit uses an AD582 sample- and-hold amplifier to control the offset, and the input voltage to the VFC is switched between ground and the signal to be measured via an AD7512DI analog switch. The offset of the AD650 is adjusted by injecting a current into—or drawing a current out of—Pin 13. Note that only one of the offset null pins is used. During the VFC norm mode, the SHA is in the hold mode and the hold capacitor is very large, 0.1 μF, which holds the AD650 offset constant for a long period of time. When the circuit is in the autozero mode, the SHA is in sample mode and behaves like an op amp. The circuit is a variation of the classical two amplifier servo loop, where the output of the device under test (DUT)—here the DUT is the AD650 op amp—is forced to ground by the feedback action of the control amplifier—the SHA. Because the input of the VFC circuit is connected to ground during the autozero mode, the input current that can flow is determined by the offset voltage of the AD650 op amp. Because the output of the integrator stage is forced to ground, it is known that the voltage is not changing (it is equal to ground potential). Therefore, if the output of the integrator is constant, its input current must be zero, so the offset voltage has been forced to be zero. Note that the output of the DUT could have been forced to any convenient voltage other than ground. All that is required is that the output voltage be known to be constant. Note also that the effect of the bias current at the inverting input of the AD650 op amp is also mulled in this circuit. The 1000 pF capacitor shunting the 200 kΩ resistor is compensation for the two amplifier servo loop. Two integrators in a loop require a single zero for compensation. The 3.6 kΩ resistor from Pin 1 of the AD650 to the negative supply is not part of the autozero circuit, but rather, it is required for VFC operation at 1 MHz. 00797-021 OP AMP COMP IN FREQ OUT OUTONE SHOT 1 14 INPUT OFFSET TRIM 10V ZENER 1N5240 NOTES 1. VCM IS THE COMMON MODE INPUT +15V TO –5V WITH RESPECT TO ANALOG GROUND. 2. VIN IS THE SIGNAL INPUT ±5V WITH RESPECT TO VCM. –0.6V AD650 –VS VIN VCM INPUT –VS 1mA 20kΩ 250kΩ 0.1µF 1µF +15V GND GND FREQUENCY OUTPUT 0kHz TO 100kHz –15V +5V 0.1µF– 1kΩ 10kΩ COS 330pF CI 1000pF 1.24kΩ 40kΩ 10kΩ Figure 20. Differential Input

Rev. E | Page 18 of 20 In signal recovery applications of a PLL, the desired output signal is the voltage applied to the oscillator. In these situations, a linear relationship between the input frequency and the output voltage is desired; the AD650 makes a superb oscillator for FM demodulation. The wide dynamic range and outstanding linearity of the AD650 VFC allow simple embodiment of high performance analog signal isolation or telemetry systems. The circuit shown in Figure 22 uses a digital phase detector that also provides proper feedback in the event of unequal frequencies. Such phase-frequency detectors (PFDs) are available in integrated form. For a full discussion of phase- lock loop circuits see “Phase Lock Techniques,” 3rd Edition, by F .M. Gardner, (John Wiley & Sons, Inc., 1979). An analysis of this circuit must begin at the 7474 Dual D flip flop. When the input carrier matches the output carrier in both phase and frequency, the Q outputs of the flip flops rise at exactly the same time. With two zeros, and then two ones on the inputs of the exclusive or (XOR) gate, the output remains low keeping the DMOS FET switched off. Also, the NAND gate goes low resetting the flip-flops to zero. Throughout this entire cycle, the DMOS integrator gate remains off, allowing the voltage at the integrator output to remain unchanged from the previous cycle. However, if the input carrier leads the output carrier by a few degrees, the XOR gate is turned on for the short time span that the two signals are mismatched. Because Q2 is low during the mismatch time, a negative current is fed into the integrator, causing its output voltage to rise. This in turn increases the frequency of the AD650 slightly, driving the system towards synchronization. In a similar manner, if the input carrier lags the output carrier, the integrator is forced down slightly to synchronize the two signals. Using a mathematical approach, the ±25 μA pulses from the phase detector are incorporated into the phase-detector gain (K d). radian/amperes1042 μA25 6−×=π=dK (9) Also, the V/F converter is configured to produce 1 MHz in response to a 10 V input so its gain (Ko) is secvolt radians103.6V10 Hz1012 5 ××=××π=OK (10) The dynamics of the phase relationship between the input and output signals can be characterized as a second order system with natural frequency (ωn). C KK do n =ω (11) and damping factor (ζ) is do KCKR =ζ (12) For the values shown in Figure 22, these relations simplify to a natural frequency of 35 kHz with a damping factor of 0.8. For a simple approach to determine component values for other PLL frequencies and VFC full-scale voltage, follow these steps: 1. Determine Ko (in units of radians per volt second) from the maximum input carrier frequency fMAX (in hertz) and the maximum output voltage VMAX. MAX MAX o V FK ×π= 2 (13) 2. Calculate a value for C based upon the desired loop bandwidth fn. Note that this is the desired frequency range of the output signal. The loop bandwidth (fn) is not the maximum carrier frequency (fMAX). The signal can be very narrow even though it is transmitted over a 1 MHz carrier. secRad101 7 2 × ×××= − FV f KC n o (14) where: C units = farads fn units = hertz Ko units = rad/volt × sec 3. Calculate R to yield a damping factor of approximately 0.8 using this equation: VK fR o where: R units = ohms fn units = hertz Ko units = rad/volt × sec If in actual operation the PLL overshoots or hunts excessively before reaching a final value, the damping factor can be raised by increasing the value of R. Conversely, if the PLL is overdamped, a smaller value of R should be used.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 20-Lead Plastic Leaded Chip Carrier [PLCC]

1 MHz

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