AD650 AD | Alldatasheet

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REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Voltage-to-Frequency and Frequency-to-Voltage Converter AD650

FEATURES

Reliable Monolithic Construction Very Low Nonlinearity 0.002% typ at 10 kHz 0.005% typ at 100 kHz 0.07% typ at 1 MHz Input Offset Trimmable to Zero CMOS or TTL Compatible Unipolar, Bipolar, or Differential V/F V/F or F/V Conversion Available in Surface Mount MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. The inherent monotonicity of the V/F transfer function makes the AD650 useful as a high-resolution analog-to-digital converter. A flexible input configuration allows a wide variety of input volt- age and current formats to be used, and an open-collector output with separate digital ground allows simple interfacing to either standard logic families or opto-couplers. The linearity error of the AD650 is typically 20 ppm (0.002% of full scale) and 50 ppm (0.005%) maximum at 10 kHz full scale. This corresponds to approximately 14-bit linearity in an analog-to-digital converter circuit. Higher full-scale frequencies or longer count intervals can be used for higher resolution con- versions. The AD650 has a useful dynamic range of six decades allowing extremely high resolution measurements. Even at 1 MHz full scale, linearity is guaranteed less than 1000 ppm (0.1%) on the AD650KN, BD, and SD grades. In addition to analog-to-digital conversion, the AD650 can be used in isolated analog signal transmission applications, phased locked- loop circuits, and precision stepper motor speed controllers. In the F/V mode, the AD650 can be used in precision tachometer and FM demodulator circuits. The input signal range and full-scale output frequency are user- programmable with two external capacitors and one resistor. Input offset voltage can be trimmed to zero with an external potentiometer. The AD650JN and AD650KN are offered in a plastic 14-lead DIP package. The AD650JP is available in a 20-lead plastic leaded chip carrier (PLCC). Both plastic pac kaged versions of the AD650 are specified for the commercial (0°C to +70°C) tempera- ture range. For industrial temperature range (–25 °C to +85°C) applications, the AD650AD and AD650BD are offered in a ceramic package. The AD650SD is specified for the full –55 °C to +125°C extended temperature range. PRODUCT HIGHLIGHTS 1. In addition to very high linearity, the AD650 can operate at full-scale output frequency up to 1 MHz. The combination of these two features makes the AD650 an inexpensive solution for applications requiring high resolution monotonic A/D conversion. 2. The AD650 has a very versatile architecture that can be con- figured to accommodate bipolar, unipolar, or differential input voltages, or unipolar input currents. 3. TTL or CMOS compatibility is achieved using an open collector frequency output. The pull-up resistor can be connected to voltages up to +30 V, or +15 V or +5 V for conventional CMOS or TTL logic levels. 4. The same components used for V/F conversion can also be used for F/V conversion by adding a simple logic biasing net- work and reconfiguring the AD650. 5. The AD650 provides separate analog and digital grounds. This feature allows prevention of ground loops in real-world applications. 6. The AD650 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD650/883B data sheet for detailed specifications. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD650J/AD650A AD650K/AD650B AD650S Model Min Typ Max Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE Full-Scale Frequency Range 1 1 1 MHz Nonlinearity Full-Scale Calibration Error 2, 100 kHz ± 5 ± 5 ± 5% Full-Scale Calibration Error 2, 1 MHz ± 10 ± 10 ± 10 % vs. Temperaturc A, B, and S Grades at 10 kHz ± 75 ± 75 ± 75 ppm/°C at 100 kHz ± 150 ± 150 ± 150 ppm/°C J and K Grades at 10 kHz ± 75 ± 75 ppm/ °C at 100 kHz ± 150 ± 150 ppm/ °C BIPOLAR OFFSET CURRENT DYNAMIC RESPONSE Maximum Settling Time for Full Scale Step Input 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs Overload Recovery Time Step Input 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs ANALOLG INPUT AMPLIFIER (V/F Conversion) Current Input Range (Figure 1) 0 +0.6 0 +0.6 0 +0.6 mA Voltage Input Range (Figure 5) –10 0 –10 0 –10 0 V Differential Impedance 2 M Ω/H2064810 pF 2 M Ω/H2064810 pF 2 M Ω/H2064810 pF Common-Mode Impedance 1000 M Ω/H2064810 pF 1000 M Ω/H2064810 pF 1000 M Ω/H2064810 pF Input Bias Current Noninverting Input 40 100 40 100 40 100 nA Inverting Input ±8 /H1155020 ±8 /H1155020 ±8 /H1155020 nA Input Offset Voltage (Trimmable to Zero) /H115504 /H115504 /H115504 mV vs. Temperature (T MIN to TMAX) ±30 ±30 ±30 µ V/°C Safe Input Voltage ±VS ±VS ±VS C COMPARATOR (F/V Conversion) Logic “0” Level –V S –1 –V S –1 –V S +1 V Logic “1” Level 0 +V S 0+ V S 0+ V S V Input Impedance 250 250 250 k Ω OPEN COLLECTOR OUTPUT (V/F Conversion) Output Voltage in Logic “0” ISINK ≤ 8 mA, TMIN to TMAX 0.4 0.4 0.4 V Output Leakage Current in Logic “1” 100 100 100 nA Voltage Range5 0 +36 0 +36 0 +36 V AMPLIFIER OUTPUT (F/V Conversion) Voltage Range (1500 Ω min Load Resistance) 0 +10 0 +10 0 +10 V Source Current (750 Ω max Load Resistance) 10 10 10 mA Capacitive Load (Without Oscillation) 100 100 100 pF POWER SUPPLY Voltage, Rated Performance ±9 /H1155018 ±9 /H1155018 ±9 /H1155018 V Quiescent Current 88 8 mA TEMPERATURE RANGE Rated Performance – N Package 0 +70 0 +70 °C Rated Performance – D Package –25 +85 –25 +85 –55 +125 °C NOTES 1Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale. 2Full-scale calibration error adjustable to zero. 3Measured at full-scale output frequency of 100 kHz. 4Refer to F/V conversion section of the text. 5Referred to digital ground. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality le vels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. AD650–SPECIFICATIONS(@ +25/H11543C, with VS = /H1155015 V, unless otherwise noted) REV. C–2–

REV. C –3– ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN NO. D-14 N-14 P-20A 1V OUT VOUT NC 2 +IN +IN V OUT 3 –IN –IN +IN

4 BIPOLAR OFFSET BIPOLAR OFFSET –IN

5– V S –VS NC

6 ONE SHOT ONE SHOT BIPOLAR OFFSET

CAPACITOR CAPACITOR CURRENT 7N C N C N C 8F OUTPUT FOUTPUT –VS

9 COMPARATOR COMPARATOR ONE SHOT

10 DIGITAL GND DIGITAL GND NC

11 ANALOG GND ANALOG GND NC

13 OFFSET NULL OFFSET NULL COMPARATOR

14 OFFSET NULL OFFSET NULL DIGITAL GND

16 ANALOG GND

S

19 OFFSET NULL

20 OFFSET NULL

ppm/ /H11543C 1 MHz Temperature Package Package Model 100 kHz Linearity Range /H11543C Description Option AD650JN 150 typ 0.1% typ 0 to +70 Plastic DIP N-14 AD650KN 150 typ 0.1% max 0 to +70 Plastic DIP N-14 AD650JP 150 typ 0.1% typ 0 to +70 Plastic Leaded Chip Carrier (PLCC) P-20A AD650AD 150 max 0.1% typ –25 to +85 Ceramic DIP D-14 AD650BD 150 max 0.1% max –25 to +85 Ceramic DIP D-14 AD650SD 150 max 0.1% max –55 to +125 Ceramic DIP D-14

Figure 7. 1 MHz V/F Connection Diagram pins and analog signal ground for proper bypassing on the AD650. practice is strongly discouraged in high accuracy analog design. Separate digital and analog grounds are provided on the AD650. with the frequency output signal. supply, for example, the open collector output will draw 10 mA. 12 inches of 20 gauge wire will produce a voltage spike of 50 mV. these types of switching transients. short, and second, the loop will not radiate RFI efficiently. reduction of interference can be found in Reference 1. voltage always decreases in magnitude as temperature is increased.

Figure 14. Phase Locked Loop F/V Conversion compact size and wide dynamic range. the AD650 slightly, driving the system towards synchronization. phase detector are incorporated into the p hase detector gain, Kd. natural frequency of 35 kHz with a damping factor of 0.8.

  1. Determine K o (in units of radians per volt second) from the

maximum output voltage V MAX.

  1. Calculate a value for C based upon the de sired loop band-

though it is transmitted over a 1 MHz carrier.

  1. Calculate R to yield a damping factor of approximately 0.8
  • 2 .5×106 Rad • Ω V R units OHMS fn units HERTZ (15) Ko units RAD/VOLT•SEC If in actual operation the PLL overshoots or hunts excessively before reaching a final value, the damping factor may be raised by increasing the value of R. Conversely, if the PLL is over- damped, a smaller value of R should be used. 3“Phase lock Techniques,” 2nd Edition, by F.M. Gardner, (John Wiley and Sons, 1979)

REV. C–12– PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Ceramic DIP (D-14) 1 7 0.098 (2.49) MAX 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) MIN PIN 1 0.100 (2.54) BSC SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) MAX 0.785 (19.94) MAX 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)14-Lead Plastic DIP (N-14) PIN 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) BSC SEATING PLANE 0.060 (1.52) MAX 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 20-Lead PLCC (P-20A) PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 0.395 (10.02) 0.385 (9.78)SQ 0.356 (9.04) 0.350 (8.89) SQ 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)0.020 (0.50) R 0.050 (1.27) BSC 0.021 (0.53) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16)