AD630_V01 AD | Alldatasheet
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Balanced Modulator/Demodulator Data Sheet AD630 Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Recovers signal from 100 dB noise
2 MHz channel bandwidth
45 V/µs slew rate
Low crosstalk: −120 dB at 1 kHz, −100 dB at 10 kHz Pin programmable, closed-loop gains of ±1 and ±2 0.05% closed-loop gain accuracy and match 100 µV channel offset voltage (AD630) 350 kHz full power bandwidth Chips available
APPLICATIONS
Balanced modulation and demodulation Synchronous detection Phase detection Quadrature detection Phase sensitive detection Lock in amplification Square wave multiplication FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD630 is a high precision balanced modulator/demodulator that combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film resistors. A network of on-board applications resistors provides precision closed-loop gains of ±1 and ±2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of 1, 2, 3, or 4. External feedback enables high gain or complex switched feedback topologies. The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. The AD630 is used in precision signal processing and instru- mentation applications that require wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, the AD630 can recover a small signal from 100 dB of interfering noise (see the Lock-In Amplifier Applications section). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Other features of the AD630 include pin programmable frequency compensation; optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the two differential inputs is active. PRODUCT HIGHLIGHTS 1. The application flexibility of the AD630 makes it the best choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification. 2. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. 3. The op amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. 4. The AD630 can be used as a 2-channel multiplexer with gains of 1, 2, 3, or 4. The channel separation of 100 dB at 10 kHz approaches the limit achievable with an empty IC package. 5. Laser trimming of the comparator and amplifying channel offsets eliminate the need for external nulling in most cases. CM OFF ADJ CM OFF ADJ DIFF OFF ADJ DIFF OFF ADJ 2.5kΩ AMP A 2.5kΩ AMP B 10kΩ 10kΩ 5kΩ COMP RINA CH A+ CH A– RINB CH B+ CH B– SEL B SEL A COMP +VS VOUT RB RF RA CHANNEL STATUS B/A –VS A B 00784-001 BIAS +VS
Rev. G | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
12/2016—Rev. F to Rev. G 7/2015—Rev. E to Rev. F Changes to Features Section, General Description Section, 6/2004—Rev. D to Rev. E 6/2001—Rev. C to Rev. D
Rev. G | Page 3 of 20 SPECIFICATIONS At 25°C and ±VS = ±15 V , unless otherwise noted. Table 1. Parameter AD630J/AD630A AD630K/AD630B AD630S Unit Min Typ Max Min Typ Max Min Typ Max GAIN Open-Loop Gain 90 110 100 120 90 110 dB ±1, ±2 Closed-Loop Gain Error 0.1 0.05 0.1 % Closed-Loop Gain Match 0.1 0.05 0.1 % Closed-Loop Gain Drift 2 2 2 ppm/°C CHANNEL INPUTS VIN Operational Limit1 (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) V Input Offset Voltage 500 100 500 µV TMIN to TMAX 800 160 1000 µV Input Bias Current 100 300 100 300 100 300 nA Input Offset Current 10 50 10 50 10 50 nA Channel Separation at 10 kHz 100 100 100 dB COMPARATOR VIN Operational Limit1 (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.3) V Switching Window ±1.5 ±1.5 ±1.5 mV TMIN to TMAX ±2.0 ±2.0 ±2.5 mV Input Bias Current 100 300 100 300 100 300 nA Response Time (−5 mV to +5 mV Step) 200 200 200 ns Channel Status ISINK at VOL = −VS + 0.4 V2 1.6 1.6 1.6 mA Pull-Up Voltage (−VS + 33) (−VS + 33) (−VS + 33) V DYNAMIC PERFORMANCE Unity Gain Bandwidth 2 2 2 MHz Slew Rate3 45 45 45 V/µs Settling Time to 0.1% (20 V Step) 3 3 3 µs OPERATING CHARACTERISTICS Common-Mode Rejection 85 105 90 110 90 110 dB Power Supply Rejection 90 110 90 110 90 110 dB Supply Voltage Range ±5 ±16.5 ±5 ±16.5 ±5 ±16.5 V Supply Current 4 5 4 5 4 5 mA OUTPUT VOLTAGE, AT RL = 2 kΩ TMIN to TMAX ±10 ±10 ±10 V Output Short-Circuit Current 25 25 25 mA TEMPERATURE RANGES N Package 0 70 0 70 °C D Package −25 +85 −25 +85 −55 +125 °C 1 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2 ISINK at VOL = (−VS + 1 V) is typically 4 mA. 3 Pin 12 open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/µs.
Figure 3. 20-Lead SOIC Pin Configuration Table 4. 20-Lead SOIC Pin Function Descriptions
2 CH A+ Noninverting Input of Op Amp A
3 DIFF OFF ADJ Differential Offset Adjustment
4 DIFF OFF ADJ Differential Offset Adjustment
5 CM OFF ADJ Common-Mode Offset Adjustment
6 CM OFF ADJ Common-Mode Offset Adjustment
7 CHANNEL STATUS B/A B or A Channel Status
9 SEL B B Channel Comparator Input
10 SEL A A Channel Comparator Input
12 COMP Pin to Connect Internal Compensation Capacitor
13 VOUT Output Voltage
14 RB 10 kΩ Gain Setting Resistor
15 RF 10 kΩ Feedback Resistor
16 RA 5 kΩ Feedback Resistor
18 CH B+ Noninverting Input of Op Amp B
19 CH B− Inverting Input of Op Amp B
20 CH A− Inverting Input of Op Amp A
Figure 4. 20-Lead PDIP Pin Configuration Table 5. 20-Lead PDIP Pin Function Descriptions
Figure 5. 20-Lead CERDIP Pin Configuration Table 6. 20-Lead CERDIP Pin Function Descriptions
Figure 6. 20-Terminal CLCC Pin Configuration Table 7. 20-Terminal CLCC Pin Function Descriptions
of the two switching cells is selected. which, as a consequence, remains off. amplifier into single-ended form for the output integrator. output to produce a low impedance output. Figure 24. AD630 Simplified Schematic
has a minor effect on the pole-zero locations. unity gain while the low frequency components are amplified. This arrangement is useful in demodulators and lock-in amplifiers. Figure 25. AD630 with External Feedback by a low impedance source, which remains stiff at high frequencies. This is generally a wideband buffer amplifier. means of an optional self-contained compensation capacitor. bandwidth and slew rate for closed loop gains of |2| and above.