AD621A

AD621 AD | Alldatasheet

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8-Lead Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages TOP VIEW (Not to Scale) G = 10/100 –IN +IN G = 10/100 +VS OUTPUT REF–VS AD621 REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Low Drift, Low Power Instrumentation Amplifier AD621

FEATURES

Pin-Strappable Gains of 10 and 100 All Errors Specified for Total System Performance Higher Performance than Discrete In Amp Designs Available in 8-Lead DIP and SOIC Low Power, 1.3 mA Max Supply Current Wide Power Supply Range ( /H115502.3 V to /H1155018 V) EXCELLENT DC PERFORMANCE 0.15% Max, Total Gain Error /H115505 ppm//H11543C, Total Gain Drift 125 /H9262V Max, Total Offset Voltage 1.0 /H9262V//H11543C Max, Offset Voltage Drift LOW NOISE 9 nV/√Hz, @ 1 kHz, Input Voltage Noise 0.28 /H9262V p-p Noise (0.1 Hz to 10 Hz) EXCELLENT AC SPECIFICATIONS 800 kHz Bandwidth (G = 10), 200 kHz (G = 100) 12 /H9262s Settling Time to 0.01%

APPLICATIONS

Transducer Interface and Data Acquisition Systems Industrial Process Controls Battery-Powered and Portable Equipment PRODUCT DESCRIPTION The AD621 is an easy to use, low cost, low power, high accu- racy instrumentation amplifier that is ideally suited for a wide range of applications. Its unique combination of high perfor- mance, small size and low power, outperforms discrete in amp implementations. High functionality, low gain errors, and low SUPPL Y CURRENT – mA 30,000 25,000 02 0 5 TOT AL ERROR, ppm OF FULL SCALE 10 15 20,000 15,000 10,000 5,000 AD621A

3 OP AMP

(3 OP 07S) Figure 1. Three Op Amp IA Designs vs. AD621 therefore, simplifying the design process. lithic instrumentation amplifiers. 10 Hz. Input current noise is also extremely low at 0.1 pA/ √Hz. Figure 2. Total Voltage Noise vs. Source Resistance

AD621–SPECIFICATIONS Gain = 10 AD621A AD621B AD621S 1 Model Conditions Min Typ Max Min Typ Max Min Typ Max Unit GAIN Gain Error V OUT = ±10 V 0.15 0.05 0.15 % Nonlinearity, VOUT = –10 V to +10 V R L = 2 kΩ 2 10 2 10 2 10 ppm of FS Gain vs. Temperature –1.5 ±5 –1.5 ±5– 1 ±5 ppm/ °C TOTAL VOLTAGE OFFSET Offset (RTI) V S = ±15 V 75 250 50 125 75 250 µV Over Temperature V S = ±5 V to ±15 V 400 215 500 µV Offset Referred to the Input vs. Supply (PSR) 2 VS = ±2.3 V to ± 18 V 95 120 100 120 95 120 dB Total NOISE Voltage Noise (RTI) 1 kHz 13 17 13 17 13 17 nV/ √Hz Current Noise f = 1 kHz 100 100 100 fA/ √Hz

0.1 Hz–10 Hz 10 10 10 pA p-p

INPUT CURRENT V S = ±15 V Over Temperature 2.5 1.5 4 nA Average TC 3.0 3.0 8.0 pA/ °C Over Temperature 1.5 0.75 2.0 nA Average TC 1.5 1.5 8.0 pA/ °C INPUT Input Impedance Differential 10 /H2064821 0 /H2064821 0 /H206482G Ω/H20648pF Common-Mode 10 /H2064821 0 /H2064821 0 /H206482G Ω/H20648pF Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance V CM = 0 V to ± 10 V 93 110 100 110 93 110 dB OUTPUT Output Swing R L = 10 kΩ, Short Current Circuit ±18 ±18 ±18 mA DYNAMIC RESPONSE Small Signal, –3 dB Bandwidth 800 800 800 kHz Settling Time to 0.01% 10 V Step 12 12 12 µs REFERENCE INPUT RIN 20 20 20 k Ω IIN VIN +, VREF = 0 50 60 50 60 +50 +60 µA Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001 POWER SUPPLY Operating Range ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V TEMPERATURE RANGE For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C NOTES 1See Analog Devices’ military data sheet for 883B tested specifications. 2This is defined as the supply range over which PSRR is defined. 3Input Voltage Range = CMV + (Gain × VDIFF). Specifications subject to change without notice. (Typical @ 25/H11543C, VS = /H1155015 V, and RL = 2 k/H9024, unless otherwise noted.) REV. B–2–

Model Conditions Min Typ Max Min Typ Max Min Typ Max Unit GAIN Gain Error V OUT = ±10 V 0.15 0.05 0.15 % Nonlinearity, VOUT = –10 V to +10 V R L = 2 kΩ 2 10 2 10 2 10 ppm of FS Gain vs. Temperature –1 ±5– 1 ±5– 1 ±5 ppm/ °C TOTAL VOLTAGE OFFSET Offset (RTI) V S = ±15 V 35 125 25 50 35 125 µV Over Temperature V S = ±5 V to ±15 V 185 215 225 µV Offset Referred to the Input vs. Supply (PSR) 2 VS = ±2.3 V to ±18 V 110 140 120 140 110 140 dB Total NOISE Voltage Noise (RTI) 1 kHz 9 13 9 13 9 13 nV/ √Hz Current Noise f = 1 kHz 100 100 100 fA/ √Hz INPUT CURRENT V S = ±15 V Over Temperature 2.5 1.5 4 nA Average TC 3.0 3.0 8.0 pA/ °C Over Temperature 1.5 0.75 2.0 nA Average TC 1.5 1.5 8.0 pA/ °C INPUT Input Impedance Differential 10 /H2064821 0 /H2064821 0 /H206482G Ω/H20648pF Common-Mode 10 /H2064821 0 /H2064821 0 /H206482G Ω/H20648pF Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance V CM = 0 V to ±10 V 110 130 120 130 110 130 dB OUTPUT Output Swing R L = 10 kΩ, Short Current Circuit ±18 ±18 ±18 mA DYNAMIC RESPONSE Small Signal, –3 dB Bandwidth 200 200 200 kHz Settling Time to 0.01% 10 V Step 12 12 12 µs REFERENCE INPUT RIN 20 20 20 k Ω IIN VIN +, VREF = 0 5 06 0 5 06 0 5 0 6 0 µA Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001 POWER SUPPLY Operating Range ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V TEMPERATURE RANGE For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C NOTES 1See Analog Devices’ military data sheet for 883B tested specifications. 2This is defined as the supply range over which PSEE is defined. 3Input Voltage Range = CMV + (Gain × VDIFF). Specifications subject to change without notice. Gain = 100 (Typical @ 25/H11543C, VS = /H1155015 V, and RL = 2 k/H9024, unless otherwise noted.) AD621 REV. B –3–

REV. B–4– NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 8-Lead Plastic Package: θJA = 95°C/W 8-Lead Cerdip Package: θJA = 110°C/W 8-Lead SOIC Package: θJA = 155°C/W ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range Lead Temperature Range ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD621 features proprietary ESD pro- tection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis- charges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Package Model Range Description Option 1 AD621AN –40 °C to +85°C 8-Lead Plastic DIP N-8 AD621BN –40 °C to +85°C 8-Lead Plastic DIP N-8 AD621AR –40 °C to +85°C 8-Lead Plastic SOIC R-8 AD621BR –40 °C to +85°C 8-Lead Plastic SOIC R-8 AD621SQ/883B2 –55°C to +125°C 8-Lead Cerdip Q-8 AD621ACHIPS –40 °C to +85°C Die NOTES 1N = Plastic DIP; Q = Cerdip; R = SOIC. 2See Analog Devices’ military data sheet for 883B specifications. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. 1.125 (3.57) 0.0708 (2.545) REFERENCE RG 1 RG 8 +VS 4 –VS –IN +IN OUTPUT

Typical Performance Characteristics–AD621 INPUT OFFSET VOLTAGE – /H9262V –200 –100 PERCENTAGE OF UNITS 0 +100 +200 SAMPLE SIZE = 90 TPC 1. Typical Distribution of VOS, Gain = 10 INPUT OFFSET VOLTAGE – /H9262V –80 –40 PERCENTAGE OF UNITS 0 +40 +80 SAMPLE SIZE = 90 TPC 2. Typical Distribution of VOS, Gain = 100 INPUT OFFSET CURRENT – pA –400 –200 PERCENT AGE OF UNITS 0 +200 +400 SAMPLE SIZE = 90 TPC 3. Typical Distribution of Input Offset Current REV. B –5– INPUT BIAS CURRENT – pA –800 –400 PERCENT AGE OF UNITS 0 +400 +800 SAMPLE SIZE = 90 TPC 4. Typical Distribution of Input Bias Current WARM-UP TIME – Minutes 2.0 05 1 CHANGE IN OFFSET VOLTAGE – /H9262V 1.5 1.0 0.5 TPC 5. Change in Input Offset Voltage vs. Warm-Up Time FREQUENCY – Hz 1000 100 1 100k 10 VOLTAGE NOISE – nV/ Hz 100 1k 10k GAIN = 10 GAIN = 100 TPC 6. Voltage Noise Spectral Density

REV. B–6– FREQUENCY – Hz 1000 100 1 10 CURRENT NOISE – nV/ Hz 100 1000 TPC 7. Current Noise Spectral Density vs. Frequency TIME – 1 sec/div RTI NOISE – 0.2/H9262V/div TPC 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10 TIME – 1 sec/div RTI NOISE – 0.1/H9262V/div TPC 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 100 1s100mV TPC 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical Div, 1 Second per Horizontal Div 100 1000 AD621A FET INPUT IN AMP SOURCE RESISTANCE – /H9024 TOTAL DRIFT FROM 25/H11543C TO 85/H11543C, RTI – /H9262V 100,000 1k 10M 10,000 10k 1M 100k TPC 10. Total Drift vs. Source Resistance FREQUENCY – Hz 0.1 1M 1 10 100 1k 10k 100k 160 CMR – dB 140 120 100 GAIN = 100 GAIN = 10 TPC 11. CMR vs. Frequency, RTI, for a Zero to 1 kΩ Source Imbalance

REV. B –7– FREQUENCY – Hz PSR – dB 160 0.1 140 100 120 100k10k1k10010 G = 100 G = 10 180 TPC 12. Positive PSR vs. Frequency FREQUENCY – Hz PSR – dB 160 0.1 140 100 120 100k10k1k10010 G = 100 G = 10 180 TPC 13. Negative PSR vs. Frequency 1000 100 10M 100 100k 1M10k FREQUENCY – Hz CLOSED-LOOP GAIN – V/V 0.1 TPC 14. Closed-Loop Gain vs. Frequency OUTPUT VOLTAGE – Volts p-p FREQUENCY – Hz 10k 100k G = 10 & 100 TPC 15. Large Signal Frequency Response INPUT VOLTAGE LIMIT – Volts (REFERRED TO SUPPLY VOLTAGES) +1.0 +0.5 +1.5 –1.5 –1.0 –0.5 1510 SUPPLY VOLTAGE /H11550 Volts –0.0 +0.0 +VS –VS TPC 16. Input Voltage Range vs. Supply Voltage INPUT VOLTAGE LIMIT – Volts (REFERRED TO SUPPLY VOLTAGES) +1.0 +0.5 +1.5 –1.5 –1.0 –0.5 1510 SUPPLY VOLTAGE /H11550 Volts –0.0 +0.0 +VS –VS RL = 10k/H9024 RL = 2k/H9024 RL = 10k/H9024 RL = 2k/H9024 TPC 17. Output Voltage Swing vs. Supply Voltage, G = 10

REV. B–8– OUTPUT VOLTAGE SWING – Volts p-p LOAD RESISTANCE – /H9024 0 10k 100 1k VS = /H11550 15V G = 10 TPC 18. Output Voltage Swing vs. Resistive Load 100 10/H9262s5V 1mV TPC 19. Large Signal Pulse Response and Settling Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 kΩ, CL = 100 pF 100 10/H9262s20mV TPC 20. Small Signal Pulse Response, G = 10, RL = 1 kΩ, CL = 100 pF 100 10/H9262s5V 1mV TPC 21. Large Signal Pulse Response and Settling Time, G = 100 (0.5 mV = 0.1%), RL = 2 kΩ, CL = 100 pF 100 10/H9262s20mV TPC 22. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF OUTPUT STEP SIZE – Volts SETTLING TIME – /H9262s 02 0 10 15 TO 0.01% TO 0.1% TPC 23. Settling Time vs. Step Size, G = 10

REV. B –9– OUTPUT STEP SIZE – Volts SETTLING TIME – /H9262s 02 0 10 15 TO 0.01% TO 0.1% TPC 24. Settling Time vs. Step Size, Gain = 100 TEMPERATURE – /H11543C INPUT CURRENT – nA +IB –IB 2.0 –2.0 175 –1.0 –1.5 –75 –0.5 0.5 1.0 1.5 1257525–25–125 TPC 25. Input Bias Current vs. Temperature 100 100/H9262V0PW 0

20 WFM AQR WARNING0 WFM

TPC 26. Gain Nonlinearity, G = 100, RL = 10 kΩ, CL = 0 pF. Vertical Scale: 100 µV/Div = 100 ppm/Div Horizontal Scale: 2 Volts/Div 100 2V100/H9262V TPC 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical Scale: 100 µV/Div = 100 ppm/Div, Horizontal Scale:

2 Volts/Div

+VS –VS G = 10 G = 100 G = 10 G = 100 INPUT 20V p-p 10k/H9024 10k/H9024 100k/H9024 VOUT 11k/H9024 0.1% 1k/H9024 0.1% TPC 28. Settling Time Test Circuit

Figure 3. Simplified Schematic of AD621 On chip gain resistors are pretrimmed for gains of 10 and 100.

1. Special design techniques assure a low gain TC of 5 ppm/°C

single-ended output referred to the REF pin potential. ductance increases asymptotically to that of the input transistors. the effect various error sources have on circuit accuracy. gain nonlinearity and noise, thus allowing full 14-bit accuracy. both contributing to the overall input error.

3 OP AMP, IN AMP, G = 100

Figure 4. Make vs. Buy

0 TO /H1155010V

USE THIS IN PLACE OF THE DAC FOR ZERO SUPPRESSION FUNCTION. Figure 6. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal differential input, V1 would be at 10.5 V and V2 at 9.5 V. Figure 7. Typical Three Op Amp Instrumentation differential-mode input for ±15 V supplies and G = 10. VOUT1 or VOUT2 may be used as the output. Figure 8. Trade-Off Between VCM and VDIFF Range (VS =

REV. B–16– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-8) Package 0.125 (3.18) MIN 0.165 0.01 (4.19 0.25) 0.39 (9.91) MAX 0.25 (6.35) 0.035 0.01 (0.89 0.25) 0.018 0.003 (0.46 0.08) 0.30 (7.62) REF 0 - 15 0.10 (2.54) TYP 0.011 0.003 (4.57 0.76) SEATING PLANE 0.31 (7.87) 0.18 0.03 (4.57 0.76) 0.033 (0.84) NOM Cerdip (Q-8) Package 0.005 (0.13) MIN 0.055 (1.4) MAX 0.405 (10.29) MAX 0.150 (3.81) MIN 0.200 (5.08) MAX 0.310 (7.87) 0.030 (0.76) 0.200 (5.08) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0 - 15 0.015 (0.38) BSC SEATING PLANE 0.060 (1.52) 0.015 (0.38) SOIC (R-8) Package 0.181 (4.60) 0.205 (5.20) 0.020 (0.50) 0.045 (1.15) 0.007 (0.18) 0.094(2.39) 0.004 (0.10) 0.010 (0.25) 1 4 0.188 (4.77) 0.198 (5.03) 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.200) 0.014 (0.36) 0.018 (0.46) 0.050 (1.27) TYP PRINTED IN U.S.A.