AD61009

AD61009 AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Low Power Mixer

3 V Receiver IF Subsystem

FEATURES

Complete Receiver-on-a-Chip: Monoceiver ® Mixer –15 dBm 1 dB Compression Point –8 dBm Input Third Order Intercept

500 MHz RF and LO Bandwidths

On-Board Phase-Locked Quadrature Oscillator Demodulates IFs from 1 MHz to 12 MHz Can Also Demodulate AM, CW, SSB Low Power 25 mW at 3 V CMOS Compatible Power-Down

APPLICATIONS

Battery-Powered Communications Receivers PIN CONFIGURATION 20-Lead SSOP (RS Suffix) TOP VIEW (Not to Scale) AD61009 FDIN QOUT IOUT FLTR VPS1 COM1 PRUP LOIP IFOP DMIP VPS2RFLO RFHI GREF MXOP VMID IFHI IFLO GAIN COM2 GENERAL DESCRIPTION The AD61009 is a 3 V low power receiver IF subsystem for opera- tion at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and Q demodulators, a ph ase-locked quadrature oscillator, and a biasing system with external power-down. The AD61009’s low noise, high intercept mixer is a doubly- balanced Gilbert cell type. It has a nominal –15 dBm input referred 1 dB compression point and a –8 dBm input referred third-order intercept. The mixer section of the AD 61009 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to –16 dBm. In MGC operation, the AD61009 accepts an external gain- control voltage input from an external AGC detector or a DAC. A quadrature VCO phase-locked to the IF drives the I and Q demodulators. The I and Q demodulators can also dem odu- late AM; when the AD61009’s quadrature VCO is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for AM. The VCO can also be phase-locked to an external beat-frequency oscillator (BFO), and the demodulator serves as a product detector for CW or SSB reception. Finally, the AD61009 can be used to demodu- late BPSK using an external Costas Loop for carrier recovery. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Monoceiver is a registered trademark of Analog Devices, Inc.

AD61009–SPECIFICATIONS REV. 0–2– (@ TA = 25/H11543C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted) Model AD61009ARS Conditions Min Typ Max Unit DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency Range For Con version Gain > 20 dB 500 MHz Maximum Mixer Input Voltage For Linear Operation; Between RFHI and RFLO ±54 mV Input 1 dB Compression Point RF Input Terminated in 50 Ω –15 dBm Input Third-Order Intercept RF Input Terminated in 50 Ω –5 dBm Noise Figure Mat ched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz 14 dB Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz 12 dB Maximum Output Voltage at MXOP Z IF = 165 Ω, at Input Compression ±1.3 V Mixer Output Bandwidth at MXOP –3 dB, Z IF = 165 Ω 45 MHz LO Drive Level Mixer LO Input Terminated in 50 Ω –16 dBm LO Input Impedance LOIP to VMID 1 k Ω Isolation, RF to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 30 dB Isolation, LO to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 20 dB Isolation, LO to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 40 dB Isolation, IF to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 70 dB IF AMPLIFIERS Noise Figure Max Gain, f = 10.7 MHz 17 dB Input 1 dB Compression Point IF = 10.7 MHz –15 dBm Output Third-Order Intercept IF = 10.7 MHz 18 dBm Maximum IF Output Voltage at IFOP Z IF = 600 Ω± 560 mV Output Resistance at IFOP From IFOP to VMID 15 Ω Bandwidth –3 dB at IFOP, Max Gain 45 MHz GAIN CONTROL (See Figures 10 and 11) Gain Control Range Mixer + IF Section, GREF to 1.5 V 90 dB Gain Scaling GREF to 1.5 V 20 mV/dB GREF to General Reference Voltage V R 75/VR dB/V Gain Scaling Accuracy GREF to 1.5 V, 80 dB Span ±1d B Bias Current at GAIN 5 µA Bias Current at GREF 1 µA Input Resistance at GAIN, GREF 1M Ω I AND Q DEMODULATORS Required DC Bias at DMIP VPOS/2 V dc Input Resistance at DMIP From DMIP to VMID 50 k Ω Input Bias Current at DMIP 2 µA Maximum Input Voltage IF > 3 MHz ±150 mV IF ≤ 3 MHz ±75 mV Amplitude Balance IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz ±0.2 dB Quadrature Error IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz –3.5 –1.2 +1.5 Degrees Phase Noise in Degrees IF = 10.7 MHz, F = 10 kHz –100 dBc/Hz Demodulation Gain Sine Wave Input, Baseband Output 17.4 18 18.8 dB Maximum Output Voltage R L ≥ 20 kΩ± 1.23 V Output Offset Voltage Measured from I OUT, QOUT to VMID –100 10 +100 mV Output Bandwidth Sine Wave Input, Baseband Output 1.5 MHz PLL Required DC Bias at FDIN VPOS/2 V dc Input Resistance at FDIN From FDIN to VMID 50 k Ω Input Bias Current at FDIN 200 nA Frequency Range 1.0 to 12 MHz Required Input Drive Level Sine Wave Input at Pin 1 400 mV Acquisition Time to ±3° IF = 10.7 MHz 16.5 µs POWER-DOWN INTERFACE Logical Threshold For Power Up on Logical High 2 V dc Input Current for Logical High 75 µA Turn-On Response Time To PLL Locked 16.5 µs Standby Current 550 µA POWER SUPPLY Supply Range 2.85 5.5 V Supply Current 8.5 12.5 mA OPERATING TEMPERATURE TMIN to TMAX Operation to 2.85 V Minimum Supply Voltage –25 +85 °C Operation to 4.5 V Minimum Supply Voltage –40 +85 °C Specifications subject to change without notice.

REV. 0 –3– ABSOLUTE MAXIMUM RATINGS 1 2.7 V to 5.5 V Operating Temperature Range 4.5 V to 5.5 V Operating Temperature Range ORDERING GUIDE Model Temperature Range Package Description Package Option AD61009ARS –25 °C to +85°C for 2.7 V to 5.5 V 20-Lead Plastic SSOP RS-20 Operation; –40°C to +85°C for 4.5 V to 5.5 V Operation CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD61009 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE NOTES 1Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2Thermal Characteristics: 20-lead SSOP Package: θJA = 126°C/W.

REV. 0–4– AD61009 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Reads Function

1 FDIN Frequency Detector Input PLL input for I/Q demodulator quadrature oscillator, ±400 mV

drive required from external oscillator. Must be biased at V P/2. 2 COM1 Common #1 Supply common for RF front end and main bias.

3 PRUP Power-Up Input 3 V/5 V CMOS compatible power-up control; logical high =

powered-up; max input level = VPS1 = VPS2.

4 LOIP Local Oscillator Input LO input, ac coupled ±54 mV LO input required (–16 dBm for

50 Ω input termination). 5 RFLO RF “Low” Input Usually connected to ac ground. 6 RFHI RF “High” Input AC coupled, ±56 mV, max RF input for linear operation. 7 GREF Gain Reference Input High impedance input, typically 1.5 V, sets gain scaling. 8 MXOP Mixer Output High impedance, single-sided current output, ±1.3 V max voltage output (±6 mA max current output). 9 VMID Midsupply Bias Voltage Output of the midsupply bias generator (VMID = VPOS/2). 10 IFHI IF “High” Input AC coupled IF input, ±56 mV max input for linear operation. 11 IFLO IF “Low” Voltage Reference node for IF input; auto-offset null.

12 GAIN Gain Control Input High impedance input, 0 V–2 V using 3 V supply, max gain at

V = 0. 13 COM2 Common #2 Supply common for IF stages and demodulator.

14 IFOP IF Output Low impedance, single-sided voltage output, 5 dBm ( ±560 mV)

max.

15 DMIP Demodulator Input Signal input to I and Q demodulators ±150 mV max input at IF

3 MHz for linear operation; ±75 mV max input at IF < 3 MHz for linear operation. Must be biased at V P/2. 16 VPS2 VPOS Supply #2 Supply to high-level IF, PLL, and demodulators. 17 QOUT Quadrature Output Low impedance Q baseband output; ±1.23 V full scale in 20 k Ω min load; ac coupled. 18 IOUT In-Phase Output Low impedance I baseband output; ±1.23 V full scale in 20 k Ω min load; ac coupled. 19 FLTR PLL Loop Filter Series RC PLL Loop filter, connected to ground. 20 VPS1 VPOS Supply #1 Supply to mixer, low level IF, PLL, and gain control. PIN CONNECTION 20-Lead SSOP (RS-20) TOP VIEW (Not to Scale) AD61009 FDIN QOUT IOUT FLTR VPS1 COM1 PRUP LOIP IFOP DMIP VPS2RFLO RFHI GREF MXOP VMID IFHI IFLO GAIN COM2

IEEE RF_OUT SYNTHESIZER HP8656B IEEE RF_OUT SYNTHESIZER HP8656B IEEE RF_OUT SYNTHESIZER HP6633A IEEE VPOS VNEG SPOS SNEG DCPS HP34401A CPIB HI LO IDMM DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP8764B V 50/H9024 50/H9024 MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN HP8764B V 50/H9024 50/H9024 HP8594E RF_IN IEEE SPEC AN HP8765B0 1 C S0 S1V 1k/H9024 CHARACTERIZATION BOARD HP8765B0 S0 S1V P6205 X10 OUT FET PROBE TEK1105 IN1 OUT1 IN2 OUT2 PROBE SUPPLY TPC 1. Mixer/Amplifier Test Set HP346B 28V NOISE NOISE SOURCE HP8656B IEEE RF_OUT SYNTHESIZER MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN HP8765B 0 S0S1 V 50/H9024 CHARACTERIZATION BOARD HP8765B0 S0 S1V HP8720C IEEE_488 PORT_1 PORT_2 NETWORK AN HP6633A IEEE VPOS VNEG SPOS SNEG DCPS DP8200 IEEE VPOS VNEG SPOS SNEGVREF HP8970A RF_IN 28V_OUT NOISE FIGURE METER TPC 2. Mixer Noise Figure Test Set Typical Performance Characteristics–AD61009 REV. 0 –5–

REV. 0–6– AD61009 HP346B 28V NOISE NOISE SOURCE MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD HP6633A IEEE VPOS VNEG SPOS SNEG DCPS DP8200 IEEE VPOS VNEG SPOS SNEGVREF HP8970A RF_IN 28V_OUT NOISE FIGURE METER P6205 X10 OUT FET PROBE TEK1103 IN1 OUT1 IN2 OUT2 PROBE SUPPLY TPC 3. IF Amp Noise Figure Test Set MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD HP8764B V 50/H9024 50/H9024 HP6633A IEEE VPOS VNEG SPOS SNEG DCPS DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP3326A IEEE OUTPUT_1 OUTPUT_2 DUAL SYNTHESIZER DCFM HP8656B IEEE RF_OUT SYNTHESIZER P6205 X10 FET PROBE P6205 X10 FET PROBE OUT OUT 1103 OUT1 OUT2 PROBE SUPPLY HP8765B 0 S0S1 V HP8765B0 S0 S1V HP8694E RF_IN IEEE SPEC AN HP54120 CH1 DIGITAL OSCILLOSCOPE CH2 CH3 CH4 TRIG IEEE_488 IN1 IN2 TPC 4. PLL/Demodulator Test Set

REV. 0 –7– DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP34401A GPIB HI LO IDMM HP6633A IEEE VPOS VNEG SPOS SNEG DCPS 499k/H9024 MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD TPC 5. GAIN Pin Bias Test Set DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP34401A GPIB HI LO IDMM HP6633A IEEE VPOS VNEG SPOS SNEG DCPS 499k/H9024 MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD TPC 6. Demodulator Bias Test Set HP6633A IEEE VPOS VNEG SPOS SNEG DCPS HP34401A GPIB HI LO I DMM HP6633A IEEE VPOS VNEG SPOS SNEG DCPS 10k/H9024 HP3325B IEEE RF_OUT SYNTHESIZER HP8594E RF_IN IEEE SPEC AN MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD TPC 7. Power-Up Threshold Test Set

REV. 0–8– AD61009 HP6633A IEEE VPOS VNEG SPOS SNEG DCPS FL6082A RF_OUTIEEE MOD_OUT DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP8112 PULSE_OUTIEEE PULSE GENERATOR HP54120 CH1 CH2 CH3 CH4 TRIG IEEE_488 P6205 X10 OUT FET PROBE 1103 IN1 OUT1 IN2 OUT2 PROBE SUPPLY P6205 X10 OUT FET PROBE 50/H9024 DIGITAL OSCILLOSCOPE NOTE: MUST BE 3 RESISTOR POWER DIVIDER MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD TPC 8. Power-Up Test Set HP8594E RF_IN IEEE SPEC AN P6205 X10 OUT FET PROBE 1103 IN1 OUT1 IN2 OUT2 PROBE SUPPLY HP6633A IEEE VPOS VNEG SPOS SNEG DCPS HP8656B RF_OUTIEEE SYNTHESIZER R1 1k/H9024 MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN BIASVPOS PRUP GAIN CHARACTERIZATION BOARD TPC 9. IF Output Impedance Test Set

REV. 0 –9– HP6633A IEEE VPOS VNEG SPOS SNEG DCPS DP8200 IEEE VPOS VNEG SPOS SNEG VREF P6205 X10 FET PROBE P6205 X10 FET PROBE OUT OUT 1103 OUT1 OUT2 PROBE SUPPLY HP54120 CH1 DIGITAL OSCILLOSCOPE CH2 CH3 CH4 TRIG IEEE_488 IN1 IN2 FL6082A IEEE RF_OUT MOD_OUT 20/H9024 dB MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN VPOS PRUP GAIN CHARACTERIZATION BOARD BIAS TPC 10. PLL Settling Time Test Set HP6633A IEEE VPOS VNEG SPOS SNEG DCPS DP8200 IEEE VPOS VNEG SPOS SNEG VREF HP3326 IEEE OUTPUT_1 OUTPUT_2 DUAL SYNTHESIZER DCFM HP3325B IEEE RF_OUT SYNTHESIZER P6205 X10 FET PROBE P6205 X10 FET PROBE OUT OUT 1103 OUT1 OUT2 PROBE SUPPLY HP8765B0 S0 S1V HP8694E RF_IN IEEE SPEC AN IN1 IN2 MXOPRFHI LOIP L R X IFOPIFHI PLL IOUT QOUT DMIP FDIN VPOS PRUP GAIN CHARACTERIZATION BOARD BIAS TPC 11. Quadrature Accuracy Test Set

REV. 0–10– AD61009 AD61009 FDIN QOUT IOUT FLTR VPS1 COM1 PRUP LOIP IFOP DMIP VPS2RFLO RFHI GREF MXOP VMID IFHI IFLO GAIN COM2 0.1/H9262F C13 C15 0.1/H9262F IOUT QOUT IFOP GAIN DMIP 0.1/H9262F 10nFR1 1k/H9024 316/H9024 0.1/H9262F 0.1/H9262F 1nF 4.99k/H9024 R10 51.1/H9024 C11 10nF 51.1/H9024 C10 1nF 51.1/H9024 1nF R14 54.9/H9024 R13 301/H9024 332/H9024 0.1/H9262F VPOS GND FDIN PRUP LOIP RFHI MXOP IFHI 0/H9024 R12 C16 1nF 1nF 0.1/H9262F NOTE: CONNECTIONS MARKED * ARE DC COUPLED. 51.1/H9024 TPC 12. Characterization Board

REV. 0 –11– RF FREQUENCY – MHz SSB NF – dB 50 25070 90 110 130 150 170 190 210 230 VPOS = 5V, IF = 20MHz VPOS = 3V, IF = 20MHz VPOS = 5V, IF = 10MHz VPOS = 3V, IF = 10MHz TPC 13. Mixer Noise Figure vs. Frequency 4500 3000 5002500 2500 2000 3500 4000 FREQUENCY – MHz 1500 1000 500 50 100 150 200 300 350 400 450 RESISTANCE – /H9024 R SHUNT COMPONENT C SHUNT COMPONENT 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 CAPACITANCE – pF TPC 14. Mixer Input Impedance vs. Frequency, VPOS = 3 V, V GAIN = 0.8 V –20 6003000 RADIO FREQUENCY – MHz –15 –10 50 100 150 200 250 350 400 450 500 550 CONVERSION GAIN – dB VGAIN = 0.00V VGAIN = 0.54V VGAIN = 1.08VVGAIN = 1.62V VGAIN = 2.16V TPC 15. Mixer Conversion Gain vs. Frequency, T = 25°C, VPOS = 2.7 V, VREF = 1.35 V, IF = 10.7 MHz 1000.1 INTERMEDIATE FREQUENCY – MHz –10 11 0 CONVERSION GAIN – dB VGAIN = 0.3V VGAIN = 0.6V VGAIN = 1.8V VGAIN = 1.2V VGAIN = 2.4V TPC 16. Mixer Conversion Gain vs. IF, T = 25 °C, VPOS = 3 V, VREF = 1.5 V 130–50 TEMPERATURE – /H11543C –20 –10 –30 –10 10 20 30 40 50 60 80 90 100 110 120–40 –20 0 GAIN – dB CUBIC FIT OF CONV_GAIN (TEMP) CUBIC FIT OF IF_GAIN (TEMP) IF AMP GAIN MIXER CG TPC 17. Mixer Conversion Gain and IF Amplifier Gain vs. Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF =

10.7 MHz, RF = 250 MHz

62.4 SUPPLY – Volts 4.8 GAIN – dB CUBIC FIT OF CONV_GAIN (VPOS) CUBIC FIT OF IF_GAIN (VPOS) IF AMP GAIN MIXER CG TPC 18. Mixer Conversion Gain and IF Amplifier Gain vs. Supply Voltage, T = 25°C, VGAIN = 0.3 V, VREF = 1.5 V, IF =

REV. 0–12– AD61009 1000.1 INTERMEDIATE FREQUENCY – MHz –10 11 0 IF AMPLIFIER GAIN – dB VGAIN = 0.3V VGAIN = 0.6V VGAIN = 1.8V VGAIN = 1.2V VGAIN = 2.4V TPC 19. IF Amplifier Gain vs. Frequency, T = 25°C, VPOS = 3 V, VREF = 1.5 V GAIN VOLTAGE – Volts –10 ERROR – dB IF AMP MIXER TPC 20. Gain Error vs. Gain Control Voltage, Representative Part 996.200/H9262s 1.00870ms 1.02120ms TRIGGER ON EXTERNAL AT POS. EDGE AT 134.0mV TIMEBASE MEMORY 1 TIMEBASE MEMORY 2 TIMEBASE DELTA T START = 2.5/H9262s/DIV = 100.0mV/DIV = 2.50/H9262s/DIV = 20.00mV/DIV = 2.50/H9262s/DIV = 16.5199/H9262s = 1.00048ms DELAY OFFSET DELAY OFFSET DELAY STOP = 1.00870ms = 127.3mV = 1.00870ms = 155.2mV = 1.00870ms = 1.01700ms TPC 21. PLL Acquisition Time 1.00E+071.00E+02 –110.00 –100.00 –130.00 –120.00 CARRIER FREQUENCY OFFSET, f(fm) – Hz –140.00 –150.00 1.00E+03 1.00E+05 –90.00 1.00E+04 1.00E+06 PHASE NOISE – dBc TPC 22. PLL Phase Noise L (F) vs. Frequency, VPOS = 3 V, C3 = 0.1 µF, IF = 10.7 MHz 1000.1 PLL FREQUENCY – MHz 1.5 11 0 FLTR PIN VOLTAGE – Volts 2.5 TPC 23. PLL Loop Voltage at FLTR (KVCO) vs. Frequency 9485 QUADRATURE ANGLE – Degrees 9186 87 88 89 90 92 93 COUNT TPC 24. Demodulator Quadrature Angle, Histogram, T = 25°C, VPOS = 3 V, IF = 10.7 MHz

REV. 0 –13– IQ GAIN BALANCE – dB COUNT –101 2 TPC 25. Demodulator Gain Balance, Histogram, T = 25°C, VPOS = 3 V, IF = 10.7 MHz BASEBAND FREQUENCY – MHz 0.2 0.4 0.6 0.8 IGAIN – dB QUADRATIC FIT OF I_GAIN_CORR (IFF) I_GAIN_CORR TPC 26. Demodulator Gain vs. Frequency –50 TEMPERATURE – /H11543C –40 –30 –20 –10 0 1 02 03 04 05 0 IGAIN – dB CUBIC FIT OF I_GAIN_CORR (TEMP) I_GAIN_CORR 60 70 80 90 100 110 120 130 TPC 27. Demodulator Gain vs. Temperature 2.5 SUPPLY – Volts 3.5 4 4.5 IGAIN – dB CUBIC FIT OF I_GAIN_CORR (TEMP) I_GAIN_CORR 5 5.5 6 TPC 28. Demodulator Gain vs. Supply Voltage DEMODULATOR GAIN – dB 17.2 COUNT 18.6 18.8 TPC 29. Demodulator Gain Histogram, T = 25°C, VPOS = 3 V, IF = 10.7 MHz 40.2127ms 40.2377ms 40.2627ms TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV TIMEBASE MEMORY 1 TIMEBASE MEMORY 2 TIMEBASE DELTA T START = 500/H9262s/DIV = 100.0mV/DIV = 5.00/H9262s/DIV = 60.00mV/DIV = 5.00/H9262s/DIV = 15.7990/H9262s = 40.2327ms DELAY OFFSET DELAY OFFSET DELAY STOP = 40.2377ms = 154.0mV = 40.2377ms = 209.0mV = 40.2377ms = 40.2485ms TPC 30. Power-Up Response Time to PLL Stable

signal conversion with a bandwidth of approximately 45 MHz. Its output at pin MXOP is in the form of a single-ended current. O, the conversion gain will be lowered by 10 log 10(165/ZO). Table I lists resistor values. Figure 3. Suggested IF Filter Matching Netwo rk. The

6.5 MHz 1000 Ω 215 Ω 787 Ω 1000 Ω

10.7 MHz 330 Ω 330 Ω 0 Ω 330 Ω

IF amplifier’s linear range. 20 dB, and it also provides differential to single-ended conversion. which will normally be connected to VMID. Figure 4. Simplified Schematic of the IF Interface are no longer removed by the onboard low-pass filters).

Figure 5. Input and Output Matching of the Optional for power supply voltages from 3 V to 5.5 V. requiring the reference voltage to have high absolute accuracy. Both demodulators (I and Q) receive their inputs at pin DMIP.

2 MHz, two-pole low-pass filter, producing single-sided outputs

Maximum gain occurs for gain control voltage = 0 V.

signal coupling, particularly from IFOP to RFHI or IFHI or both. unwanted local EM signals may have an effect on the performance. emanations out of the interior. capacitor with a ferrite bead on both inside and outside leads. to-noise ratio and lowest intermodulation distortion. how these vary when GREF is connected to a 1.23 V refere nce. Figure 10. Gain Distribution for GREF = 1.5 V

01 V2 V

Figure 11. Gain Distribution for GREF = 1.23 V Figure 9. Signal Levels for Minimum and Maximum Gain

tions when the PRUP signal has a rise time slower than 35 µs. operate normally when reset. C = 1.5 nF. This circuit is shown in Figure 12. Figure 12. Proper Configuration of AD61009 PRUP Signal supply and the PRUP pin as shown in Figure 12. tion Board’s I/O Connectors and their functions.

Figure 13. Evaluation Board

Figure 14. Evaluation Board Layout

REV. 0–22– AD61009 Table III. AD61009 Evaluation Board Input and Output Connections Reference Connector Approximate Designation Type Description Coupling Signal Level Comments J1 SMA Frequency DC ±400 mV This pin needs to be biased at VMID Detector Input and ac coupled when driven by an external signal generator. J2 SMA Power Up DC CMOS Logic Tied to Positive Supply by Jumper J10. Level Input J3 SMA LO Input AC –16 dBm Input is terminated in 50 Ω. (±50 mV) J4 SMA RF Input AC –15 dBm max Input is terminated in 50 Ω. (±54 mV) J5 SMA MGC Input DC 0.4 V to 2.0 V Jumper is set for Manual Gain Control (3 V Supply) Input; See Table I for Control Voltage (GREF = VMID) Values. J6 SMA IF Output AC NA This signal level depends on the AD61009’s gain setting. J7 SMA Q Output AC NA This signal level depends on the AD61009’s gain setting. J8 SMA I Output AC NA This signal level depends on the AD61009’s gain setting. J9 Jumper Ties GREF NA NA Sets gain-control Scale Factor (SF); to VMID SF = 75/VMID in dB/V, where VMID = VPOS/2. J10 Jumper Ties Power-Up NA NA Remove to test Power-Up/-Down. to Positive Supply T1 Terminal Pin Power Supply DC DC 2.85 V to 5.5 V Positive Input Draws 8.5 mA at midgain connection. (VPS1, VPS2) T2 Terminal Pin Power Supply DC 0 V Return (GND)

Figure 15. Evaluation Board Test Setup terminated bandpass filter is used.

REV. 0–24– AD61009 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic SSOP (RS-20) 20 11 101 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PIN 1 SEATING PLANE 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) BSC 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) PRINTED IN U.S.A.