AD604ARZ-RL

AD604_08 AD | Alldatasheet

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Dual, Ultralow Noise Variable Gain Amplifier AD604 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.

FEATURES

Ultralow input noise at maximum gain 0.80 nV/√Hz, 3.0 pA/√Hz 2 independent linear-in-dB channels Absolute gain range per channel programmable 0 dB to 48 dB (preamplifier gain = 14 dB) through 6 dB to 54 dB (preamplifier gain = 20 dB) ±1.0 dB gain accuracy Bandwidth: 40 MHz (−3 dB) Input resistance: 300 kΩ Variable gain scaling: 20 dB/V through 40 dB/V Stable gain with temperature and supply variations Single-ended unipolar gain control Power shutdown at lower end of gain control Drive ADCs directly

APPLICATIONS

Ultrasound and sonar time gain controls High performance AGC systems Signal measurement FUNCTIONAL BLOCK DIAGRAM OUT VOCM PAO PAI +DSX–DSX VGN VREF AFA FIXED GAIN AMPLIFIER 34.4dBPRECISION PASSIVE INPUT ATTENUATOR PROGRAMMABLE ULTRALOW NOISE PREAMPLIFIER G = 14dB TO 20dB DIFFERENTIAL ATTENUATOR R-1.5R LADDER NETWORK 0dB TO –48.4dB GAIN CONTROL AND SCALING 00540-001 Figure 1. GENERAL DESCRIPTION The AD604 is an ultralow noise, very accurate, dual-channel, linear-in-dB variable gain amplifier (VGA) optimized for time- based variable gain control in ultrasound applications; however, it supports any application requiring low noise, wide bandwidth, variable gain control. Each channel of the AD604 provides a 300 kΩ input resistance and unipolar gain control for ease of use. User-determined gain ranges, gain scaling (dB/V), and dc level shifting of output further optimize performance. Each channel of the AD604 uses a high performance preamplifier that provides an input-referred noise voltage of 0.8 nV/√Hz. The very accurate linear-in-dB response of the AD604 is achieved with the differential input exponential amplifier (DSX-AMP) architecture. Each of the DSX-AMPs comprises a variable attenuator of 0 dB to 48.36 dB followed by a high speed fixed gain amplifier. The attenuator is a 7-stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB and 48.36 dB for the ladder network. The equation for the linear-in-dB gain response is G (dB) = (Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB) Preamplifier gains between 5 and 10 (14 dB and 20 dB) provide overall gain ranges per channel of 0 dB through 48 dB and 6 dB through 54 dB. The two channels of the AD604 can be cascaded to provide greater levels of gain range by bypassing the preamplifier of the second channel. However, in multiple channel systems, cascading the AD604 with other devices in the AD60x VGA family that do not include a preamplifier may provide a more efficient solution. The AD604 provides access to the output of the preamplifier, allowing for external filtering between the preamplifier and the differential attenuator stage. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V . The gain scales linearly-in- dB with control voltages of 0.4 V to 2.4 V with the 20 dB/V scale. Below and above this gain control range, the gain begins to deviate from the ideal linear-in-dB control law. The gain control region below 0.1 V is not used for gain control. When the gain control voltage is <50 mV , the amplifier channel is powered down to 1.9 mA. The AD604 is available in 24-lead SSOP , SOIC, and PDIP packages and is guaranteed for operation over the −40°C to +85°C temperature range.

Rev. D | Page 2 of 32 TABLE OF CONTENTS An Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain Ultralow Noise, Differential Input-Differential Output VGA Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40

REVISION HISTORY

1/08—Rev. C to Rev. D Changes to An Ultralow Noise AGC Amplifier with 82 dB to 3/07—Rev. B to Rev. C 12/06—Rev. A to Rev. B 1/04—Rev. 0 to Rev. A 10/96—Revision 0: Initial Version

Rev. D | Page 3 of 32 SPECIFICATIONS Each amplifier channel at TA = 25°C, VS = ±5 V , RS = 50 Ω, RL = 500 Ω, CL = 5 pF, VREF = 2.50 V (scaling = 20 dB/V), 0 dB to 48 dB gain range (preamplifier gain = 14 dB), VOCM = 2.5 V , C1 and C2 = 0.1 μF (see Figure 37), unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Preamplifier Input Resistance 300 kΩ Input Capacitance 8.5 pF Input Bias Current −27 mA Peak Input Voltage Preamplifier gain = 14 dB ±400 mV Preamplifier gain = 20 dB ±200 mV Input Voltage Noise VGN = 2.9 V, RS = 0 Ω Preamplifier gain = 14 dB 0.8 nV/√Hz Preamplifier gain = 20 dB 0.73 nV/√Hz Input Current Noise Independent of gain 3.0 pA/√Hz Noise Figure RS = 50 Ω, f = 10 MHz, VGN = 2.9 V 2.3 dB RS = 200 Ω, f = 10 MHz, VGN = 2.9 V 1.1 dB DSX Input Resistance 175 Ω Input Capacitance 3.0 pF Peak Input Voltage 2.5 ± 2 V Input Voltage Noise VGN = 2.9 V 1.8 nV/√Hz Input Current Noise VGN = 2.9 V 2.7 pA/√Hz Noise Figure RS = 50 Ω, f = 10 MHz, VGN = 2.9 V 8.4 dB RS = 200 Ω, f = 10 MHz, VGN = 2.9 V 12 dB Common-Mode Rejection Ratio f = 1 MHz, VGN = 2.65 V −20 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth Constant with gain 40 MHz Slew Rate VGN = 1.5 V, output = 1 V step 170 V/μs Output Signal Range RL ≥ 500 Ω 2.5 ± 1.5 V Output Impedance f = 10 MHz 2 Ω Output Short-Circuit Current ±40 mA Harmonic Distortion VGN = 1 V, VOUT = 1 V p-p HD2 f = 1 MHz −54 dBc HD3 f = 1 MHz −67 dBc HD2 f = 10 MHz −43 dBc HD3 f = 10 MHz −48 dBc Two-Tone Intermodulation Distortion (IMD) VGN = 2.9 V, VOUT = 1 V p-p f = 1 MHz −74 dBc f = 10 MHz −71 dBc Third-Order Intercept f = 10 MHz, VGN = 2.65 V, VOUT = 1 V p-p, input referred −12.5 dBm 1 dB Compression Point f = 1 MHz, VGN = 2.9 V, output referred 15 dBm Channel-to-Channel Crosstalk VOUT = 1 V p-p, f = 1 MHz, Channel 1: VGN = 2.65 V, inputs shorted, Channel 2: VGN = 1.5 V (mid gain) −30 dB Group Delay Variation 1 MHz < f < 10 MHz, full gain range ±2 ns VOCM Input Resistance 45 kΩ

Rev. D | Page 4 of 32 Parameter Conditions Min Typ Max Unit ACCURACY Absolute Gain Error 0 dB to 3 dB 0.25 V < VGN < 0.400 V −1.2 +0.75 +3 dB Gain Scaling Error 0.400 V < VGN < 2.400 V ±0.25 dB/V Output Offset Voltage VREF = 2.500 V, VOCM = 2.500 V −50 ±30 +50 mV Output Offset Variation VREF = 2.500 V, VOCM = 2.500 V 30 50 mV GAIN CONTROL INTERFACE Gain Scaling Factor VREF = 2.5 V, 0.4 V < VGN < 2.4 V 19 20 21 dB/V VREF = 1.67 V 30 dB/V Gain Range Preamplifier gain = 14 dB 0 to 48 dB Preamplifier gain = 20 dB 6 to 54 dB Input Voltage (VGN) Range 20 dB/V, VREF = 2.5 V 0.1 to 2.9 V Input Bias Current −0.4 μA Input Resistance 2 MΩ Response Time 48 dB gain change 0.2 μs VREF Input Resistance 10 kΩ POWER SUPPLY Specified Operating Range One complete channel ±5 V One DSX only 5 V Power Dissipation One complete channel 220 mW One DSX only 95 mW Quiescent Supply Current VPOS, one complete channel 32 36 mA VPOS, one DSX only 19 23 mA VNEG, one preamplifier only −15 −12 mA Powered Down VPOS, VGN < 50 mV, one channel 1.9 3.0 mA VNEG, VGN < 50 mV, one channel −150 μA Power-Up Response Time 48 dB gain change, VOUT = 2 V p-p 0.6 μs Power-Down Response Time 0.4 μs

Rev. D | Page 5 of 32 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter1, 2 Rating Supply Voltage ±VS Pin 17 to Pin 20 (with Pin 16, Pin 22 = 0 V) ±6.5 V Input Voltages Pin 1, Pin 2, Pin 11, Pin 12 VPOS/2 ± 2 V continuous Pin 4, Pin 9 ±2 V Pin 5, Pin 8 VPOS, VNEG Pin 6, Pin 7, Pin 13, Pin 14, Pin 23, Pin 24 VPOS, 0 V Internal Power Dissipation PDIP (N) 2.2 W SOIC (RW) 1.7 W SSOP (RS) 1.1 W Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering 60 sec 300°C θJA3 AD604AN 105°C/W AD604AR 73°C/W AD604ARS 112°C/W θJC3 AD604AN 35°C/W AD604AR 38°C/W AD604ARS 34°C/W

1 Pin 1, Pin 2, Pin 11 to Pin 14, Pin 23, and Pin 24 are part of a single-supply

circuit. The part is likely to suffer damage if any of these pins are accidentally connected to VN. 2 When driven from an external low impedance source. 3 Using MIL-STD-883 test method G43-87 with a 1S (2-layer) test board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 –DSX1 Channel 1 Negative Signal Input to DSX1. 2 +DSX1 Channel 1 Positive Signal Input to DSX1. 3 PAO1 Channel 1 Preamplifier Output. 4 FBK1 Channel 1 Preamplifier Feedback Pin. 5 PAI1 Channel 1 Preamplifier Positive Input. 6 COM1 Channel 1 Signal Ground. When connected to positive supply, Preamplifier 1 shuts down. 7 COM2 Channel 2 Signal Ground. When connected to positive supply, Preamplifier 2 shuts down. 8 PAI2 Channel 2 Preamplifier Positive Input. 9 FBK2 Channel 2 Preamplifier Feedback Pin. 10 PAO2 Channel 2 Preamplifier Output. 11 +DSX2 Channel 2 Positive Signal Input to DSX2. 12 –DSX2 Channel 2 Negative Signal Input to DSX2. 13 VGN2 Channel 2 Gain Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. 14 VOCM Input to this pin defines the common mode of the output at OUT1 and OUT2. 15 OUT2 Channel 2 Signal Output. 22 OUT1 Channel 1 Signal Output. 23 VREF Input to this pin sets gain scaling for both channels to 2.5 V = 20 dB/V and 1.67 V = 30 dB/V. 24 VGN1 Channel 1 Gain Control Input and Power-Down Pin. If grounded, the device is off; otherwise, positive voltage increases gain.

3 CURVES

Figure 3. Gain vs. VGN for Three Temperatures Figure 4. Gain vs. VGN for Different Preamplfier Gains Figure 5. Gain vs. VGN for Different Gain Scalings Figure 6. Gain Scaling vs. VREF Figure 7. Gain Error vs. VGN Figure 8. Gain Error vs. VGN at Different Frequencies

• A precision passive attenuator (differential ladder).
• A gain control block.
• A VOCM buffer with supply splitting resistors (R3 and R4).
• An active feedback amplifier (AFA) with gain setting resistors (R1 and R2). (To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The AD830 is a practical implementation of the idea.) The preamplifier is powered by a ±5 V supply, while the DSX uses a single +5 V supply. The linear-in-dB gain response of the AD604 can generally be described by G (dB) = Gain Scaling (dB/V) × Gain Control (V) + (Preamp Gain (dB) − 19 dB) (1) Each channel provides between 0 dB to 48.4 dB through 6 dB to 54.4 dB of gain, depending on the user-determined preamplifier gain. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain of the preamplifier is typically either 14 dB or 20 dB but can be set to intermediate values by a single external resistor (see the Preamplifier section for details). The gain of the DSX can vary from −14 dB to +34.4 dB, as is determined by the gain control voltage (VGN). The VREF input establishes the gain scaling; the useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V , respectively. For example, if the preamp gain is set to 14 dB and VREF is set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation simplifies to G (dB) = 20 (dB/V) × VGN (V) – 5 dB The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control voltage range of 0.1 V to 2.9 V . Maximum gain can be achieved at a VGN of 2.9 V . The inputs VREF and VOCM are common to both channels. They are decoupled to ground, minimizing inter-channel crosstalk. For the highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode, the gain scaling is determined by the midpoint between VPOS and GND; therefore, care should be taken to control the supply voltage to 5 V . The input resistance looking into the VREF pin is 10 kΩ ± 20%. The DSX portion of the AD604 is a single-supply circuit, and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. The VOCM pin only needs an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 V , GND); however, if the dc level of the output is important to the user (see the Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40 MSPS ADC section for the AD9050 example), VOCM can be specifically set. The input resistance looking into the VOCM pin is 45 kΩ ± 20%. FBK VGN PAI –DSX EXT. COM VPOS VOCM OUT 175Ω Ao EXT. 175Ω 200kΩ 200kΩ VREF DISTRIBUTED GM GAIN CONTROL DIFFERENTIAL ATTENUATOR 820Ω 20Ω +DSXPAO 40Ω 32Ω 00540-037

Figure 37. Simplified Block Diagram of a Single Channel of the AD604

or ±200 mV for the 20 dB gain configuration. accurate because they are set by the ratio of the on-chip resistors. where it is assumed that REXT is exact. Figure 38. Preamplifier Gain Programmability of 20 dB, the bandwidth is reduced by half to 65 MHz. Figure 38. Note that the gain for an REXT of 40 Ω should be 40 MHz and is independent of gain. handled to maintain performance even at large signal levels.

10 GAIN (dB)

Figure 39. AC Response for Preamplifier Gains of 14 dB, 17.5 dB, and 20 dB any offset that would otherwise be introduced by the preamplifier. reference) seriously degrades gain accuracy and noise performance. node should be as short as possible. contributes 0.33 nV/√Hz to the total input referred voltage noise.

ground to the dc value established by VOCM (nominal 2.5 V). ladder of the DSX, the −3 dB high-pass corner is 9.1 kHz. a high-pass filter with −3 dB corner frequency at about 3.2 kHz. the low frequency noise in the system. 20 dB/V scale and 0.2 V to 1.2 V for the 40 dB/V scale. Figure 42. Ideal Gain Curves vs. VGN REF can be calculated as shown in Equation 7. on or off is less than 1 μs. depending on the gain-control voltage. input voltage to G1 times gm1 (the transconductance of G1).

2 R 1 R

VATTEN is the effective voltage sensed on the attenuator. The overall gain is thus 52.5 (34.4 dB).

Rev. D | Page 17 of 32 The AFA offers additional features:

• The ability to invert the signal by switching the positive and negative inputs to the ladder network.
• The possibility of using the DSX1 input as a second signal input.
• Fully differential high impedance inputs when both preamplifiers are used with one DSX (the other DSX could still be used alone).
• Independent control of the DSX common-mode voltage. Under normal operating conditions, it is best to connect a decoupling capacitor to VOCM, in which case, the common- mode voltage of the DSX is half the supply voltage; which allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew rate of the VOCM buffer. If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again this is done for level shifting and to eliminate any dc offsets contributed by the DSX (see the AC Coupling section).

a 50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm). network or by transformer coupling of the input signal. Figure 45. Cascaded Gain vs. VGN Figure 46. Cascaded Gain Error vs. VGN signal amplitude is ±400 mV . Figure 47. Control Voltage vs. Input Power of Circuit in Figure 44 bead, combined with R2 and C6, forms a 1 MHz low-pass filter.

1 MHz are not significantly affected. the circuit in Figure 48; note that the AGC threshold is at −95 dBm. −80 mV to the VSET connector. Figure 48. Modifications of AGC Amplifier to Create 96 dB of Gain Range

1.5 CONTROL VOLTAGE (V)

Figure 49. Control Voltage vs. Input Power of Circuit in Figure 48 ALL SUPPLY PINS ARE DECOUPLED AS SHOWN. Figure 50. Ultralow Noise, Differential Input-Differential Output VGA scope photo when reading the vertical scale as 200 mV/div.

1. THE OUTPUT AFTER 10× ATTENUATER FORMED

BY 453Ω TOGETHER WITH 50Ω OF 7A24 PLUG-IN. Figure 51. Output of VGA in Figure 50 for VGN = 1 V

To channel cascade the two channels, insert a jumper in JP13. signal source at test loop VGN1 or VGN2. gains are accurate due to close matching of thin film resistors. inherent tolerance of absolute accuracy. to accommodate other output impedances. Table 4. Trimmer Functions Table 5. Jumpers

1 Connects R1 gain adjust wiper to VGN1

2 Connects R2 reference voltage trimmer to VREF input

3 Connects common-mode voltage trimmer to VOCM

4 Connects VGN2 to R4 Channel 2 gain trimmer or to VGN1 or common gain adjustment

5 Connects –DSX1 to CH1 VGA IN (−) or to ground

7 When open, the Preamp 1 Gain is 20 dB; Preamp Gain 1 is 14 dB when a shunt is installed

8 Shunt in left position disables Preamp 1; shunt in rightmost position enables Preamp 1

9 Shunt in left position disables Preamp 2; shunt in rightmost position enables Preamp 2

12 When open, the Preamp 2 gain is 20 dB; Preamp 2 gain is 14 dB when a shunt is installed

13 Cascades DSX2 with DSX 1 when a jumper is inserted

15 Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2

16 Connects –DSX2 to CH2 VGA IN (−) or to ground

1. PARTS IN GRAY ARE NOT INSTALLED.

Figure 61. Evaluation Board Schematic Table 6. Bill of Materials

14 Test Loop Purple +DSX1, +DSX2, −DSX1, −DSX2, OUT1, OUT2, PAI1,

2 Capacitor Tantalum 10 μF , 10 V, A size C1, C3 Nichicon F931A106MAA

2 Capacitor SM, 1000 pF , 50 V, 0805 C5, C12 Panasonic ECU-V1H102KBN

8 Connector SMA FEM PC Mount, RA J1, J2, J3, J4, J5, J6, J7, J8 Amphenol 901-143-6RFX

4 Trimmer 10 kΩ, 1/4" SM R1, R2, R3, R4 Bourns 3361P-1-103G

1 Integrated

40 MHz dual low

10 Jumper Mini jumper Install in headers at JP1, JP2, JP3, JP4 lower,

0.05 MIN

0.65 BSC

2.00 MAX

Figure 64. 24-Lead Shrink Small Outline Package [SSOP]

Rev. D | Page 30 of 32 NOTES

Rev. D | Page 31 of 32 NOTES

Rev. D | Page 32 of 32 NOTES ©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00540-0-1/08(D)