AD603-EB

AD603 AD | Alldatasheet

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD603*

FEATURES

“Linear in dB” Gain Control Pin Programmable Gain Ranges –11 dB to +31 dB with 90 MHz Bandwidth +9 dB to +51 dB with 9 MHz Bandwidth Any Intermediate Range, e.g., –1 dB to +41 dB with

30 MHz Bandwidth

Bandwidth Independent of Variable Gain 1.3 nV/ ÖHz Input Noise Spectral Density 60.5 dB Typical Gain Accuracy MIL-STD-883 Compliant and DESC Versions Available

APPLICATIONS

Low Noise, 90 MHz Variable-Gain Amplifier PRODUCT DESCRIPTION The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin selectable gains of –11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to +51 dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is only 1.3 nV/ÖHz and power consumption is 125 mW at the recommended – 5 V supplies. The decibel gain is “linear in dB,” accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 M W ), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain-control voltage of only FUNCTIONAL BLOCK DIAGRAM SCALING REFERENCE VG GAIN CONTROL INTERFACE AD603 PRECISION PASSIVE INPUT ATTENUATOR FIXED GAIN AMPLIFIER *NORMAL VALUESR = 2R LADDER NETWORK VPOS VNEG GPOS GNEG VINP COMM RRRRRRR 2R 2R 2R 2R 2R 2R R 20V* 694V* 6.44kV* VOUT FDBK 1 V to span the central 40 dB of the gain range. An over- and under-range of 1 dB is provided whatever the selected range. The gain-control response time is less than 1 ms for a 40 dB change. The differential gain-control interface allows the use of either differential or single-ended positive or negative control voltages. Several of these amplifiers may be cascaded and their gain-con- trol gains offset to optimize the system S/N ratio. The AD603 can drive a load impedance as low as 100 W with low distortion. For a 500 W load in shunt with 5 pF, the total harmonic distortion for a – 1 V sinusoidal output at 10 MHz is typically –60 dBc. The peak specified output is – 2.5 V mini- mum into a 500 W load, or – 1 V into a 100 W load. The AD603 uses a proprietary circuit topology—the X-AMP™. The X-AMP comprises a variable attenuator of 0 dB to –42.14 dB followed by a fixed-gain amplifier. Because of the attenuator, the amplifier never has to cope with large inputs and can use negative feedback to define its (fixed) gain and dynamic performance. The attenuator has an input resistance of 100 W , laser trimmed to – 3%, and comprises a seven-stage R-2R ladder network, resulting in an attenuation between tap points of 6.021 dB. A proprietary interpolation technique provides a continuous gain-control function which is linear in dB. The AD603A is specified for operation from –40 °C to +85°C and is available in both 8-lead SOIC (R) and 8-lead ceramic DIP (Q). The AD603S is specified for operation from –55 °C to +125°C and is available in an 8-lead ceramic DIP (Q). The AD603 is also available under DESC SMD 5962-94572. *Patented. X-AMP is a trademark of Analog Devices, Inc. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD603–SPECIFICATIONS REV. C–2– Model AD603 Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Pins 3 to 4 97 100 103 W Input Capacitance 2p F Input Noise Spectral Density 1 Input Short Circuited 1.3 nV/ ÖHz Noise Figure f = 10 MHz, Gain = max, R S = 10 W 8.8 dB 1 dB Compression Point f = 10 MHz, Gain = max, R S = 10 W –11 dBm Peak Input Voltage – 1.4 – 2V OUTPUT CHARACTERISTICS –3 dB Bandwidth V OUT = 100 mV rms 90 MHz Slew Rate R L ‡ 500 W 275 V/ ms Peak Output2 RL ‡ 500 W– 2.5 – 3.0 V Output Impedance f £ 10 MHz 2 W Output Short-Circuit Current 50 mA Group Delay Change vs. Gain f = 3 MHz; Full Gain Range – 2n s Group Delay Change vs. Frequency V G = 0 V; f = 1 MHz to 10 MHz – 2n s Differential Gain 0.2 % Differential Phase 0.2 Degree Total Harmonic Distortion f = 10 MHz, V OUT = 1 V rms –60 dBc 3rd Order Intercept f = 40 MHz, Gain = max, R S = 50 W 15 dBm ACCURACY Gain Accuracy –500 mV £ VG £ +500 mV – 0.5 61 dB TMIN to TMAX – 1.5 dB Output Offset Voltage 3 VG = 0 V 20 mV TMIN to TMAX 30 mV Output Offset Variation vs. V G –500 mV £ VG £ +500 mV 20 mV TMIN to TMAX 30 mV GAIN CONTROL INTERFACE Gain Scaling Factor 39.4 40 40.6 dB/V TMIN to TMAX 38 42 dB/V GNEG, GPOS Voltage Range 4 –1.2 +2.0 V Input Bias Current 200 nA Input Offset Current 10 nA Differential Input Resistance Pins 1 to 2 50 M W Response Rate Full 40 dB Gain Change 40 dB/ ms POWER SUPPLY Specified Operating Range – 4.75 – 6.3 V Quiescent Current 12.5 17 mA TMIN to TMAX 20 mA NOTES 1Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This fig ure includes the effects of both voltage and current noise sources. 2Using resistive loads of 500 W or greater, or with the addition of a 1 k W pull-down resistor when driving lower loads. 3The dc gain of the main amplifier in the AD603 is ·35.7; thus, an input offset of 100 mV becomes a 3.57 mV output offset. 4GNEG and GPOS, gain control, voltage range is guaranteed to be within the range of –V S + 4.2 V to +VS – 3.4 V over the full temperature range of –40 °C to +85°C. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality le vels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice. (@ TA = +258C, VS = 65 V, –500 mV £ VG £ +500 mV, GNEG = 0 V, –10 dB to +30 dB Gain Range, RL = 500 V, and CL = 5 pF, unless otherwise noted.)

REV. C –3– ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Thermal Characteristics: 8-Lead SOIC Package: qJA = 155°C/W, qJC = 33°C/W 8-Lead Ceramic Package: qJA = 140°C/W, qJC = 15°C/W PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description Pin 1 GPOS Gain-Control Input “HI” (Positive Voltage Increases Gain) Pin 2 GNEG Gain-Control Input “LO” (Negative Voltage Increases Gain) Pin 3 VINP Amplifier Input Pin 4 COMM Amplifier Ground Pin 5 FDBK Connection to Feedback Network Pin 6 VNEG Negative Supply Input Pin 7 VOUT Amplifier Output Pin 8 VPOS Positive Supply Input CONNECTION DIAGRAMS 8-Lead Plastic SOIC (R) Package 8-Lead Ceramic DIP (Q) Package TOP VIEW (Not to Scale) GPOS GNEG VINP VPOS VOUT VNEG FDBKCOMM AD603 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD603 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package Package Part Number Range Description Option AD603AR –40 °C to +85°C 8-Lead SOIC SO-8 AD603AQ –40 °C to +85°C 8-Lead Ceramic DIP Q-8 AD603SQ/883B* –55°C to +125°C 8-Lead Ceramic DIP Q-8 AD603-EB Evaluation Board AD603ACHIPS –40 °C to +85°C Die AD603AR-REEL –40 °C to +85°C 13" Reel SO-8 AD603AR-REEL7 –40 °C to +85°C 7" Reel SO-8 *Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.

maximum-bandwidth mode (Pin 5 and Pin 7 strapped).

100 W – 3%, which ensures accurate operation (gain and HP

this connection will reduce the gain accuracy. control interface are discussed later. law, by about – 0.2 dB peak (see, for example, Figure 16).

41.7 W (one third of 125 W ), which exhibits a Johnson noise-

match a high impedance source to the low impedance AD603. source impedance quickly diminishes. the fixed gain of ·35.8 raises the output NSD to 46.5 nV/ ÖHz. Figure 1. Simplified Block Diagram of the AD603

REV. C–10– AD603 output signal. The automatic gain control voltage, V AGC, is the time-integral of this error current. In order for V AGC (and thus the gain) to remain insensitive to short-term amplitude fluctuations in the output signal, the rectified current in Q1 must, on average, exactly balance the current in Q2. If the output of A2 is too small to do this, VAGC will increase, causing the gain to increase, until Q1 conducts sufficiently. Consider the case where R8 is zero and the output voltage V OUT is a square wave at, say, 455 kHz, which is well above the corner frequency of the control loop. During the time VOUT is negative with respect to the base voltage of Q1, Q1 conducts; when V OUT is positive, it is cut off. Since the average collector current of Q1 is forced to be 300 mA, and the square wave has a duty-cycle of 1:1, Q1’s collector current when conducting must be 600 mA. With R8 omitted, the peak amplitude of VOUT is forced to be just the V BE of Q1 at 600 mA, typically about 700 mV, or 2 V BE peak-to-peak. This voltage, hence the amplitude at which the output stabilizes, has a strong negative temperature coefficient (TC), typically –1.7 mV/°C. Although this may not be troublesome in some applications, the correct value of R8 will render the output stable with temperature. To understand this, first note that the current in Q2 is made to be proportional to absolute temperature (PTAT). For the moment, continue to assume that the signal is a square wave. When Q1 is conducting, V OUT is now the sum of V BE and a voltage that is PTAT and which can be chosen to have an equal but opposite TC to that of the VBE. This is actually nothing more than an application of the “bandgap voltage reference” principle. When R8 is chosen such that the sum of the voltage across it and the VBE of Q1 is close to the bandgap voltage of about 1.2 V, VOUT will be stable over a wide range of tempe ratures, provided, of course, that Q1 and Q2 share the same thermal environment. Since the average emitter current is 600 mA during each half- cycle of the square wave a resistor of 833 W would add a PTAT voltage of 500 mV at 300 K, increasing by 1.66 mV/ °C. In prac- tice, the optimum value will depend on the type of transistor used and, to a lesser extent, on the waveform for which the temperature stability is to be optimized; for the inexpensive 2N3904/2N306 pair and sine wave signals, the recommended value is 806 W . This resistor also serves to lower the peak current in Q1 when more typical signals (usually, sinusoidal) are involved, and the 1.8 kHz LP filter it forms with C AV helps to minimize distortion due to ripple in VAGC. Note that the output amplitude under sine wave conditions will be higher than for a square wave, since the average value of the current for an ideal rectifier would be 0.637 times as large, causing the output amplitude to be nonideal rectifier results in the sine wave output being regulated to about 1.4 V rms, or 3.6 V p-p. The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz, the AGC threshold is 100 mV (–67 dBm) and its maximum gain is 83 dB (20 log 1.4 V/100 mV). The circuit holds its output at

1.4 V rms for inputs as low as –67 dBm to +15 dBm (82 dB),

where the input signal exceeds the AD603’s maximum input rating. For a 30 dBm input at 10.7 MHz, the second harmonic is 34 dB down from the fundamental and the third harmonic is 35 dB down. CAUTION Careful component selection, circuit layout, power-supply decoupling, and shielding are needed to minimize the AD603’s susceptibility to interference from radio and TV stations, etc. In bench evaluation, we recommend placing all of the components in a shielded box and using feedthrough decoupling networks for the supply voltage. Circuit layout and construction are also critical, since stray capacitances and lead inductances can form resonant circuits and are a potential source of circuit peaking, oscillation, or both.

Figure 16. Gain Error vs. Gain Control

70 MHz

Figure 19. Frequency and Phase Figure 22. Third Order Intermodula- Figure 17. Frequency and Phase Figure 20. Group Delay vs. Gain Figure 23. Third Order Intermodula- Figure 18. Frequency and Phase Figure 21. Third Order Intermodula- Figure 24. Typical Output Voltage

REV. C–14– AD603 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Cerdip (Q-8) 1 4 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.055 (1.4) MAX SEATING PLANE0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.405 (10.29) MAX 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 8-Lead SOIC (SO-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)3 458 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) C1851a–0–1/00 (rev. C)PRINTED IN U.S.A.