AD600

AD600/AD602 Dual, Low Noise, Wideband Variable Gain Amplifiers Data Sheet (Rev. F)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 32

Technical content

Dual, Low Noise, Wideband Variable Gain Amplifiers AD600/AD602 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

2 channels with independent gain control Linear in dB gain response 2 gain ranges AD600: 0 dB to 40 dB AD602: –10 dB to +30 dB Accurate absolute gain: ±0.3 dB Low input noise: 1.4 nV/√Hz Low distortion: −60 dBc THD at ±1 V output High bandwidth: dc to 35 MHz (−3 dB) Stable group delay: ±2 ns Low power: 125 mW (maximum) per amplifier Signal gating function for each amplifier Drive high speed ADCs MIL-STD-883-compliant and DESC versions available

APPLICATIONS

Ultrasound and sonar time-gain controls High performance audio and RF AGC systems Signal measurement GENERAL DESCRIPTION The AD600/AD6021 dual-channel, low noise, variable gain amplifiers are optimized for use in ultrasound imaging systems but are applicable to any application requiring precise gain, low noise and distortion, and wide bandwidth. Each independent channel provides a gain of 0 dB to +40 dB in the AD600 and −10 dB to +30 dB in the AD602. The lower gain of the AD602 results in an improved signal-to-noise ratio (SNR) at the output. However, both products have the same 1.4 nV/√Hz input noise spectral density. The decibel gain is directly proportional to the control voltage, accurately calibrated, and supply and temper- ature stable. To achieve the difficult performance objectives, a proprietary circuit form, the X-AMP®, was developed. Each channel of the X-AMP comprises a variable attenuator of 0 dB to −42.14 dB followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs and can benefit from the use of negative feedback to precisely define the gain and dynamics. The attenuator is realized as a 7-stage R-2R ladder network having an input resistance of 100 Ω, laser trimmed to ±2%. The attenuation between tap points is 6.02 dB; the gain-control circuit provides continuous interpolation between these taps. The resulting control function is linear in dB. 1 Patented. FUNCTIONAL BLOCK DIAGRAM PRECISION P ASSIVE INPUT A TTENUA TOR GA TING INTERF ACE SCALING REFERENCE GAT1 A1OP A1CM C1HI C1LO A1HI A1LO VG R-2R LADDER NETWORK GAIN CONTROL INTERFACE RF2 2.24kΩ (AD600) 694Ω (AD602) RF1 20Ω FIXED-GAIN AMPLIFIER 41.07dB (AD600) 31.07dB (AD602) 500Ω 0dB –6.02dB –12.04dB –18.06dB –22.08dB –30.1dB –36.12dB –42.14dB 62.5Ω 00538-001 Figure 1. Functional Block Diagram of a Single Channel of the AD600/AD602 varies by less than ±2 ns at all gain settings. a ±1 V sinusoidal output at 10 MHz is typically −60 dBc. and are available in 16-lead PDIP (N) and 16-lead SOIC packages. available under DESC SMD 5962-94572.

Rev. F | Page 2 of 32 TABLE OF CONTENTS Time-Gain Control (TGC) and Time-Variable Wide Range, RMS-Linear dB Measurement System 100 dB to 120 dB RMS Responding Constant Bandwidth 100 dB RMS/AGC System with Minimal Gain Error 120 dB RMS/AGC System with Optimal SNR

REVISION HISTORY

10/08—Rev. E to Rev. F 1/06—Rev. D to Rev. E 3/04—Rev. C to Rev. D 5/02—Rev. B to Rev. C 8/01—Rev. A to Rev. B

Rev. F | Page 3 of 32 SPECIFICATIONS Each amplifier section at TA = 25°C, VS = ±5 V , −625 mV ≤ VG ≤ +625 mV , RL = 500 Ω, and CL = 5 pF, unless otherwise noted. Specifications for the AD600/AD602 are identical, unless otherwise noted. Table 1. AD600J/AD602J1 AD600A/AD602A1 Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Pin 2 to Pin 3; Pin 6 to Pin 7 98 100 102 95 100 105 Ω Input Capacitance 2 2 pF Input Noise Spectral Density2 1.4 1.4 nV/√Hz Noise Figure RS = 50 Ω, maximum gain 5.3 5.3 dB R S = 200 Ω, maximum gain 2 2 dB Common-Mode Rejection Ratio f = 100 kHz 30 30 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth VOUT = 100 mV rms 35 35 MHz Slew Rate 275 275 V/μs Peak Output3 RL ≥ 500 Ω ±2.5 ±3 ±2.5 ±3 V Output Impedance f ≤ 10 MHz 2 2 Ω Output Short-Circuit Current 50 50 mA Group Delay Change vs. Gain f = 3 MHz; full gain range ±2 ±2 ns Group Delay Change vs. Frequency VG = 0 V, f = 1 MHz to 10 MHz ±2 ±2 ns Total Harmonic Distortion RL= 200 Ω, VOUT = ±1 V peak, RPD = 1 kΩ −60 −60 dBc ACCURACY AD600 Gain Error 0 dB to 3 dB gain 0 +0.5 +1 −0.5 +0.5 +1.5 dB 37 dB to 40 dB gain −1 −0.5 0 −1.5 −0.5 +0.5 dB Maximum Output Offset Voltage4 VG = –625 mV to +625 mV 10 50 10 65 mV Output Offset Variation VG = –625 mV to +625 mV 10 50 10 65 mV AD602 Gain Error –10 dB to –7 dB gain 0 +0.5 +1 –0.5 +0.5 +1.5 dB 27 dB to 30 dB gain −1 −0.5 0 −1.5 −0.5 +0.5 dB Maximum Output Offset Voltage4 VG = −625 mV to +625 mV 5 30 10 45 mV Output Offset Variation VG = −625 mV to +625 mV 5 30 10 45 mV GAIN CONTROL INTERFACE Gain Scaling Factor +3 dB to +37 dB (AD600); −7 dB to +27 dB (AD602) 31.7 32 32.3 30.5 32 33.5 dB/V Common-Mode Range −0.75 +2.5 −0.75 +2.5 V Input Bias Current 0.35 1 0.35 1 μA Input Offset Current 10 50 10 50 nA Differential Input Resistance Pin 1 to Pin 16; Pin 8 to Pin 9 15 15 MΩ Response Rate Full 40 dB gain change 40 40 dB/μs

Rev. F | Page 4 of 32 AD600J/AD602J 1 AD600A/AD602A1 Parameter Conditions Min Typ Max Min Typ Max Unit SIGNAL GATING INTERFACE Logic Input Low (Output On) 0.8 0.8 V Logic Input High (Output Off) 2.4 2.4 V Response Time On to off, off to on 0.3 0.3 μs Input Resistance Pin 4 to Pin 3; Pin 5 to Pin 6 30 30 kΩ Output Gated Off Output Offset Voltage ±10 ±100 ±10 ±400 mV Output Noise Spectral Density 65 65 nV/√Hz Signal Feedthrough @ 1 MHz AD600 −80 −80 dB AD602 −70 −70 dB POWER SUPPLY Specified Operating Range ±4.75 ±5.25 ±4.75 ±5.25 V Quiescent Current Each channel 11 12.5 11 14 mA 1 Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units. 2 Typical open- or short-circuited input; noise is lower when the system is set to maximum gain and the input is short-circuited. This figure includes the effects of both voltage and current noise sources. 3 With an additional 1 kΩ pull-down resistor, if RL < 500 Ω. 4 The dc gain of the main amplifier in the AD600 is ×113; therefore, an input offset of only 100 μV becomes an 11.3 mV output offset. In the AD602, the amplifier gain is ×35.7; therefore, an input offset of 100 μV becomes a 3.57 mV output offset.

Rev. F | Page 5 of 32 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage ± VS ±7.5 V Input Voltages Pin 1, Pin 8, Pin 9, Pin 16 ±VS Pin 2, Pin 3, Pin 6, Pin 7 ±2 V continuous ±V S for 10 ms Pin 4, Pin 5 ±VS Internal Power Dissipation 600 mW Operating Temperature Range J Grade 0°C to 70°C A Grade −40°C to +85°C S Grade −55°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C θJA 16-Lead PDIP 85°C/W 16-Lead SOIC 100°C/W 16-Lead CERDIP 120°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 C1LO CH1 Gain-Control Input Low. Positive voltage reduces CH1 gain. 2 A1HI CH1 Signal Input High. Positive voltage increases CH1 output. 3 A1LO CH1 Signal Input Low. Usually connected to CH1 input ground. 4 GAT1 CH1 Gating Input. A logic high shuts off the CH1 signal path. 5 GAT2 CH2 Gating Input. A logic high shuts off the CH2 signal path. 6 A2LO CH2 Signal Input Low. Usually connected to CH2 input ground. 7 A2HI CH2 Signal Input High. Positive voltage increases CH2 output. 8 C2LO CH2 Gain-Control Input Low. Positive voltage reduces CH2 gain. 9 C2HI CH2 Gain-Control Input High. Positive voltage increases CH2 gain. 10 A2CM CH2 Common. Usually connected to CH2 output ground. 12 VNEG Negative Supply for Both Amplifiers. 13 VPOS Positive Supply for Both Amplifiers. 15 A1CM CH1 Common. Usually connected to CH1 output ground. 16 C1HI CH1 Gain-Control Input High. Positive voltage increases CH1 gain.

Figure 3. Gain Error vs. Gain Control Voltage Figure 4. AD600 Frequency and Phase Response vs. Gain

8.4 GROUP DELA Y (ns)

Figure 5. AD602 Frequency and Phase Response vs. Gain Figure 6. AD600 and AD602 Typical Group Delay vs. VC Figure 7. Third-Order Intermodulation Distortion, VOUT = 2 V p-p, RL = 500 Ω Figure 8. Typical Output Voltage vs. Load Resistance

Rev. F | Page 11 of 32 It is apparent from the foregoing that it is essential to use a low resistance in the design of the ladder network to achieve low noise. In some applications, this can be inconvenient, requiring the use of an external buffer or preamplifier. However, very few amplifiers combine the needed low noise with low distortion at maximum input levels, and the power consumption required to achieve this performance is quite high (due to the need to maintain very low resistance values while also coping with large inputs). On the other hand, there is little value in providing a buffer with high input impedance because the usual reason for this—the minimization of loading of a high resistance source— is not compatible with low noise. Apart from the small variations just mentioned, the SNR at the output is essentially independent of the attenuator setting, because the maximum undistorted output is 1 V rms, and the NSD at the output of the AD600 is fixed at 113 × 114 nV/√Hz, or 158 nV/√Hz. Therefore, in a 1 MHz bandwidth, the output SNR is 76 dB. The input NSD of the AD600/AD602 is the same but, because of the 10 dB lower gain in the AD602’s fixed amplifier, its output SNR is 10 dB better, or 86 dB in a 1 MHz bandwidth. GAIN-CONTROL INTERFACE The attenuation is controlled through a differential, high impedance (15 MΩ) input, with a scaling factor that is laser trimmed to 32 dB per volt, that is, 31.25 mV/dB. Each of the two amplifiers has its own control interface. An internal band gap reference ensures stability of the scaling with respect to supply and temperature variations and is the only circuitry common to both channels. When the differential input voltage V G = 0 V , the attenuator slider is centered, providing an attenuation of +21.07 dB, resulting in an overall gain of +20 dB (= –21.07 dB + +41.07 dB). When the control input is −625 mV , the gain is lowered by +20 dB (= +0.625 × +32) to 0 dB; when set to +625 mV , the gain is increased by +20 dB to +40 dB. When this interface is overdriven in either direction, the gain approaches either +41.07 dB), respectively. The gain of the AD600 can be calculated by Gain (dB) = 32 V G + 20 (1) where VG is in volts. For the AD602, the expression is Gain (dB) = 32 VG + 10 (2) Operation is specified for VG in the range from −625 mV dc to +625 mV dc. The high impedance gain-control input ensures minimal loading when driving many amplifiers in multiple- channel applications. The differential input configuration provides flexibility in choosing the appropriate signal levels and polarities for various control schemes. For example, the gain-control input can be fed differentially to the inputs or single-ended by simply grounding the unused input. In another example, if the gain is controlled by a DAC providing a positive-only, ground-referenced output, the gain control LO pin (either C1LO or C2LO) should be biased to a fixed offset of 625 mV to set the gain to 0 dB when gain control HI (C1HI or C2HI) is at zero and to set the gain to 40 dB when at 1.25 V . It is a simple matter to include a voltage divider to achieve other scaling factors. When using an 8-bit DAC with an FS output of 2.55 V (10 mV/bit), a 1.6 divider ratio (generating 6.25 mV/bit) results in a gain setting resolution of 0.2 dB/bit. The process of cascading the two sections of an AD600 or AD602 when various options exist for gain control is explained in the Achieving 80 DB Gain Range section. SIGNAL-GATING INPUTS Each amplifier section of the AD600/AD602 is equipped with a signal-gating function, controlled by a TTL or CMOS logic input (GAT1 or GAT2). The ground references for these inputs are the signal input grounds A1LO and A2LO, respectively. Operation of the channel is unaffected when this input is LO or left open-circuited. Signal transmission is blocked when this input is HI. The dc output level of the channel is set to within a few millivolts of the output ground (A1CM or A2CM), and simultaneously the noise level drops significantly. The reduction in noise and spurious signal feedthrough is useful in ultrasound beam-forming applications, where many amplifier outputs are summed. COMMON-MODE REJECTION A special circuit technique provides rejection of voltages appearing between input grounds (A1LO and A2LO) and output grounds (A1CM and A2CM). This is necessary because of the op amp form of the amplifier, as shown in Figure 21. The feedback voltage is developed across the RF1 resistor (which, to achieve low noise, has a value of only 20 Ω). The voltage developed across this resistor is referenced to the input common, so the output voltage is also referred to that node. For zero differential signal input between A1HI and A1LO, the output A1OP simply follows the voltage at A1CM. Note that the range of voltage differences that can exist between A1LO and A1CM (or A2LO and A2CM) is limited to about ±100 mV . Figure 18 shows the typical common-mode rejection ratio vs. frequency. ACHIEVING 80 dB GAIN RANGE The two amplifier sections of the X-AMP can be connected in series to achieve higher gain. In this mode, the output of A1 (A1OP and A1CM) drives the input of A2 via a high-pass network (usually just a capacitor) that rejects the dc offset. The nominal gain range is now –2 dB to +82 dB for the AD600 or −22 dB to +62 dB for the AD602.

after the gain of A1 has reached its maximum value (see Figure 26). where VC is the applied control voltage. Figure 26. Explanation of Offset Calibration for Sequential Control the gain error of the cascaded amplifiers vs. the control voltage. A2 decreases linearly as the gain is increased (see Figure 30).

conducts sufficiently. The operation of this control system follows. renders the output stable with temperature.

200 Hz LP filter it forms with C2 helps to minimize distortion

at high gains when using a 5 V supply. gain of this AGC system actually runs from –6 dB to +74 dB.

1 V rms output at the minimum gain, which exceeds the 1 V rms

Figure 38. AC Response at the Stabilized Output Level of 1.3 V rms

Figure 52. VLOG Is Linear over the Full 120 dB Range Figure 52 shows VLOG to be linear over a full 120 dB range. functions bounded by ±0.2 dB (dotted lines) from 6 μV to 2 V . Figure 55. The SNR degrades uniformly as the gain is increased. of the gain-control voltage.

250 GAIN ERROR (mV)

Figure 53. Error Ripple Caused by the Individual Gain Functions Figure 54. VAGC Remains Close to Its Setpoint of Figure 55. SNR vs. Control Voltage for Parallel Gain Control (See Figure 47) In contrast, the SNR for the sequential mode is shown in Figure 56. VCA section has its gain varied, the SNR remains constant. Figure 56. SNR vs. Control Voltage for Sequential Gain Control (See Figure 51)

Rev. F | Page 26 of 32 For the next 40 dB of control range, the gain of U1A remains fixed at its maximum value of 41.07 dB and only the gain of U1B is varied, while that of U2A remains at its minimum value of −1.07 dB. In this interval, the fixed output noise of U1A is amplified by the increasing gain of U1B, and the SNR progressively decreases. Once U1B reaches its maximum gain of 41.07 dB, its output also becomes a gain-independent noise source; this noise is presented to U2A. As the control voltage is further increased, the gains of both U1A and U1B remain fixed at their maximum value of 41.07 dB, and the SNR continues to decrease. Figure 56 clearly shows this because the maximum SNR of 90 dB is extended for the first 40 dB of input signal before it starts to roll off. This arrangement of staggered gains can be easily implemented because, when the control inputs of the AD600 are overdriven, the gain limits to its maximum or minimum values without side effects. This eliminates the need for awkward nonlinear shaping circuits that have previously been used to break up the gain range of multistage AGC amplifiers. The precise values of the AD600’s maximum and minimum gain (not 0 dB and +40 dB but −1.07 dB and +41.07 dB) explain the rather odd values of the offset values that are used. The optimization of the output SNR is of obvious value in AGC systems. However, in applications where these circuits are considered for their wide range logarithmic measurement capabilities, the inevitable degradation of the SNR at high gains need not seriously impair their utility. In fact, the bandwidth of the circuit shown in Figure 47 was specifically chosen to improve measurement accuracy by altering the shape of the log error curve at low signal levels (see Figure 53).

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 59. 16-Lead Standard Small Outline Package [SOIC_W]

Rev. F | Page 29 of 32 ORDERING GUIDE Model Gain Range Temperature Range Package Description Package Option AD600AQ 0 dB to 40 dB −40°C to +85°C 16-Lead CERDIP Q-16 AD600AR 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600AR-REEL 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600AR-REEL7 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600ARZ1 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600ARZ-R71 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600ARZ-RL1 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600JN 0 dB to 40 dB 0°C to 70°C 16-Lead PDIP N-16 AD600JNZ1 0 dB to 40 dB 0°C to 70°C 16-Lead PDIP N-16 AD600JR 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JR-REEL 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JR-REEL7 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JRZ1 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JRZ-R71 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JRZ-RL1 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600SQ/883B2 0 dB to 40 dB −55°C to +125°C 16-Lead CERDIP Q-16 AD602AQ −10 dB to +30 dB −40°C to +85°C 16-Lead CERDIP Q-16 AD602AR −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602AR-REEL −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602AR-REEL7 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602ARZ1 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602ARZ-R71 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602ARZ-RL1 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602JCHIPS DIE AD602JN −10 dB to +30 dB 0°C to 70°C 16-Lead PDIP N-16 AD602JNZ1 −10 dB to +30 dB 0°C to 70°C 16-Lead PDIP N-16 AD602JR −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JR-REEL –10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JR-REEL7 −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JRZ1 −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JRZ-R71 –10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JRZ-RL1 −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602SQ/883B3 −10 dB to +30 dB −55°C to +125°C 16-Lead CERDIP Q-16 1 Z = RoHS Compliant Part. 2 Refers to AD600/AD602 military data sheet. Also available as 5962-9457201MEA. 3 Refers to AD600/AD602 military data sheet. Also available as 5962-9457202MEA.

Rev. F | Page 30 of 32 NOTES

Rev. F | Page 31 of 32 NOTES

Rev. F | Page 32 of 32 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00538-0-10/08(F)