AD5941BCPZ-RL7

Analog Devices

High Precision, Impedance, and Electrochemical Front End

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High Precision, Impedance, and Electrochemical Front End Data Sheet AD5940/AD5941 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2019-2022 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

16-bit ADC with both 800 kSPS and 1.6 MSPS options Voltage, current, and impedance measurement capability Internal and external current and voltage channels Ultralow leakage switch matrix and input mux Input buffers and programmable gain amplifier Voltage DACs Dual output voltage DAC with an output range of 0.2 V to 2.4 V 12-bit VBIAS0 output to bias potentiostat 6-bit VZERO0 output to bias TIA Ultra low power: 1 µA 1 high speed, 12-bit DAC Output range to sensor: ±607 mV Programmable gain amplifier on output with gain settings of 2 and 0.05 Amplifiers, accelerators, and references 1 low power, low noise potentiostat amplifier suitable for potentiostat bias in electrochemical sensing 1 low noise, low power TIA, suitable for measuring sensor current output 50 pA to 3 mA range Programmable load and gain resistors for sensor output Analog hardware accelerators Digital waveform generator Receive filters Complex impedance measurement (DFT) engine 1 high speed TIA to handle wide bandwidth input signals from 0.015 Hz up to 200 kHz Digital waveform generator for generation of sinusoid and trapezoid waveforms 2.5 V and 1.82 V internal reference voltage sources System level power savings Fast power-up and power-down analog blocks for duty cycling Programmable AFE sequencer to minimize workload of host controller 6 kB SRAM to preprogram AFE sequences Ultra low power potentiostat channel: 6.5 µA of current consumption when powered on and all other blocks in hibernate mode Smart sensor synchronization and data collection Cycle accurate control of sensor measurement Sequencer controlled GPIOs On-chip peripherals SPI serial input/output Wake-up timer Interrupt controller Power 2.8 V to 3.6 V supply

1.82 V input/output compliant

Hibernate mode with low power DAC and potentiostat amplifier powered up to maintain sensor bias Package and temperature range 3.6 mm × 4.2 mm, 56-ball WLCSP 7 mm × 7 mm, 48-lead LFCSP AD5940 and AD5941 fully specified for operating temperature range of −40°C to +85°C AD5941W fully specified for operating temperature range of −40°C to +105°C AEC-Q100 qualified for automotive applications

APPLICATIONS

Electrochemical measurements Electrochemical gas sensors Potentiostat/amperometric/voltammetry/cyclic voltammetry Bioimpedance applications Skin impedance Body impedance Continuous glucose monitoring Battery impedance SIMPLIFIED BLOCK DIAGRAM F igure 1. SPI DATA FIFODIGITAL FILTERS DF T SLEEP/WAKEUP TIMER ADC FIFO AND MMR SEQUENCER WAVEFORM GENERATOR INTERRUPTION GENERATORGPIOs POTENTIOSTAT: AMPLIFIER AND DAC CURRENT CHANNELS VOLTAGE CHANNELS INTERNAL CHANNELS TEMPERATURE CHANNEL 16-BIT ADC LDOs VOLTAGE REFERENCESIMPEDANCE ENGINE AMPLIFIERS AND DAC 16778-201

Rev. C | Page 2 of 134 TABLE OF CONTENTS Recommended Switch Settings for Various Operating Modes Coupling an AC Signal from the High Speed DAC to the DC Avoiding Incoherency Errors Between Excitation and Measurement Frequencies During Impedance Measurements High Power and Low Power Buffer Control Register—

Rev. C | Page 4 of 134 8/2019—Rev. 0 to Rev. A Changes to Figure 2, Added Figure 3, Renumbered Sequentially Change to Table 20, Amperometric Mode with Short Switch Changes to Configuring a Defined Sequence Order Section .... 102 /2019—Revision 0: Initial Version

Rev. C | Page 6 of 134 GENERAL DESCRIPTION The AD5940 and AD5941are high precision, low power analog front ends (AFEs) designed for portable applications that require high precision, electrochemical-based measurement techniques, such as amperometric, voltammetric, or impedance measurements. The AD5940/AD5941 is designed for skin impedance and body impedance measurements, and works with the AD8233 AFE in a complete bioelectric or biopotential measurement system. The AD5940/AD5941 is designed for electrochemical toxic gas sensing. The AD5940/AD5941 consist of two high precision excitation loops and one common measurement channel, which enables a wide capability of measurements of the sensor under test. The first excitation loop consists of an ultra low power, dual-output string, digital-to-analog converter (DAC), and a low power, low noise potentiostat. One output of the DAC controls the non- inverting input of the potentiostat, and the other output controls the noninverting input of the transimpedance amplifier (TIA). This low power excitation loop is capable of generating signals from dc to 200 Hz. The second excitation loop consists of a 12-bit DAC, referred to as the high speed DAC. This DAC is capable of generating high frequency excitation signals up to 200 kHz. The AD5940/AD5941 measurement channel features a 16-bit, 800 kSPS, multichannel successive approximation register (SAR) analog-to-digital converter (ADC) with input buffers, a built in antialias filter, and a programmable gain amplifier (PGA). An input multiplexer (mux) in front of the ADC allows the user to select an input channel for measurement. These input channels include multiple external current inputs, external voltage inputs, and internal channels. The internal channels allow diagnostic measurements of the internal supply voltages, die temperature, and reference voltages. The current inputs include two TIAs with programmable gain and load resistors for measuring different sensor types. The first TIA, referred to as the low power TIA, measures low bandwidth signals. The second TIA, referred to as the high speed TIA, measures high bandwidth signals up to 200 kHz. An ultra low leakage, programmable switch matrix connects the sensor to the internal analog excitation and measurement blocks. This matrix provides an interface for connecting external trans- impedance amplifier resistors (R TIAs) and calibration resistors. The matrix can also be used to multiplex multiple electronic measurement devices to the same wearable electrodes. A precision 1.82 V and 2.5 V on-chip reference source is available. The internal ADC and DAC circuits use this on-chip reference source to ensure low drift performance for the 1.82 V and 2.5 V peripherals. The AD5940/AD5941 measurement blocks can be controlled via direct register writes through the serial peripheral interface (SPI) interface, or, alternatively, by using a preprogrammable sequencer, which provides autonomous control of the AFE chip. 6 kB of static random access memory (SRAM) is partitioned for a deep data first in, first out (FIFO) and command FIFO. Measurement commands are stored in the command FIFO and measurement results are stored in the data FIFO. A number of FIFO related interrupts are available to indicate when the FIFO is full. A number of general-purpose inputs/outputs (GPIOs) are available and controlled using the AFE sequencer. The AFE sequencer allows cycle accurate control of multiple external sensor devices. The A D5940/ AD5941 operate from a 2.8 V to 3.6 V supply and are specified over a temperature range of −40°C to +85°C. The AD5940 is packaged in a 56-lead, 3.6 mm × 4.2 mm WLCSP . The AD5941 is packaged in a 48-lead LFCSP .

Rev. C | Page 7 of 134 SPECIFICATIONS reference, excitation, DAC, and amplifier = 1.82 V, internal reference; low power DAC reference = 2.5 V, internal reference; TA = −40°C to +85°C for the AD5940 and AD5941, unless otherwise noted. TA = −40°C to 105°C for the AD5941W, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments BASIC ADC SPECIFICATIONS P seudo differential mode measured relative to ADC bias voltage (voltage on VBIAS_CAP1 pin, 1.11 V), unless otherwise noted; specifications based on high speed mode, unless otherwise noted; ADC voltage channel calibrated in production with PGA gain = 1.5; AFE die clock for the analog domain (ACLK) = 32 MHz or 16 MHz, unless otherwise noted Data Rate2 fSAMPLE 400 k SPS High speed mode; decimation factor = 4 200 k SPS Normal mode; decimation factor = 4 Resolution2 16 Bi ts Number of data bits Integral Nonlinearity2 INL Normal Mode −4 ± 2.0 +4 LSB PGA gain = 1.5, 1.82 V internal reference, 1 LSB = 1.82 V ÷ 215 ÷ PGA gain − 5.6 ±2.0 +4.7 LSB PGA gain = 9, 1.82 V internal reference Differential Nonlinearity2 DNL

1.82 V ÷ 215 ÷ PGA gain, no missing codes

DC Code Distribution3 ±6 LSB P GA gain = 1.5, low power mode, ADC input = 0.9 V; ADC output data rate = 200 kSPS; 1 LSB = 1.82 V ÷ 215 ±6 LSB I nput channel is low power TIA = 1 µA, RTIA = 512 kΩ, RLOAD = 10 Ω, ADC output data rate = 200 kSPS ±6 LSB I nput channel is high speed TIA = 1 µA, RTIA = 10 kΩ, RLOAD = 100 Ω, ADC output data rate = 200 kSPS ADC ENDPOINT ERRORS Offset Error Low Power Mode − 600 ±200 +600 µV PGA gain = 1.5, low power mode, all channels except AIN3 −6 20 ±200 +880 µV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −1 .1 ±0.5 +1.4 mV PGA gain = 1.5 Drift over Temperature2 ±3 µ V/°C Using 1.82 V internal reference Offset Matching ±2 LSB Matching compared to AIN3 Full-Scale Error −10 00 ±400 +800 µV PGA gain = 1.5, excluding internal channels and AIN3; both negative and positive full scale; error at both endpoints −10 00 +10 00 µV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −2 .2 ±0.9 +1.82 mV PGA gain = 1.5 Internal Channels2 0.2 0. 75 % FS AVDD/2, DVDD/2, VBIAS_CAP, VREF_2V5, VREF_1V82, AVDD_REG Gain Drift over Temperature2 −3 ±1 +3 µ V/°C Full-scale error drift minus offset error drift Gain Error Matching ±3 LSB M ismatch from channel to channel PGA Mismatch Error2 A DC offset and gain calibration5, 6, 7, 8 with a gain value of 1.5 PGA Gain = 1 to 1.5 − 0.2 +0.1 +0.3 % PGA Gain =1.5 to 2 − 0.2 +0.1 +0.3 %

Rev. C | Page 8 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments PGA Gain = 2 to 4 −0.65 +0.2 +0.65 % PGA Gain = 4 to 9 −0.65 +0.2 +0.65 % ADC DYNAMIC PERFORMANCE fIN = 20 kHz sine wave, fSAMPLE = 200 kSPS; using AINx voltage input channels; PGA gain = 1.5 Signal-to-Noise Ratio SNR Includes distortion and noise components 80 dB PGA gain = 1, 1.5, and 2 762 dB PGA gain = 4 702 dB PGA gain = 9 Total Harmonic Distortion2 THD −84 dB Peak Harmonic or Spurious Noise2 −86 dB Channel to Channel Crosstalk2 −86 dB Measured on adjacent channels Noise (RMS)9 800 nV/√Hz Chop on 400 nV/√Hz Chop off ADC INPUT Input to ADC mux Input Voltage Ranges2 0.2 2.1 V Voltage applied to any input pin V Pseudo differential voltage between VBIAS_ CAP pin and analog input from ADC mux −0.9 +0.9 V Gain = 1 −0.6 +0.6 V Gain = 2 −0.3 +0.3 V Gain = 4 −0.133 +0.133 V Gain = 9 Input Current Range2 0.0000 3000 µA Low power TIA and high speed TIA current input channel ranges Common Mode Range2 0.2 1.1 2.1 V Leakage Current −1.5 ±0.5 +1.5 nA AIN0, AIN1, AIN2, AIN3/BUF_VREF1V82, AIN4/LPF0, AIN6 (TA = −40°C to +85°C) −6 +6 nA CE0, RE0, SE0 and DE0 (TA = −40°C to 85°C) −3.5 ±0.5 +3.5 nA AIN0, AIN1, AIN2, AIN3/BUF_VREF1V82, AIN4/LPF0, AIN6 ( TA = −40°C to +105°C) −8 +8 nA CE0, RE0, SE0 and DE0 (TA = −40°C to +105°C) Input Current2 −8 ±2 +8 nA AIN0, AIN1, AIN2, AIN3, AIN4, AIN6, CE0, RE0, SE0, and DE0 Input Capacitance2 40 pF During ADC acquisition Antialias Filter 3 dB Frequency Range2 Three programmable settings Mode 0 50 kHz Mode 1 100 kHz Mode 2 250 kHz ADC Channel Switch Settling Time Time delay required after switching ADC input channel; excludes sinc3 settling time Antialias Filter −3 dB Cutoff Frequency2 250 kHz 20 µs 100 kHz 40 µs 50 kHz 60 µs DISCRETE FOURIER TRANSFORM (DFT)-BASED IMPEDANCE MEASUREMENTS2 With High Bandwidth Loop For impedance (Z) of 1000 Ω (0.1% tolerant resistor), excitation frequency = 0.1 Hz to 200 kHz, sine amplitude = 10 mV rms, R TIA = 5 kΩ; RCAL = 200 Ω;1% accurate temperature coefficient 5 ppm/°C; single DFT measure-ment; DFT using 8192 ADC samples; Hanning on; HSDACCON Bits[8:1] = 0x1B for low power mode and impedance measurements ≤80 kHz; HSDACCON Bits[8:1] = 0x7 for high power mode and impedance measurements ≥80 kHz

Rev. C | Page 9 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Accuracy Magnitude −1.25 ±0.2 +1.25 % 20 kHz to 200 kHz ±0.2 % 10 Hz to 20 kHz ±1 % 1 Hz to <10 Hz Phase −0.3 ±0.1 +0.3 Degrees Three-Resistor Star Cell Accuracy R1 = R2 = R3 = 2.2 Ω (see Figure 18); 0.1 Hz to 200 kHz Magnitude ±0.5 % Phase ±0.5 Degrees Accuracy R1 = R2 = R3 = 100 Ω connected (see Figure 18); 0.1 kHz to 200 kHz Magnitude ±0.2 % Phase ±0.2 Degrees With High Bandwidth Loop, 50 kHz, 4-Wire Isolated For Z = 1 kΩ (0.1% tolerant resistor); excitation frequency = 50 kHz; sine amplitude =

0.6 V p-p; RTIA = 1 kΩ; CTIA = 32 pF; Isolation Capacitor

1 (CISO1) = 15 nF; Isolation Capacitor 2 (CISO2) = Isolation Capacitor 3 (CISO3) = Isolation Capacitor 4 (CISO4) = 470 nF; current-limiting resistor (RLIMIT) = 1 kΩ Accuracy Device to device repeatability for three devices at 50 kHz Magnitude 0.26 % Percentage error Phase 1 Degrees With Low Bandwidth Loop For Z = 100 kΩ; excitation frequency = 100 Hz; sine amplitude = 1.1 V p-p; RTIA = 100 kΩ; CTIA = 100 nF; CISO1 = 15 nF; CISO2 = 470 nF; RLIMIT = 1000 Ω Frequency Range 1 300 Hz Accuracy2 Device to device repeatability for three devices at 100 Hz Magnitude ±0.3 % Percentage error Precision2 Magnitude 450 Ω Standard deviation High Speed Loop See Figure 18; valid for impedance spectroscopy, voltammetry, and pulse tests Allowed External Load Capacitance2 100 pF R2 + R3 ≤ 100 Ω; R1 ≤ 100 Ω 50 pF R2 + R3 ≤ 500 Ω; R1 ≤ 100 Ω 40 pF R2 + R3 ≤ 1600 Ω; R1 ≤ 800 Ω; frequency ≥ 1 kHz Excitation Amplifier Bandwidth2

3 MHz

0.015 200,00 Hz LOW POWER TIA AND POTENTIOSTAT Input Bias Current2 TIA Amplifier, SE0 Pin 80 200 pA Potentiostat Amplifier 20 150 pA Offset Voltage2 50 150 µV Offset Voltage Drift vs. Temperature 1 µV/°C Noise2 Unity-gain mode; V p-p in 0.1 Hz to 10 Hz range 1.6 µV Normal mode (LPTIACON0 Bit 2 = 0) 2 µV Half power mode (LPTIACON0 Bit 2 = 1) Potentiostat Source/Sink Current2 −750 +750 µA Normal mode (LPTIACON0 Bits[4:3] = 00); from CE0 −3 +3 mA High current mode (LPTIACON0 Bits[4:3] = 01 or 11 from CE0

Rev. C | Page 10 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC PSRR2 70 dB At RE0 pin; RTIA = 256 kΩ; RLOAD = 10 Ω Input Common-Mode Range2 300 AVDD – 600 mV Output Voltage Range2 300 AVDD – 400 mV Normal mode (LPTIACON0 Bits[4:3] = 00; sink/source = 750 µA

300 AVDD

− 400 mV High current mode (LPTIACON0 Bits[4:3] = 01 or 11); sink/source = 3 mA Overcurrent Limit Protection2 20 mA Amplifiers try to limit source/sink current to this value via internal clamp Allowed Duration of Overcurrent Limit2 5 sec User must limit duration of overcurrent condition to less than 5 sec or risk damaging amplifier Allowed Frequency of Overcurrent Conditions2

1 Per hour

Short-Circuit Protection2 12 mA When amplifier output is shorted to ground PROGRAMMABLE RESISTORS Low Power TIA RLOAD on SE0 Inputs2 0 Ω RLOAD Accuracy 0.01 0.08 0.15 Ω 10 Ω RLOAD Accuracy 9.8 11.7 13.5 Ω 30 Ω RLOAD Accuracy 28 33.8 39 Ω 50 Ω RLOAD Accuracy 48 55 63 Ω 100 Ω RLOAD Accuracy 88 110 130 Ω ±200 ppm/°C 10 Ω, 30 Ω, 100 Ω, 1500 Ω, 3000 Ω, and 3500 Ω ±400 ppm/°C 50 Ω Low Power TIA RTIA10 on SE0 Input2 Accuracy −5 +20 % User programmable; includes 1 kΩ, 2 kΩ, 3 kΩ, 4 kΩ, 6 kΩ, 8 kΩ, 10 kΩ, 16 kΩ, 20 kΩ, 22 kΩ, 30 kΩ, 40 kΩ, 64 kΩ, 100 kΩ, 128 kΩ, 160 kΩ, 192 kΩ, 256 kΩ, and 512 kΩ 100 120 140 Ω 200 Ω setting with RLOAD = 100 Ω Drift over Temperature ±100 ppm/°C Mismatch Error2 Error when moving up or down one RTIA value −0.6 +0.2 +0.6 % 512 kΩ to 2 kΩ range excluding 40 kΩ −3.5 +0.5 +3.5 % 40 kΩ (up to 48 kΩ, down to 32 kΩ) ±20 % 200 Ω High Speed TIA RTIA on SE0 Input Accuracy 20 % User programmable; includes 100 Ω, 200 Ω, 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Drift over Temperature ±200 ppm/°C High Speed TIA RLOAD on SE0 Input2 User programmable; includes 10 Ω, 30 Ω, 50 Ω, and 100 Ω Accuracy 102 110 116 Ω Fixed 100 Ω target setting Drift over Temperature ±160 ppm/°C High Speed TIA RTIA on DE0 Input2 User programmable; includes 0.1 kΩ, 0.2 kΩ, 1.5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Accuracy 100 135 170 Ω 100 Ω setting 190 250 320 Ω 200 Ω setting ±20 % 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Drift over Temperature ±350 ppm/°C 100 Ω and 200 Ω settings ±200 ppm/°C 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ High Speed TIA RTIA Mismatch Error on DE02 Error introduced when moving up or down one R TIA value −3.5 +1 +3.5 % 160 kΩ to 5 kΩ range −25 ±2 +5 % 1 kΩ, 200 Ω, and 100 Ω

Rev. C | Page 11 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments High Speed TIA RLOAD on DE0 Input2 Load resistor on the DE0 pin (RLOAD_DE0) Accuracy 0.001 0.15 Ω 0 Ω setting 5 11 Ω 10 Ω setting 26.5 32.6 37.6 Ω 30 Ω setting ±15 40 % 50 Ω and 100 Ω settings Drift over Temperature ±0.2 %/°C 10 Ω setting ±200 ppm/°C Excludes RLOAD = 0 Ω and 10 Ω HIGH SPEED TIA Bias Current2 1 nA Maximum Current Sink/Source2 −3 +3 mA Ensure RTIA selection generates an output voltage of <±900 mV with PGA gain = 1 Input Common-Mode Range2 300 AVDD − 700 mV Output Voltage Range2 200 AVDD − 400 mV Overcurrent Limit Protection2 17 mA Amplifier attempts to limit the source/sink current to this value via the internal clamp; tested with RLOAD = 0 Ω and RTIA = 100 Ω Allowed Duration of Overcurrent Limit2 5 sec Allowed Frequency of Overcurrent Conditions2 Short-Circuit Protection2 12 mA When amplifier output is shorted to ground LOW POWER, ON-CHIP VOLTAGE REFERENCE 2.5 V 0.47 µF from VREF_2V5 to AGND; reference is measured with low power voltage DAC and output amplifier enabled Accuracy ±5 mV TA = 25°C Noise2 60 µV p-p Reference Temperature Coefficient2 , 15 −25 ±10 +25 ppm/°C PSRR DC 70 dB AC11 48 dB AC 1 kHz; 50 mV p-p ripple applied to AVDD supply HIGH POWER, ON-CHIP VOLTAGE REFERENCE 1.82 V 0.47 µF from VREF_1V82 to AGND; reference is measured with ADC enabled Accuracy ±5 mV TA = 25°C Reference Temperature Coefficient2 −20 ±5 +20 ppm/°C PSRR DC12 85 dB DC; variation due to AVDD supply changes AC 60 dB AC; 1 kHz, 50 mV p-p ripple applied to AVDD supply ADC Common-Mode Reference Source2

1.11 V 470 nF from bias capacitor on ADC (VBIAS_CAP)

to AGND; reference is measured with ADC enabled Accuracy 2 ±5 mV TA = 25°C Reference Temperature Coefficie nt2 −20 +20 ppm/°C DC Power Supply Rejection Ratio PSRR 80 dB DC variation due to AVDD supply changes AC Power Supply Rejection Ratio PSRR 60 dB AC 1 kHz, 50 mV p-p ripple applied to AVDD supply

Rev. C | Page 12 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOW POWER, DUAL OUTPUT DAC (VBIAS013 AND VZERO0) VBIAS0 specifications derived from measurements taken with potentiostat in unity-gain mode and measured at CE0; VZERO0 specifications derived from measurements at VZERO0; dual output low power DAC Resolution2 Number of data bits 12-Bit Mode 12 Bits 6-Bit Mode 6 Bits Relative Accuracy2 INL 12-Bit Mode −3.5 ±1 +3 LSB 1 LSB = 2.2 V/(212 − 1) 6-Bit Mode −3.5 ±0.5 +2 LSB 1 LSB = 2.2 V/26 Differential Nonlinearity2 DNL 12-Bit Mode −0.99 +2.5 LSB Guaranteed monotonic, 6-Bit Mode −0.5 +0.5 LSB Guaranteed monotonic, 1 LSB = 2.2 V/26 Offset Error2 −7 ±3.9 +7 mV VBIAS0/VZERO0 in 12-bit mode; 2.5 V internal reference, DAC output code = 0x000; Target 0x000 code = 200 mV −2 ±0.2 +2.6 mV Differential offset voltage of VBIAS0 referred to VZERO0 Drift over Temperature ±5 µV/°C VBIAS0 or VZERO0 referred to AGND Differential Offset VBIAS0 to VZERO0 ≈ 0 V2 4 µV/°C Differential offset voltage of VBIAS0 referred to VZERO0; −40°C to +60°C range; LPDACDAT0 = 0x1A680 Differential Offset VBIAS0 to VZERO0 ≈ ±600 mV2 10 µV/°C Differential offset voltage of VBIAS0 referred to VZERO0, −40°C to +60°C range; LPDACDAT0 = 0x1AAE0 Gain Error2 ±0.2 ±0.5 % 12-bit mode, DAC code = 0xFFF with target voltage of 2.4 V Drift over Temperature 10 ppm/°C Using internal low power reference Analog Outputs Output Voltage Range2 LSB size = 2.2/(212 − 1); the input common-mode voltage of the low power potentiostat amplifier and low power TIA = AVDD − 600 mV 12-Bit Outputs 0.2 2.4 V AVDD ≥ 2.8 V 6-Bit Outputs LSB size is 2.2/26; the input common-mode voltage of the low power potentiostat amplifier and low power TIA = AVDD − 600 mV 0.2 2.366 V AVDD ≥ 2.8 V 0.2 2.3 V AVDD < 2.8V AVDD to VBIAS0/VZERO0 Headroom Voltage2 400 mV A minimum headroom between AVDD and VBIAS0/VZERO0 output voltage, increases to 600 mV if connected to low power TIA or low power low power potentiostat amplifiers Output Impedance2 1.65 MΩ DAC AC Characteristics Output Settling Time 1.5 sec Settled to ±2 LSB12 with 0.1 µF load for ¼ of full scale to ¾ of full scale Output Settling Time 500 µs Settled to ±2 LSB12; no load Glitch Energy ±5 nV/sec 1 LSB change when the maximum number of bits changes simultaneously in the LPDACDAT0 register; switch to external capacitors on VBIAS0/VZERO0 opened; no capacitors on CE0 and RC0_x pins EXCITATION DAC/PGA/ RECONSTRUCTION FILTER Use HSDACDAT register range of 0x200 to 0xE00; specified for gain = 2 (HSDACCON Bit 12 and Bit 0 = 0); for gain = 0.05 (HSDACCON Bit 12 and Bit 0 = 1) DAC Common-Mode Voltage Range2

0.2 AVDD

− 0.6 V Set by the negative node of the excitation amplifier

Rev. C | Page 13 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resolution2 12 Bits 1 LSB = 293 µV × programmable gain Differential Nonlinearity2 DNL −0.99 +1.25 LSB Gain = 2 ±7 ±20 LSB Gain = 0.05 Integral Nonlinearity2 INL ±2 ±3 LSB Gain = 2 ±8 ±20 LSB Gain = 0.05 ±0.6 ±3 LSB Gain = 2 Full-Scale Error2, 14 Positive 600 630 650 mV Gain = 2, DAC code = 0xE00 15.1 mV Gain = 0.05, DAC code = 0xE00 Negative −660 −640 −620 mV Gain = 2, DAC code = 0x200 −15.1 mV Gain = 0.05, DAC code = 0x200 Gain Error Drift over Temperature2 Gain = 2 11.5 µV/°C Gain = 0.05 0.33 µV/°C Offset Error (Midscale) Measured at an output of the excitation loop across R CAL; DAC code = 0x800 ±25 mV Gain = 2 ±0.5 mV Gain = 0.05 Offset Error Drift over Temperature Gain = 2 40 µV/°C Gain = 0.05 5 µV/°C DC PSRR2 70 dB DC variation due to AVDD supply changes PGA, Programmable Gain2 0.05 2 Gain Reconstruction Filter 3 dB Corner Frequency Accuracy ±5 % Programmable to 50 kHz, 100 kHz, and 250 kHz Allowed External Load Capacitance SE0, DE0, AINx, and RCAL0/RCAL1 pins <80 kHz (Low Power Mode) 100 pF >80 kHz (High Power Mode) 80 pF Overcurrent Limit Protection2 15 mA Amplifier attempts to limit the source/sink current to this value via the internal clamp Allowed Duration of Overcurrent Limit2 5 sec Allowed Frequency of Overcurrent Conditions2 Short-Circuit Protection2 10 mA When amplifier output is shorted to ground SWITCH MATRIX Switches on analog front end before ADC mux On Resistance2 RON Characterized with a voltage sweep from 0 V to AVDD; production tested at 2.8 V Current Carrying Switches 40 80 Ω Tx/TR1 switches, except T5 and T7 30 52 Ω T5 and T7 switches only 35 70 Ω Dx/DR0 switches Noncurrent Carrying Switches 1 5 kΩ Nx/Nxx and Px/Pxx switches DC Off Leakage 370 pA Analog input pin used for test driven to 0.3 V DC On Leakage2 530 2000 pA Analog input pin used for test driven to 0.3 V TEMPERATURE SENSOR Resolution 0.3 °C Accuracy ±2 °C Measurement taken immediately after exiting hibernate mode; user single-point calibration required POWER-ON RESET POR Refers to voltage on DVDD pin POR Trip Level Power-On 1.59 1.62 1.72 V Power-Down2 1.799 1.8 1.801 V POR Hysteresis1 10 mV

Rev. C | Page 14 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Delay Between POR Power-On and Power-Down Trip Levels2 110 ms After DVDD passes POR power-on trip level, DVDD must remain at or above power-down level for this period External Reset Minimum Pulse Width2 1 µs Minimum pulse width required on external reset pin to trigger a reset WAKE-UP TIMER2 Shortest Duration 31.25 µs Longest Duration 32 sec DIGITAL INPUTS Input Leakage Current2 Logic 1 GPIO 1 ±5 nA Voltage input high (VIH ) = IOVDD, pull-up resistor disabled Logic 0 GPIO 1 ±10 nA Voltage input low (VIL ) = 0 V, pull-up resistor disabled Input Capacitance2 10 pF Pin Capacitance2 XTALI 10 pF XTALO 10 pF GPIO Input Voltage Low VINL 0.25 × IOVDD V High VINH 0.57 × IOVDD V XTALI Input Voltage2 Low VINL 1.1 V High VINH 1.7 V LOGIC INPUTS GPIO Input Voltage2 Low VINL 0.25 × IOVDD V High VINH 0.57 × IOVDD V Pull-Up Current2 30 130 µA Input voltage (VIN) = 0 V; DVDD = 3.6 V LOGIC OUTPUTS All digital outputs, excluding XTALO GPIO Output Voltage2,15 High VOH IOVDD − 0.4 V Source current (I SOURCE) = 2 mA Low VOL 0.35 V Sink current (ISINK) = 2 mA Pull-Down Current2 30 100 µA VIN = 3.3 V GPIO Short-Circuit Current 11.5 mA PIN SUPPLY RANGE FOR 1.8 V INPUT/OUTPUT2 1.62 1.8 1.98 V Input Voltage Low VINL 0.3 × pin supply V High VINH 0.7 × pin supply V Output Voltage Low VOL 0.45 V ISINK = 1.0 mA High VOH Pin supply − 0.5 V I SOURCE = 1.0 mA

Rev. C | Page 15 of 134 Parameter Symbol Min Typ Max Unit Test Conditions/Comments OSCILLATORS Internal System Oscillator 16 or MHz Accuracy 16 MHz Mode ±0.5 ±3 % 32 MHz Mode ±0.5 ±3 % External Crystal Oscillator 16 32 MHz Can be selected in place of the internal oscillator Logic Inputs, XTALI Only Input Low Voltage VINL 1.1 V Input High Voltage VINH 1.7 V XTALI Input Capacitance 8 pF XTALO Output Capacitance 8 pF 32 kHz Internal Oscillators 32.768 kHz Used for watchdog16 timers and wake-up timers Accuracy ±5 ±15 % EXTERNAL INTERRUPTS Pulse Width2 Level Triggered 7 ns Edge Triggered 1 ns POWER REQUIREMENTS Power Supply Voltage Range (AVDD to AGND, DVDD to DGND, and IOVDD to DGND) 2.8 3.3 3.6 V IOVDD17 1.62 1.8 1.98 V AVDD Current 0.56 0.74 mA Analog peripheral in idle mode Hibernate Mode 8.5 µA Only low power DAC, potentiostat amplifiers, low power reference, low power TIA, and 32 kHz oscillator active 6.52 µA Only low power DACs, potentiostat amplifier, low power reference, and 32 kHz oscillator active; potentiostat amplifier and low power TIA in half power mode 1.82 µA Lowest power mode; only wake-up timer active; all analog peripherals powered down Impedance Measurement Modes2 Impedance Spectroscopy Mode 9.1 mA When ac impedance engine, ADC and sequencer are active 50 kHz Impedance Measurement 106 µA 50 kHz excitation signal; DFT enabled with DFT sample number = 2048; 1 Hz output data rate (ODR)

100 Hz Impedance

65 µA When low power loop creates sine wave at

100 Hz and the receive channel and DFT engine is

duty cycled, with DFT sample number = 16, gives 4 Hz ODR Additional Power Supply Currents2 ADC 1.5 mA ADC frequency (fADC) = 200 kSPS, ADC clock is

16 MHz

3.45 mA fADC = 400 kSPS, ADC clock is 32 MHz High Speed TIA 0.3 mA Low power mode

0.9 High power mode

High Speed DAC Includes excitation amplifier and instrumentation amplifier 2.2 mA Low power mode 4.5 mA High power mode DFT Hardware Accelerator 550 µA

1 VBIAS_CAP is only meant for internal biasing within the IC. 2 Guaranteed by design, not production tested. 3 Code distribution can be reduced if ADC output rate is reduced by using sinc2 filter option. 4 ADC offset and gain not calibrated for high power mode in production. User calibration can eliminate this error. 5 There is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the calibration to the ADC. 6 A 1.835 V/1.82 V factor must be added while performing the calibration. 7 The 1.82 V reference is used to calibrate the ADC offset and gain. values in the MCU flash during factory calibration and load those values on power-up. 9 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. See Table 2 for ADC rms noise: digital filter settings. 10 The low power TIA gain resistor must be calibrated regularly because the resistor has a high temperature drift. 11 See Figure 8 for details. 12 See Figure 10 for details. 13 VBIAS0 can be used for sourcing the offset voltage to external amplifiers. 14 High speed DAC offset calibration can remove this error. See the High Speed DAC Calibration Options section for details. 15 Measured using the box method. 16 The watchdog can be turned off during system initialization. 17 IOVDD can optionally be powered from a 1.8 V supply rail. The internal 1.82 V reference is used for all measurements. Table 2 provides the rms noise specifications for the ADC with different ADC digital filter settings. Table 2. ADC RMS Noise1 1 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. Input Range is the input voltage range to the ADC. RMS Noise is the rms of the noise.

Table 3. ADC Effective Bits Based on RMS Noise 1 Settling time except for 50 Hz and 60 Hz notch filter enables. 2 Settling time including 50 Hz and 60 Hz notch filter enables. Figure 4. SPI Interface Timing Diagram

PCB thermal design is required. resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance

Table 7. Pin Function Descriptions A1 28 AFE4 Analog Uncommitted Analog Front End Pin 4. A2 27 AFE3 Analog Uncommitted Analog Front End Pin 3. A4 41 AVDD Supply Analog Circuit Power. Short this pin to Pin F2 (AVDD). Loop Circuits. This pin connects to the switch matrix. Bandwidth Loop Circuits. This pin connects to the switch matrix. B2 34 AFE1 Analog Uncommitted Analog Front End Pin 1. B4 40 AIN4/LPF0 Analog Uncommitted Analog Input Pin 4 (AIN4). Low Power TIA Output Low-Pass Filter Capacitor Pin (LPF0). B5 36 AIN3/BUF_VREF1V8 Analog Uncommitted Analog Input Pin 3 (AIN3). connects to the switch matrix. 100 nF capacitor to this pin. connected to the output of the low power TIA. C2 35 AFE2 Analog Uncommitted Analog Front End Pin 2. C3, D3 N/A DNC Analog Do Not Connect. Do not connect to this pin. C4 42 AGND Ground Analog Ground. Short this pin to Pin E3 (AGND). C5 N/A AIN6 Analog Uncommitted Analog Input Pin 6. 100 nF capacitor to this pin. recommended capacitor value is 470 nF. Do Not Connect. Do not connect to this pin. D5 44 AGND_REF Ground Analog Reference Ground. General-Purpose Input/Output Pin 1. D8 5 AVDD_REG Supply Analog Regulator Decoupling Capacitor Pin.

Rev. C | Page 21 of 134 Pin No. Mnemonic Input/Output Supply Description AD5940 AD5941 E1 21 GPIO2 Digital input/output General-Purpose Input/Output Pin 2. E2 N/A GPIO3 Digital input/output General-Purpose Input/Output Pin 3. E3 29 AGND Ground Analog Ground. Short this pin to Pin C4. E4 to E6 13, 23, 25 DGND Ground Digital Ground. E7 17 MOSI Digital input SPI Master Output, Slave Input. E8 18 MISO Digital output SPI Master Input Slave Output. F1 22 RESET Digital input Reset Pin, Active Low. F2 30 AVDD Supply Analog 3.3 V Circuit Power. F3 6 DVDD Supply Digital Circuit Power. F4 N/A GPIO6 Digital input/output General-Purpose Input/Output Pin 6. F5 19 GPIO0 Digital input/output General-Purpose Input/Output Pin 0. F6 N/A GPIO5 Digital input/output General-Purpose Input/Output Pin 5. F7 15 CS Digital input/output SPI Chip Select. F8 16 SCLK Digital input SPI Clock. G2 26 IOVDD Supply Digital Input/Output Supply Pin. DVDD (Pin F3) must be driven before IOVDD is enabled. G3 14 DVDD_REG_1V8 Analog 1.8 V Digital Regulator Decoupling Capacitor Pin. Connect a 470 nF capacitor to this pin. G4 N/A GPIO7 Digital input/output General-Purpose Input/Output Pin 7. G5 11 XTALI Digital Input 16 MHz External Crystal Input Pin. G6 12 XTALO Digital output 16 MHz External Crystal Output Pin. G7 N/A GPIO4 Digital input/output General-Purpose Input/Output Pin 4.

Figure 7. Magnitude vs. Frequency, ADC 1.82 V Voltage Reference AC Figure 8. Magnitude vs. Frequency, Low Power 2.5 V Voltage Reference Figure 9. Low Power Reference (2.5 V) vs. Supply Voltage, Figure 10. High Power Reference vs. Supply Voltage,

1.11 V Voltage Reference DC PSRR

Figure 11. High Power Reference vs. Supply Voltage, Figure 12. Low Power Potentiostat Input Bias Current (IBIAS) vs. RE0 Pin

Figure 18. High Speed Loop Connected to Sensor (R1, R2, and R3), C1 and C2 Represent Capacitance to Ground

Low power, dual-output, string DAC used to set the sensor bias voltage and low frequency excitation. Supports chronoamperometric and voltammetry electrochemical techniques.
Low power potentiostat that applies the bias voltage to the sensor.
Low power TIA that performs low bandwidth current measurements.
High speed DAC and amplifier designed to generate excitation signals for impedance measurements up to 200 kHz.
High speed TIA that supports wider signal bandwidth measurements.
High performance ADC circuit (see the High Performance ADC Circuit section).
Programmable switch matrix. The input switching of the AD5940/AD5941 allows full configurability in the connections of the external sensors (see the Programmable Switch Matrix section).
Programmable sequencer (see the Sequencer section).
SPI interface.
Waveform generator designed to create sinusoid and trapezoid waveforms up to 200 kHz (see the Waveform Generator section).
Interrupt sources that output to a GPIOx pin to alert the host controller that an interrupt event occurred (see the Interrupts).
Digital inputs/outputs (see the Digital Inputs/Outputs section). CONFIGURATION REGISTERS

Table 8. Configuration Registers Summary Table 9. Bit Descriptions for AFECON Register 0 Disables the dc DAC buffer. 1 Enables the dc DAC buffer. 0 Reference disable. Clear to 0 to disable the high speed DAC reference. 1 Reference enable. Set to 1 to enable the high speed DAC reference. drawn from the battery while charging the capacitor on the AVDD_REG pin. 0 Analog LDO buffer current limiting enabled. 1 Analog LDO buffer current limiting disabled. 0 Supply rejection filter disabled. Disables sinc2 (50 Hz/60 Hz digital filter). Disable this bit for impedance measurements. 1 Supply rejection filter enabled. Enables sinc2 (50 Hz/60 Hz digital filter). 0 DFT hardware accelerator disabled. 1 DFT hardware accelerator enabled.

Rev. C | Page 26 of 134 Bits Bit Name Settings Description Reset Access 14 WAVEGENEN Waveform generator enable. This bit enables the waveform generator. 0x0 R/W 0 Waveform generator disabled. The waveform generator includes a sinusoid wave and a trapezoid wave. 1 Waveform generator enabled. 13 TEMPCONVEN ADC temperature sensor convert enable. This bit enables the temperature reading. If this bit is set to 1, a temperature reading is initiated. When the temperature conversion is complete, the result available in the TEMPSENSDAT register. 0x0 R/W 0 Temperature reading disabled. 1 Temperature reading enabled. 12 TEMPSENSEN ADC temperature sensor channel enable. This bit enables the temperature sensor. 0x0 R/W 0 Temperature sensor disabled. The temperature sensor is powered down. 1 Temperature sensor enabled. The temperature sensor is powered up. Temperature readings are not performed unless TEMPCONVEN = 1. 11 TIAEN High speed TIA enable. This bit enables the high speed TIA. 0x0 R/W 0 High speed TIA disabled. 1 High speed TIA enabled. 10 INAMPEN Excitation instrumentation amplifier enable. This bit enables the instrumentation amplifier. 0x0 R/W 0 Programmable instrumentation amplifier disabled. 1 Programmable instrumentation amplifier enabled. 9 EXBUFEN Excitation buffer enable. This bit enables the excitation buffer to drive the resistance being measured. 0x0 R/W 0 Excitation buffer disabled. 1 Excitation buffer enabled. 8 ADCCONVEN ADC conversion start enable. 0x0 R/W 0 ADC idle. The ADC is powered on, but is not converting. 1 ADC conversions enabled. 7 ADCEN ADC power enable. This bit enables the ADC. 0x0 R/W 0 ADC disabled. The ADC is powered off. 1 ADC enabled. The ADC is powered on. The ADCCONVEN bit must be set to 1 to start conversions. 6 DACEN High speed DAC enable. This bit enables the high speed DAC, the corresponding reconstruction filter, and the attenuator. This bit only enables the analog block and does not include the DAC waveform generator. 0x0 R/W 0 High speed DAC disabled. 1 High speed DAC enabled. 5 HSREFDIS High speed reference disable. This bit is the power-down signal of the high power reference. Set this bit to 1 to power down the reference. 0x0 R/W 0 High power reference enabled. 1 High power reference disabled. [4:0] Reserved Reserved. 0x0 R

The power mode configuration register, PMBW, configures the high and low power system modes for the high speed DAC and ADC circuits. Table 10. Bit Descriptions for PMBW Register automatically configured according to the waveform generator frequency. antialias filter cutoff = 250 kHz. 01 Sets cutoff frequency to 50 kHz, −3 dB bandwidth. 10 Sets cutoff frequency to 100 kHz, −3 dB bandwidth. 11 Sets cutoff frequency to 250 kHz, −3 dB bandwidth. 0 Low power mode. Clear this bit for impedance measurements of <80 kHz. 1 High speed mode. Set this bit for impedance measurements of >80 kHz.

(Bits[3:0]). The device identifier changes with silicon revision. Table 11. Identification Registers Summary Table 12. Bit Descriptions for ADIID Register Table 13. Bit Descriptions for CHIPID Register

Table 14. AD5940/AD5941 Initialization

Rev. C | Page 30 of 134 LOW POWER DAC The ultra low power DAC is a dual output string DAC that sets the bias voltage of the sensor. There are two output resolution formats: 12-bit resolution (VBIAS0) and 6-bit resolution (VZERO0). In normal operation, the 12-bit output sets the voltage on the reference electrode and counter electrode pins, RE0 and CE0, via the potentiostat circuit. This voltage can also be sent to the VBIAS0 pin by configuring the SW12 switch (see Figure 23). An external filtering capacitor can be connected to the VBIAS0 pin. The 6-bit output sets the voltage to the positive low power TIA internal node that connects to the ADC mux, LPTIA_P. The voltage on the sense electrode is equal to this pin. This voltage is referred to as VZERO0 and can be connected to the VZERO0 pin by configuring the SW13 switch (see Figure 23). In diagnostic mode, the VZERO0 output can also be connected to the high speed TIA by setting Bit 5 in the LPDACCON0 register to 1. The low power DAC reference source is a low power, 2.5 V reference. The low power DACs are made up of two 6-bit string DACs. The main 6-bit string DAC provides the VZERO0 DAC output, and is made up of 63 resistors. Each resistor is the same value. The main 6-bit string with the 6-bit subDAC provides the VBIAS0 DAC output. In 12-bit mode, the MSBs select a resistor from the main string DAC. The top end of this resistor is selected as the top of the 6-bit subDAC, and the bottom end of the selected resistor is connected to the bottom of the 6-bit subDAC string, as shown in Figure 19. The resistor matching between the 12-bit and 6-bit DACs means 64 LSB 12 (VBIAS0) is equal to one LSB6 (VZERO0). The output voltage range is not rail to rail. Rather, it ranges from 0.2 V to 2.4 V for the 12-bit output of the low power DAC. Therefore, the LSB value of the 12-bit output (12-BIT_ DAC_LSB) is 12-BIT_DAC_LSB = 2.2 V 21 − = 537.2 µV The 6-bit output range is from 0.2 V to 2.366 V . This range is not 0.2 V to 2.4 V because there is a voltage drop across R1 in the resistor string (see Figure 19). The LSB value of the 6-bit output (6-BIT_DAC_LSB) is 6-BIT_DAC_LSB = 12-BIT_DAC_LSB × 64 = 34.38 mV To set the output voltage of the 12-bit DAC, write to LPDACDAT0, Bits[11:0]. To set the 6-bit DAC output voltage, write to LPDACDAT0, Bits[17:12]. If the system clock is 16 MHz, LPDACDAT0 takes 10 clock cycles to update. If system clock is 32 kHz, LPDACDAT0 takes one clock cycle to update. Take these values into consideration when using the sequencer. The following code demonstrates how to correctly set the LPDACDAT0 value: SEQ_WR(REG_AFE_LPDACDAT0, 0x1234); SEQ_WAIT(10); // Wait 10 clocks for LPDADAT0 to update SEQ_SLP(); Optionally, the waveform generator described in the Waveform Generator section can be used as the DAC codes source for the low power DAC. When using the waveform generator with the low power DAC, ensure that the settling time specification of the low power DAC is not violated. The system clock source must be the 32 kHz oscillator. This feature is provided for ultra low power, always on, low frequency measurements, such as skin impedance measurements where the excitation signal is approximately 100 Hz and system power consumption needs to be <100 μA. LOW POWER DAC SWITCH OPTIONS There are a number of switch options available that allow the user to configure the low power DAC for various modes of operation. These switches facilitate different use cases, such as electrochemical impedance spectroscopy. Figure 23 shows the available switches, labeled SW0 to SW4. These switches are controlled either automatically via Bit 5 in the LPDACCON0 register, or individually via the LPDACSW0 register When LPDACCON0, Bit 5, is cleared, the switches are configured for normal mode. The SW2 switch and the SW3 switch are closed and the SW0, SW1, and SW4 switches are open. When LPDACCON0, Bit 5, is set, the switches are configured for diagnostic mode. The SW0 switch and the SW4 switch are closed and the remaining switches are open. This feature is designed for electrochemical use cases, such as continuous glucose measurement where, in normal mode, the low power TIA measures the sense electrode. Then, in diagnostic mode, the high speed TIA measures the sense electrode. By switching the V ZERO0 voltage output from the low power TIA to the high speed TIA, the effective bias on the sensor, VBIAS0 − VZERO0, is unaffected. Using the high speed TIA facilitates high bandwidth measurements, such as impedance, ramp, and cyclic voltammetry. Use the LPDACSW0 register to control the switches individually. LPDACSW0, Bit 5, must be set to 1. Then, each switch can be individually controlled via LPDACSW0, Bits[4:0].

buffers must also be enabled by setting AFECON, Bit 21. voltage for the high speed DAC excitation buffer. Figure 21. Low Power DACs Used in a 4-Wire Impedance Measurement (HSTIA_P = Positive Output of High Speed TIA) Table 15. Low Power TIA and Low Power DAC Registers Summary Table 16. Bit Descriptions for LPDACCON0 Register

output switch operation. See the Low Power DAC section for more information. mode switch settings. See the Low Power DAC section for more information. VZERO0 node. Ensure that the same value is written to the VBIASMUX bit. 0 VZERO0, 6-bit (default). Clear this bit to 0 for the VZERO0 voltage output to be 6-bit. 1 VZERO0, voltage 12-bit. Set this bit to 1 for the VZERO0 voltage output to be 12-bit. to the VBIAS0 node. Ensure that the same value is written to the VZEROMUX bit. 0 Output, 12-bit (default). The 12-bit DAC is connected to VBIAS0 voltage. 1 Output, 6-bit. The 6-bit DAC is connected to VBIAS0 voltage. 0 Selects the low power 2.5 V reference as the low power DAC reference source. 1 Selects AVDD as the low power DAC reference source. 0 Low Power DAC powered on. Clear this bit to 0 to power on the low power DAC. opens all switches on the low power DAC output. always 0. Writes to LPDACDAT0 are disabled. 1 Enables low power DAC writes. Set this bit to 1 to enable writes to LPDACDAT0. Table 17. Bit Descriptions for LPDACSW0 Register

0 Disconnects the direct connection of the VBIAS0 DAC output to the positive input

of the potentiostat amplifier (default).

1 Connects the VBIAS0 DAC voltage output directly to the positive input of the

1 Connects the VBIAS0 DAC voltage output to the low-pass filter/VBIAS0 pin (default). 2 SW2 Low power DAC SW2 switch control.

0 Disconnects the direct connection of the VZERO0 DAC voltage output to the low

power TIA positive input (default).

1 Connects the VZERO0 DAC voltage output directly to the low power TIA positive

1 Connects the VZERO0 DAC voltage output to the low-pass filter/VZERO0 pin (default).

0 Disconnects the VZERO0 DAC voltage output from the high speed TIA positive input

1 Connects the VZERO0 DAC voltage output to the high speed TIA positive input. Table 18. Bit Descriptions for LPDACDAT0 Register and 0x3F sets the 6-bit output voltage. 0 Sets output voltage to 0.2 V. 111111 Sets output voltage to 2.366 V. and 0xFFF sets the 12-bit output voltage. 0 Sets output voltage to 0.2 V. 0xFFF Sets output voltage to 2.4 V. Table 19. Bit Descriptions for LPREFBUFCON Register 0 Enables the low power 2.5 V buffer. 1 Powers down the low power 2.5 V buffer. 0 Low power reference enabled. 1 Low power reference powered down. Table 20. Bit Descriptions for SWMUX Register

1 Enables the common-mode switches with a 10 MΩ resistor to set up the common-

Rev. C | Page 35 of 134 LOW POWER POTENTIOSTAT The AD5940/AD5941 has a low power potentiostat that sets and controls the bias voltage of an electrochemical sensor. Typically, the output of the potentiostat is connected to CE0. The noninverting input is connected to VBIAS0 voltage and the inverting input is connected to RE0 as shown in Figure 20. For an electrochemical cell, the potentiostat maintains the bias voltage on the reference electrode (RE0) by sourcing or sinking current through the counter electrode (CE0). The output of the potentiostat can be connected to various package pins through the switch matrix (see the Programmable Switch Matrix section for details). There are a number of configurable switch options around the potentiostat to provide numerous configuration options (see Figure 23). The potentiostat can also be used a standard buffer output to output V BIAS0 voltage onto CE0. To achieve this, the inverting input is connected to the output of the potentiostat by closing the SW10 switch, as shown in Figure 23.

Table 21. Recommended Switch Settings in Low Power Potentiostat Loop tors to the VBIAS0 and VZERO0 DACs are connected. power TIA back to back diode protection enabled. VBIAS0 output generates pulse to CE0 electrode. Capacitors on low power DACs are disconnected. Low power TIA measures SE0 current response. VBIAS0 output generates pulse to CE0 electrode. Capacitors on VBIAS0 and VZERO0 are disconnected. High speed TIA measures SE0 current response. VBIAS0 output generates pulse to CE0 electrode. Capacitors on VBIAS0 and VZERO0 are disconnected. BIAS0 or VZERO0 DAC outputs.

Figure 23. Low Bandwidth Loop Switches

Table 22. Low Power TIA and DAC Registers Summary Table 23. Bit Descriptions for LPTIASW0 Register

Table 24. Bit Descriptions for LPTIACON0 Register output low-pass filter cutoff frequency.

0 Disconnects the TIA output from the low-pass filter pin (LPF0), which is useful for

disconnects the low power TIA output from the low-pass filter capacitor. 1 Bypass resistor; 0 Ω option. setting is the lowest cutoff frequency setting for the low-pass filter. 1 200 Ω. The RTIA is combination of RLOAD and a fixed series 110 Ω. Assumes RLOAD = 10 Ω. Set by the TIARL bits. RTIA = 100 Ω − RLOAD + 110 Ω. The fixed overall RTIA = 200 Ω.

Rev. C | Page 41 of 134 Bits Bit Name Settings Description Reset Access 1001 12 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 12 kΩ. If RLOAD > 100 Ω, RTIA = 12 kΩ − (RLOAD − 100 Ω). 1010 16 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 16 kΩ. If RLOAD > 100 Ω, RTIA = 16 kΩ − (RLOAD − 100 Ω). 1011 20 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 20 kΩ. If RLOAD > 100 Ω, RTIA = 20 kΩ − (RLOAD − 100 Ω). 1100 24 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 24 kΩ. If RLOAD > 100 Ω, RTIA = 24 kΩ − (RLOAD − 100 Ω). 1101 30 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 30 kΩ. If RLOAD > 100 Ω, RTIA = 30 kΩ − (RLOAD − 100 Ω). 1110 32 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 32 kΩ. If RLOAD > 100 Ω, RTIA = 32 kΩ − (RLOAD − 100 Ω). 1111 40 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 40 kΩ. If RLOAD >100 Ω, RTIA = 40 kΩ − (RLOAD − 100 Ω). 10000 48 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 48 kΩ. If RLOAD > 100 Ω, RTIA = 48 kΩ − (RLOAD − 100 Ω). 10001 64 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 64 kΩ. If RLOAD > 100 Ω, RTIA = 64 kΩ − (RLOAD − 100 Ω). 10010 85 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 85 kΩ. If RLOAD > 100 Ω, RTIA = 85 kΩ − (RLOAD − 100 Ω). 10011 96 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 96 kΩ. If RLOAD > 100 Ω, RTIA = 96 kΩ − (RLOAD − 100 Ω). 10100 100 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 100 kΩ. If RLOAD > 100 Ω, RTIA = 100 kΩ − (RLOAD − 100 Ω). 10101 120 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 120 kΩ. If RLOAD > 100 Ω, RTIA = 120 kΩ − (RLOAD − 100 Ω). 10110 128 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 128 kΩ. If RLOAD > 100 Ω, RTIA = 128 kΩ − (RLOAD − 100 Ω). 10111 160 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 160 kΩ. If RLOAD > 100 Ω, RTIA = 160 kΩ − (RLOAD − 100 Ω). 11000 196 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 196 kΩ. If RLOAD > 100 Ω, RTIA = 196 kΩ − (RLOAD − 100 Ω). 11001 256 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 256 kΩ. If RLOAD > 100 Ω, RTIA = 256 kΩ − (RLOAD − 100 Ω). 11010 512 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 512 kΩ. If RLOAD > 100 Ω, RTIA = 512 kΩ − (RLOAD − 100 Ω). [4:3] IBOOST Current boost control. 0x0 R/W 00 Normal mode. 01 Increase amplifier output stage current to quickly charge external capacitor load. This setting is intended for use with high current sensors.

10 Double TIA and potentiostat amplifier overall quiescent current and increase

amplifier bandwidth. This setting is useful for diagnostic tests.

11 Double TIA and potentiostat amplifier overall quiescent current and increase

output stage current. This setting increases amplifier bandwidth and output current capability. 2 HALFPWR Half power mode select. This control bit reduces the active power consumption of the TIA and potentiostat amplifier for Sensor Channel 0. 0x0 R/W 0 Normal mode (default). 1 Reduces and TIA current by half. 1 PAPDEN Potentiostat amplifier power-down. Low power potentiostat power-down control bit. 0x1 R/W 0 Power-up. 1 Power-down. 0 TIAPDEN TIA power-down. Low power TIA power-down control bit. 0x1 R/W 0 Power-up. 1 Power-down.

Rev. C | Page 42 of 134 HIGH SPEED DAC CIRCUITS The 12-bit high speed DAC generates an ac excitation signal when measuring the impedance of an external sensor. Control the DAC output signal directly by writing to a data register or by using the automated waveform generator block. The high speed DAC signal is fed to an excitation amplifier designed specifically to couple the ac signal on top of the normal dc bias voltage of a sensor. HIGH SPEED DAC OUTPUT SIGNAL GENERATION There are two ways of setting the output voltage of the high speed DAC, as follows:

A direct write to the DAC code register, HSDACDAT. This register is a 12-bit register where the most significant bit (MSB) is a sign bit. Writing 0x800 results in a 0 V output. Writing 0x200 results in negative full-scale, and writing 0xE00 results in positive full-scale. The following equation can be used for calculating the output voltage: OUT × 404.4mV × INAMPGNMDE × ATTENEN where: VOUT is the voltage at the output of the excitation amplifier. HSDACDAT is the 12-bit HSDAC code register value. INAMPGNMDE is the gain setting of the excitation amplifier. The setting can be 2 or 0.25. ATTENEN is the attenuator setting. The setting can be 1 or 0.2.
Use the automatic waveform generator. The waveform generator can be programmed to generate fixed frequency, fixed amplitude signals including, sine, trapezoid, and square wave signals. If the user selects the sine wave, options exist to adjust the offset and phase of the output signal. The following equation can be used to calculate the sine wave amplitude: () 1121 ppOUT WGAMPLITUDEV − × 808.8mV × INAMPGNMDE × ATTENEN where: VOUT(p-p) is the peak-to-peak voltage of the ac signal. WGAMPLITUDE is the 12-bit HSDAC code register value. INAMPGNMDE is the gain setting of the excitation amplifier. The setting can be 2 or 0.25. ATTENEN is the attenuator setting. The setting can be 1 or 0.2. POWER MODES OF THE HIGH SPEED DAC CORE The reference source of the high speed DAC is an internal 1.82 V precision reference voltage (VREF_1V82 pin). There are three basic modes of operation for the high speed DAC that trade off between power consumption vs. output speed: low power mode, high power mode, and hibernate mode. The high speed DAC can also be placed into hibernate mode when inactive. Low Power Mode Low power mode is used when the high speed DAC output signal frequency is <80 kHz. When configuring the high speed DAC for low power mode, take the following steps: 1. Clear the PMBW register (Bit 0 = 0). 2. In this mode, the system clock to the high speed DAC and the ADC is 16 MHz. 3. Ensure that CLKSEL, Bits[1:0] = 0 to select a 16 MHz, internal, high frequency oscillator clock source. Ensure the system clock divide ratio is 1 (CLKCON0, Bits[5:0] = 0 or 1. 4. If the internal high speed oscillator is selected as the system clock source, ensure that the 16 MHz option is selected. Set HSOSCCON, Bit 2 = 1. High Power Mode High power mode increases the bandwidth supported by the high speed DAC amplifiers. Use high power mode when the high speed DAC frequency is greater than 80 kHz. To enter high power mode, a number of register writes are required. To configure the high speed DAC for high power mode, take the following steps: 1. Set the PMBW register, Bit 0 = 1. Power consumption is increased, but the output signal bandwidth increases to a maximum of 200 kHz. In high power mode, the system clock to the DAC and the ADC is 32 MHz. 2. Ensure that CLKSEL Bits[1:0] select a 32 MHz clock source. For example, to select an internal high speed oscillator, set CLKSEL Bits[1:0] (SYSCLKSEL) = 00. Ensure that the system clock divide ratio is 1 (CLKCON0 Bits[5:0] = 0 or 1). 3. If the internal high speed oscillator is selected as the system clock source, ensure that the 32 MHz option is selected. Clear HSOSCCON, Bit 2 = 0. Hibernate Mode When the AD5940/AD5941 enter hibernate mode, the clocks to the high speed DAC circuits are clock gated to save power. When in active mode and the high speed DAC is not in use, disable the clocks to save power. HIGH SPEED DAC FILTER OPTIONS The output stage of the high speed DAC features a configurable reconstruction filter. The configuration of the reconstruction filter is dependent on the output signal frequency of the DAC.

frequency is higher than the required DAC output frequency.

PMBW Bits[3:2] = 01 for optimal performance if the DAC update frequency is ≤50 kHz.
PMBW Bits[3:2] = 10 for optimal performance if the DAC update rate is ≤100 kHz.
PMBW Bits[3:2] = 11 for optimal performance if the DAC update rate is up to 250 kHz.

Figure 24. High Speed DAC Block

Table 25. High Speed DAC Control Registers Summary Table 26. Bit Descriptions for HSDACCON Register 0 DAC attenuator disabled. Gain of 1 mode. 1 DAC attenuator enabled. Gain of 0.2 mode. Table 27. Bit Descriptions for HSDACDAT Register code is 0xE00. Midscale (0x800) corresponds to an output voltage of 0 V. Table 28. High Speed DAC Calibration Registers Summary Table 29. High Speed DAC Calibration Register Assignment

Table 30. Bit Descriptions for CALDATLOCK Register the overwriting of data after the calibration phase. Write this value to unlock the calibration registers. Protected by CALDATLOCK. Valid for all settings of HSDACCON, Bit 12 and HSDACCON, Bit 0. Table 31. Bit Descriptions for DACGAIN 0x000 Maximum negative gain adjustment occurs. 0xFFF Maximum positive gain adjustment occurs. for HSDACCON, Bit 12 = 1 and HSDACON, Bit 0 = 0. Table 32. Bit Descriptions for DACOFFSETATTEN complement format with 0.5 LSB precision. Used when the attenuator is enabled. 0x001 0.5. Results in a 0.5 LSB adjustment. 0x000 0. No offset adjustment. 0xFFF −0.5. Results in a −0.5 LSB adjustment. 0x800 −210. Maximum negative adjustment that results in negative full scale/2 adjustment. 39.5 μV for HSDACCON, Bit 12 = 0 and HSDACCON, Bit 0 = 1. Table 33. Bit Descriptions for DACOFFSET Register complement format with 0.5 LSB precision. Used when the attenuator is disabled. 0x001 0.5. Results in a 0.5 LSB adjustment. 0x000 0. No offset adjustment. 0xFFF −0.5. Results in a −0.5 LSB adjustment. 0x800 −210. Maximum negative adjustment that results in negative full scale/2 adjustment.

adjustment is typically 24.7 μV for HSDACCON, Bit 12 = 1 and HSDACCON, Bit 0 = 0. Table 34. Bit Descriptions for DACOFFSETATTENHS Register complement format with 0.5 LSB precision. Used when the attenuator is enabled. 0x001 0.5. Results in a 0.5 LSB adjustment. 0x000 0. No offset adjustment. 0xFFF −0.5. Results in a −0.5 LSB adjustment. adjustment is typically 39.5 μV for HSDACCON, Bit 12 = 0 and HSDACCON, Bit 0 = 1. Table 35. Bit Descriptions for DACOFFSETHS complement format with 0.5 LSB precision. Used when the attenuator is disabled. 0x001 0.5. Results in a 0.5 LSB adjustment. 0x000 0. No offset adjustment. 0xFFF −0.5. Results in a −0.5 LSB adjustment.

Table 36. High Speed TIA Resistor Options on the DE0 Input

Table 37. High Speed TIA Registers Summary Table 38. Bit Descriptions for HSRTIACON Register diode in parallel with RTIA. 0 SW6 off, diode is not in parallel with RTIA. 1 SW6 on, diode is in parallel with RTIA. Bit 17) and open the T10 switch (SWCON, Bit 17). Table 39. Bit Descriptions for DE0RESCON Register switch, close the T10 switch, and set the RTIA resistor values (see Table 36).

Table 40. Bit Descriptions for HSTIACON Register 00 VBIAS_CAP pin 1.11 V voltage source. 01 VZERO0 output from low power DAC.

Rev. C | Page 54 of 134 ADC CIRCUIT FEATURES An input multiplexer, located in front of the high speed, multichannel, 16-bit ADC, enables the measurement of a number of external and internal channels. These channels include the following:

Two low power current measurement channels. These channels measure the low current outputs of the connected sensor through the SE0 pin or DE0 pin. The current channels feed into a programmable load resistor.
One low power TIA. The low power TIA has its own programmable gain resistor to convert very small currents to a voltage signal that can be measured by the ADC. The low power current channel can be configured to sample with or without a low-pass filter in place.
One high speed current input channel for performing impedance measurements up to 200 kHz. The high speed current channel has a dedicated high speed TIA with a programmable gain resistor.
Multiple external voltage inputs.
Six dedicated voltage input channels: AIN0, AIN1, AIN2, AIN3/BUF_VREF1V8, AIN4/LPF0, and AIN6 (AD5940 only).
The sensor electrode pins, SE0, DE0, RE0, and CE0, can also be measured as ADC voltage pins. Divide by 2 options are available on the CE0 pin.
Internal ADC channels.
AVDD, DVDD, and AVDD_REG power supply measurement channels.
ADC, high speed DAC, and low power reference voltage sources.
Internal die temperature sensor.
Two low power DAC output voltages, V BIAS0 and VZERO0.
ADC result post processing features.
Digital filters (sinc2 and sinc3) and 50 Hz/60 Hz power supply rejection. The sinc2 and sinc3 filters have programmable oversampling rates to allow the user to trade off conversion speed vs. noise performance.
Discrete Fourier transform (DFT), used with impedance measurements to automatically calculate magnitude and phase values.
Programmable averaging of ADC results to separate the sinc2 and sinc3 filters.
Programmable statistics option for calculating mean and variance automatically.
Multiple calibration options to support system calibration of the current, voltage, and temperature channels. The ADC input stage provides an input buffer to support low input current leakage specifications on all channels. To support a range of current and voltage based input ranges, the ADC front end provides a PGA and a TIA. The PGA supports gains of 1, 1.5, 2, 4, and 9. The low power TIA supports programmable gain resistors ranging from 200 Ω to 512 kΩ. The high speed TIA used for impedance measurement supports programmable gain resistors ranging from 200 Ω to 160 kΩ. By default, the reference source of the ADC is a precision, low drift, internal 1.82 V reference source. Optionally, an external reference can be connected to the VREF_1.82V pin and the AGND_REF pin. The ADC supports averaging and digital filtering options. The user can trade off speed vs. precision by using these options. The highest ADC update rate is 800 kHz in normal mode and 1.6 MHz in high speed mode, with no digital filtering. The ADC filtering options also include a 50 Hz/60 Hz mains power supply filter. With this filter enabled, the ADC update rate is typically 900 Hz. The ADC supports a number of post processing features, including a DFT engine intended for impedance measurements to remove the processing requirements from the host microcontroller. Minimum, maximum, and mean value detection is also supported. ADC CIRCUIT OPERATION The SAR ADC is based on a charge redistribution DAC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two inputs of the comparator. The ADC block operates from the 16 MHz clock in normal operation and samples at 800 kSPS. The postprocessing sinc3 and sinc2 filters reduce this output sampling rate. It is recommended to use a sinc3 oversampling rate of 4, which gives an output data rate of 200 kSPS. For high power mode, the 32 MHz oscillator must be selected as the ADC clock source. The ADC maximum update rate is

1.6 MSPS with higher power consumption, which is only

required for impedance measurements in the >80 kHz range. ADC TRANSFER FUNCTION The transfer function in Figure 33 shows the ADC output codes on the y-axis vs. the differential voltage into the ADC. In Figure 33, the ADC negative input channel is the 1.11 V voltage source. The positive input channel is any voltage input to the ADC after the TIA or PGA and/or input buffer stages.

Figure 33. Ideal ADC Transfer Function, Output Codes vs. Voltage Input when Calculate the input voltage, VIN, with the following equations.

1.835 V 0x8000 __2

VREF is the ADC reference voltage (1.82 V typical). PGA_G is the PGA gain and is selectable as 1, 1.5, 2, 4, or 9. ADCDAT is the raw ADC code in the ADCDAT register. ADC measures the output voltage of the low power TIA. The positive inputs can be selected via ADCCON, Bits[5:0]. cutoff frequency of the antialias filter is set by PMBW , Bits[3:2]. Set the cutoff frequency to suit the input signal bandwidth. depends on the ADC input channel selected.

1 MΩ and the external capacitor is recommended to be 1 µF ,

which provides a low cutoff frequency. Figure 34. Low Power TIA Current Input Channel to the ADC

Voltage measurement
Positive mux select = CE0, RE0, SE0, DE0, and AINx
Negative mux select = VBIAS_CAP pin
DC current measurement on low power TIA
Positive mux select = low-pass filter of low power TIA
Negative mux select =LPTIA_N node
AC or higher bandwidth current measurements on the low power TIA
Positive mux select = LPTIA_P node
MUXSEL_N = LPTIA_N node
Current and impedance measurement on the high speed TIA
MUXSEL_P = positive high speed TIA output
MUXSEL_N = negative high speed TIA input 0.2V 0x0000 0x4000 0x8000 0xC000 0xFFFF16-BIT ADC HEX CODE 1.11V 2.02V 16778-021 LPTIA RTIA RLOAD RLPF ADC MUX SE0 AIN4/ LPF0 VZERO 16778-022

the postprocessing filter options.

Digital filtering (sinc2 or sinc3) and 50 Hz or 60 Hz power supply rejection.
DFT used with impedance measurements to automatically calculate magnitude and phase values.
Programmable averaging of ADC results.
Programmable statistics option for calculating mean and variance automatically. Sinc3 Filter The input to the sinc3 filter is the raw ADC codes at a rate of 800 kHz (if the 16 MHz oscillator is selected) or 1.6 MHz (if the 32 MHz oscillator is selected). If the ADC clock is 32 MHz, ADCFILTERCON (Bit 0) = 0. This setting ensures that the sinc3 block functions correctly with the 1.6 MHz data rate. To enable the sinc3 filter, ensure that ADCFILTERCON, Bit 6 = 0. The filter decimation rate is programmable with options of 2, 4, or 5. It is recommended to use a decimation rate of 4. The gain correction block is enabled by default and is not user programmable. INTERNAL TEMPERATURE SENSOR CHANNEL The AD5940/AD5941 contains an internal temperature sensor channel. The temperature sensor outputs a voltage proportional to die temperature. This voltage is linear relative to temperature. This internal channel is measured via the ADC by selecting the temperature sensor channels as the positive and negative inputs from the mux. The die temperature is calculated by the following: (TEMPSENSDAT0/(PGA Gain × K)) − 273.15 (2) where K = 8.13. For improved accuracy, configure the temperature sensor in chop mode via TEMPCON0, Bits[3:1]. If chopping is selected, the user must ensure an even number of ADC conversions take place on the temperature sensor channel and that these results are averaged. Dedicated calibration registers for the temperature sensor channel are also available. When the ADC selects the temperature sensor as the positive input, the calibration values in the ADCOFFSETTEMPSENS0 and ADCGAINTEMPSENS0 registers are automatically used. To enable the internal temperature sensor, set AFECON, Bit 12 = 1. Select ADC input channels as follows:
ADCCON, Bits[12:8] = 1011 selects the ADC negative input channel.
ADCCON, Bits[5:0] = 001011 selects the positive input channel. To start an ADC conversion of the temperature sensor channel, set AFECON, Bit 13 and AFECON, Bit 8 to 1. For optimal temperature sensor results, enable chop mode of the tempera- ture sensor with the 6.25 kHz chopping frequency. Then, average an even number of ADC temperature sensor results to eliminate any inaccuracies caused by the chopping clock. SINC2 FILTER (50 HZ/60 HZ MAINS FILTER) To enable the 50 Hz or 60 Hz notch filter for filtering mains noise, clear ADCFILTERCON, Bit 4 = 0 and set AFECON, Bit 16 = 1. The input is the sinc2 filter output. The input rate is dependent on the sinc3 and sinc2 settings. If selected, the sinc2 filter output can be read via the SINC2DAT register. Table 41 describes the digital filter settings that support simultaneous 50 Hz or 60 Hz mains rejection. ADC CALIBRATION Because of the multiple input types on the AD5940/AD5941 (for example, current, voltage, and temperature), there are multiple offset and gain calibration options. A built in, self calibration system is provided to aid the user when calibrating different ADC input channels, which is included in the AD5940/AD5941 software development kit.

Table 41. Digital Filter Settings to Support Simultaneous 50 Hz/60 Hz Mains Rejection

16 MHz 5 178 900 SPS 37 ms

16 MHz 2 667 600 SPS 37 ms

16 MHz 2 1333 300 SPS 37 ms

32 MHz 2 1333 600 SPS 37 ms

Figure 35. Postprocessing Filter Options Table 42. ADC Control Registers Summary Table 43. Bit Descriptions for ADCFILTERCON Register 0 2 ADC samples used for the average function. 1 4 ADC samples used for the average function. 10 8 ADC samples used for the average function. 11 16 ADC samples used for the average function.

2 TO 16,384

update rate and when the ADC update rate is 800 kSPS (default). update rate and when the ADC update rate is 1.6 MSPS. High power option. update rate and when the ADC update rate is 800 kSPS. update rate and when the ADC update rate is 800 kSPS. 0 22 samples for this OSR setting. 1 44 samples for this OSR setting. 10 89 samples for this OSR setting. 11 178 samples for this OSR setting. 100 267 samples for this OSR setting. 101 533 samples for this OSR setting. 110 640 samples for this OSR setting. 111 667 samples for this OSR setting. 1000 800 samples for this OSR setting. 1001 889 samples for this OSR setting. 1010 1067 samples for this OSR setting. 1011 1333 samples for this OSR setting.

7 AVRGEN

1 Enable average to feed to the DFT block. the gain offset block output is used as the DFT input.

5 Reserved Reserved 0x0 R

1 Bypasses the 50 Hz notch and 60 Hz notch filters. must be 32 MHz (refer to the clock configuration). The ADCDAT register is the ADC result register for the raw ADC output or when the sinc3 and/or sinc2 filter options are selected. Table 44. Bit Descriptions for ADCDAT Register

Table 45. Bit Descriptions for DFTREAL Register part of the DFT result. The DFT result is represented in twos complement format. Table 46. Bit Descriptions for DFTIMAG Register part of the DFT result. The DFT result is represented in twos complement format. Table 47. Bit Descriptions for SINC2DAT Register INTCFLAG2 registers, Bit 2 is set to 1. Table 48. Bit Descriptions for TEMPSENSDAT Register Table 49. Bit Descriptions for DFTCON Register input, regardless of the DFTINSEL setting. 00 Sinc2 filter output. Select the output from the Sinc2 filter. the sinc3 output through gain/offset correction is the DFT input. ADC raw data. Selects the output direct from the ADC; no offset/gain correction. Only supported for an ADC sample rate of 800 kHz. 11 Sinc2 filter output. Select the output from the Sinc2 filter Same as 00.

0 DFT point number is 4. DFT uses 4 ADC samples. 1 DFT point number is 8. DFT uses 8 ADC samples. 10 DFT point number is 16. DFT uses 16 ADC samples. 11 DFT point number is 32. DFT uses 32 ADC samples. 100 DFT point number is 64. DFT uses 64 ADC samples. 101 DFT point number is 128. DFT uses 128 ADC samples. 110 DFT point number is 256. DFT uses 256 ADC samples. 111 DFT point number is 512. DFT uses 512 ADC samples. 1000 DFT point number is 1024. DFT uses 1024 ADC samples. 1001 DFT point number is 2048. DFT uses 2048 ADC samples. 1010 DFT point number is 4096. DFT uses 4096 ADC samples. 1011 DFT point number is 8192. DFT uses 8192 ADC samples. 1100 DFT point number is 16,384. DFT uses 16,384 ADC samples. Table 50. Bit Descriptions for TEMPSENS Register 00 Chop switch frequency = 6.25 kHz. 01 Chop switch frequency = 25 kHz. 10 Chop switch frequency = 100 kHz. 11 Chop switch frequency = 200 kHz. reduces the offset error associated with this channel. 0 Disable temperature sensor. Table 51. Bit Descriptions for ADCCON Register

Rev. C | Page 61 of 134 Bits Bit Name Settings Description Reset Access 15 GNOFSELPGA Internal offset/gain cancellation. 0x0 R/W 0 DC offset cancellation disabled. Enables dc offset cancellation. When the PGA is enabled, only a gain value of 4 is supported. [14:13] Reserved Reserved. 0x0 R/W [12:8] MUXSELN Select signals for the ADC input multiplexer as negative input. 0x0 R/W 00000 Floating input.

00001 High speed TIA negative input

00010 Low power TIA negative input

00011 Reserved. 00100 AIN0. 00101 AIN1. 00110 AIN2. 00111 AIN3/BUF_VREF1V8. 01000 VBIAS_CAP. 01001 Reserved. 01010 Reserved. 01011 Temperature sensor negative output. TEMPSEN_N. 01100 AIN4/LPF0. 01101 Reserved. 01110 AIN6. (AD5940 only) 01111 Reserved. 10000 VZERO0 – Measured at VZERO pin. 10001 VBIAS0 – Measured at VBIAS pin. 10010 Reserved. 10011 Reserved. 10100 Negative node of excitation amplifier. 10101 Reserved. 10110 Reserved. [7:6] Reserved Reserved. 0x0 R [5:0] MUXSELP Select signals for the ADC input multiplexer as positive input. 0x0 R/W 00000 Floating input. 00001 High speed TIA positive signal. 00010 Low power TIA positive low-pass filter signal. 00011 Reserved. 00100 AIN0. 00101 AIN1. 00110 AIN2. 00111 AIN3/BUF_VREF1V8. 01000 AVDD/2. 01001 DVDD/2. 01010 AVDD_REG/2. 01011 Internal temperature sensor. 01100 VBIAS_CAP.

01101 DE0 – Measured at pin

01110 SE0 – Measured at pin

01111 AFE3. 010000 VREF_2V5/2. 010001 Reserved.

010010 VREF_1V82

010011 Negative terminal of temperature sensor (TEMPSENS_N). 010100 AIN4/LPF0. 010101 Reserved.

010110 AIN6 (AD5940 only)

010111 VZERO0 – Measured at VZERO pin

011000 VBIAS0 – Measured at VBIAS pin

011001 Voltage on CE0 pin, VCE0. 011010 Voltage on RE0 pin, VRE0.

011011 AFE4

100001 Low power TIA positive output, LPTIA_P. 100100 Positive node of excitation amplifier. Table 52. Bit Descriptions for REPEATADCCNV Register 0 Disable repeat ADC conversions. 1 Enable repeat ADC conversions. The recommended value is 0x005F3D0F in high power mode and 0x005F3D04 in low power mode. Table 53. Bit Descriptions for ADCBUFCON Bit 8 controls the offset cancellation buffers. Bit 7 controls the ADC buffers. Bit 5 controls the positive front-end buffer. Bit 4 controls the negative front-end buffer. bits when measuring signals <80 kHz. Set these bits when measuring signals >80 kHz. Bit 3 controls the offset cancellation buffers. Bit 2 controls the ADC buffers. Bit 0 controls the front-end buffers.

Table 54. ADC Calibration Registers Summary Table 55. Bit Descriptions for CALDATLOCK Register data after the calibration phase. 0xDE87A5AF Write this value to unlock the calibration registers. Table 56. Bit descriptions for ADCOFFSETLPTIA Register resolution is 0.25 LSBs of the ADCDAT LSB size. 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096.0. Maximum negative offset calibration value.

Table 57. Bit Descriptions for ADCGNLPTIA Register 0x7FFF 2. Maximum positive gain adjustment. 0x4001 1.000 061. Minimum positive gain adjustment. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default). 0x3FFF 0.999939. Minimum negative gain adjustment. 0x2000 0.5. ADC result multiplied by 0.5. 0x0001 0.000061. Maximum negative gain adjustment. 0x0000 0. Illegal value; results in an ADC result of 0. Table 58. Bit Descriptions for ADCOFFSETHSTIA Register resolution is 0.25 LSBs of the ADCDAT LSB size. 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset correction. 0x7FFF −0.25. Minimum negative offset correction. 0x4000 −4096.0. Maximum negative offset correction. Table 59. Bit Descriptions for ADCGAINHSTIA Register 0x7FFF 2. Maximum positive gain adjustment. 0x4001 1.000061. Minimum positive gain adjustment. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default). 0x3FFF 0.999939. Minimum negative gain adjustment. 0x2000 0.5. ADC result multiplied by 0.5. 0x0001 0.000061. Maximum negative gain adjustment. 0x0000 0. Illegal value; results in an ADC result of 0.

Table 60. Bit Descriptions for ADCOFFSETGN1 Register VREF = 1.82 V, the calibration resolution is 1.82/217 = 13.885 µV. 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. The ADCGAINGN1 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels. Table 61. Bit Descriptions for ADCGAINGN1 Register [14:0] Value Gain calibration for PGA gain = 1. ADC gain correction for auxiliary input channels. sign bit, and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value; results in an ADC result of 0x8000. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment. The ADCOFFSETGN1P5 register provides ADC input offset calibration with PGA gain =1.5. Table 62. Bit Descriptions for ADCOFFSETGN1P5 Register 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value.

The ADCGAINGN1P5 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels. Table 63. Bit Descriptions for ADCGAINGN1P5 Register number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value resulting in an ADC result of 0. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment. Table 64. Bit Descriptions for ADCOFFSETGN2 Register 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. PGA is enabled with gain = 2. Table 65. Bit Descriptions for ADCGAINGN2 Register number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value resulting in an ADC result of 0. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment.

0x3FFF 0.999939. Minimum negative gain adjustment. The ADCOFFSETGN4 register provides ADC input offset calibration with PGA gain = 4. Table 66. Bit Descriptions for ADCOFFSETGN4 Register 0x3FFF +4095.75. Maximum positive offset calibration value. 0x0001 +0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. PGA is enabled with gain = 4. Table 67. Bit Descriptions for ADCGAINGN4 Register number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value resulting in an ADC result of 0. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment. The ADCOFFSETGN9 register provides ADC input offset calibration with PGA gain = 9. Table 68. Bit Descriptions for ADCOFFSETGN9 Register 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum Negative Offset calibration value. 0x4000 −4096. Maximum Negative Offset calibration value.

PGA is enabled with gain = 9. Table 69. Bit Descriptions for ADCGAINGN9 Register number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value resulting in an ADC result of 0. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment. Table 70. Bit Descriptions for ADCOFFSETTEMPSENS for the temperature sensor channel, represented as a twos complement number. 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. The ADCGAINTEMPSENS register provides the ADC gain calibration value used when measuring the internal temperature sensor. Table 71. Bit Descriptions for ADCGAINTEMPSENS Register number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part. 0x0000 0. Illegal value resulting in an ADC result of 0. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment.

Table 72. ADC Digital Postprocessing Registers Summary Table 73. Bit Descriptions for ADCMIN Register register or INTCFLAG1 register is set to 1. Table 74. Bit Descriptions for ADCMINSM Register Table 75. Bit Descriptions for ADCMAX Register INTCFLAG1 register is set to 1. Table 76. Bit Descriptions for ADCMAXSMEN Register the value of ADCMAX, Bits[15:0] – ADCMAXSMEN, Bits[15:0]. Table 77. Bit Descriptions for ADCDELTA Register FLAG6 bit of the INTCFLAG0 register or INTCFLAG1 register.

Table 78. ADC Statistics Registers Summary Table 79. Bit Descriptions for STATSVAR Table 80. Bit Descriptions for STATSCON Register Table 81. Bit Descriptions for STATSMEAN Register samples set by STATSCON, Bits[6:4].

Figure 36. Switch Matrix High Level Diagram

Figure 37. Switch Matrix Block Diagram—Switches Connecting to the High Speed DAC and High Speed TIA

Table 82. Programmable Switch Matrix Registers Summary This register allows configuration of the switch matrix. Table 83. Bit Descriptions for SWCON Register PSWFULLCON, and NSWFULLCON registers. 0 Dx/DR0, Tx/TR1, Px/Pxx, and Nx/Nxx switches controlled as groups. Switches controlled as groups via the SWCON register. 0001 T1 closed, remaining switches open. 0010 T2 closed, remaining switches open. 0011 T3 closed, remaining switches open. 0100 T4 closed, remaining switches open. 0101 T5 closed, remaining switches open. 0110 T6 closed, remaining switches open. 0111 T7 closed, remaining switches open. 1000 TR1 closed, remaining switches open. 1010 to 1111 All switches open.

Rev. C | Page 75 of 134 Bits Bit Name Settings Description Reset Access [11:8] NMUXCON Control of N switch mux. 0xF R/W 0000 NL closed, remaining switches open. 0001 N1 closed, remaining switches open. 0010 N2 closed, remaining switches open. 0011 N3 closed, remaining switches open. 0100 N4 closed, remaining switches open. 0101 N5 closed, remaining switches open. 0110 N6 closed, remaining switches open. 0111 N7 closed, remaining switches open. 1000 Reserved. 1001 N9 closed, remaining switches open. 1010 NR1 closed, remaining switches open. 1011 to 1110 NL2 closed, remaining switches open. 1111 All switches open. [7:4] PMUXCON Control of Px/Pxx switch mux. 0xF R/W 0000 PL closed, remaining switches open. 0001 PR0 closed, remaining switches open. 0010 P2 closed, remaining switches open. 0011 P3 closed, remaining switches open. 0100 P4 closed, remaining switches open. 0101 P5 closed, remaining switches open. 0110 P6 closed, remaining switches open. 0111 P7 closed, remaining switches open. 1000 P8 closed, remaining switches open. 1001 P9 closed, remaining switches open. 1010 Reserved. 1011 P11 closed, remaining switches open. 1100 Reserved. 1101 to 1110 PL2 closed, remaining switches open. 1111 All switches open. [3:0] DMUXCON Control of Dx/DR0 switch mux. 0xF R/W 0000 All switches open. 0001 DR0 closed, remaining switches open. 0010 D2 closed, remaining switches open. 0011 D3 closed, remaining switches open. 0100 D4 closed, remaining switches open. 0101 D5 closed, remaining switches open. 0110 D6 closed, remaining switches open. 0111 D7 closed, remaining switches open. 1000 D8 closed, remaining switches open. 1001 All switches closed. 1010 to 1111 All switches open.

Rev. C | Page 77 of 134 Bits Bit Name Settings Description Reset Access 9 NR1 Control of the NR1 switch. If this bit is set, NR1 is closed. If this bit is not set, NR1 is open. This bit connects the negative node of the excitation amplifier to the RCAL1 pin. 0x0 R/W 0 Switch open. 1 Switch closed. 8 N9 Control of the N9 switch. If this bit is set, N9 is closed. If this bit is not set, N9 is open. This bit connects the negative node of the excitation amplifier directly to the SE0 pin, bypassing the RLOAD_SE0 resistor. 0x0 R/W 0 Switch open. 1 Switch closed. 7 Reserved Reserved. 6 N7 Control of the N7 switch. If this bit is set, N7 is closed. If this bit is not set, N7 is open. This bit connects the negative node of the excitation amplifier to the AFE3 pin via the RLOAD_AFE3 resistor. 0x0 R/W 0 Switch open. 1 Switch closed. 5 N6 Control of the N6 switch. If this bit is set, N6 is closed. If this bit is not set, N6 is open. This bit connects the negative node of the excitation amplifier to SE0. 0x0 R/W 0 Switch open. 1 Switch closed. 4 N5 Control of the N5 switch. If this bit is set, N5 is closed. If this bit is not set, N5 is open. This bit connects the negative node of the excitation amplifier to the SE0 pin via RLOAD_SE0. 0x0 R/W 0 Switch open. 1 Switch closed. 3 N4 Control of the N4 switch. If this bit is set, N4 is closed. If this bit is not set, N4 is open. This bit connects the negative node of the excitation amplifier to the AIN3 pin. 0x0 R/W 0 Switch open. 1 Switch closed. 2 N3 Control of the N3 switch. If this bit is set, N3 is closed. If this bit is not set, N3 is open. This bit connects the negative node of the excitation amplifier to the AIN2 pin. 0x0 R/W 0 Switch open. 1 Switch closed. 1 N2 Control of the N2 switch. If this bit is set, N2 is closed. If this bit is not set, N2 is open. This bit connects the negative node of the excitation amplifier to the AIN1 pin. 0x0 R/W 0 Switch open. 1 Switch closed. 0 N1 Control of the N1 switch. If this bit is set, N1 is closed. If this bit is not set, N1 is open. This bit connects the negative node of the excitation amplifier to the AIN0 pin. 0x0 R/W 0 Switch open. 1 Switch closed. Switch Matrix Full Configuration Px/Pxx Register—PSWFULLCON Address 0x00002158, Reset: 0x00000000, Name: PSWFULLCON The PSWFULLCON register allows individual control of the Px/Pxx switches. The bit names are the same as the switch names shown in Figure 37.

Table 86. Bit Descriptions for PSWFULLCON Register 5 P6 Control of the P6 switch. Setting this bit closes P6. P6 is open if this bit is not set. This bit connects the positive node of the excitation amplifier to the AFE2 pin.

Table 87. Bit Descriptions for TSWFULLCON Register not set. This switch is used in conjunction with the T10 switch. determined by T1, T2, T3, T4, T5, and T6. the RLOAD_DE0 and RTIA_DE0 resistors. via the T9 switch and RLOAD_SE0.

1 T2 Control of the T2 switch. Setting this bit closes T2. T2 is open if this bit is not set. 0 T1 Control of the T1 switch. Setting this bit closes T1. T1 is open if this bit is not set. The DSWSTA register indicates the status of the Dx/DR0 switches. The bit names are the same as the switch names shown in Figure 37. Table 88. Bit Descriptions for DSWSTA Register The PSWSTA register indicates the status of the Px/Pxx switches. The bit names are the same as the switch names shown in Figure 37. Table 89. Bit Descriptions for PSWSTA Register

11 Reserved Reserved 0x0 R

9 Reserved Reserved 0x0 R

0 PR0STA Status of the PR0 Switch 0x0 R

The NSWSTA register indicates the status of the Nx/Nxx switches. The bit names are the same as the switch names shown in Figure 37. Table 90. Bit Descriptions for NSWSTA Register

7 Reserved Reserved 0x0 R

The TSWSTA register indicates the status of the Tx/TR1 switches. The bit names are the same as the switch names shown in Figure 37. Table 91. Bit Descriptions for TSWSTA Register

10 Reserved Reserved 0x0 R

Rev. C | Page 83 of 134 Bits Bit Name Settings Description Reset Access 7 Reserved Reserved. 0x0 R 6 T7STA Status of the T7 switch. 0x0 R 0 Switch open. 1 Switch closed. 5 T6STA Status of the T6 switch. 0x0 R 0 Switch open. 1 Switch closed. 4 T5STA Status of the T5 switch. 0x0 R 0 Switch open. 1 Switch closed. 3 T4STA Status of the T4 switch. 0x0 R 0 Switch open. 1 Switch closed. 2 T3STA Status of the T3 switch. 0x0 R 0 Switch open. 1 Switch closed. 1 T2STA Status of the T2 switch. 0x0 R 0 Switch open. 1 Switch closed. 0 T1STA Status of the T1 switch. 0x0 R 0 Switch open. 1 Switch closed.

Table 92. Bit Descriptions for BUFSENCON Register 0 Disables 1.82 V buffered reference output. 1 Enables 1.82 V buffered reference output. charge on external decoupling capacitor for the 1.11 V reference. speed or low power reference buffer. 0 Disables the 1.11 V low power reference buffer of the ADC. 1 Enables the 1.11 V low power reference buffer of the ADC. 0 Disables the 1.11 V, high speed, common-mode buffer. value for normal ADC operation). the external decoupling capacitor. capacitor for the reference is maintained (recommended value). 0 Disables the low power 1.82 V reference buffer. setting speeds up the settling time when exiting a power-down state. 0 Disables buffer current limit. 1 Enables buffer current limit (recommended value). 0 Disables 1.82 V high speed ADC reference buffer. 1 Enables 1.82 V high speed ADC reference buffer.

Rev. C | Page 88 of 134 SEQUENCER OPERATION Figure 42 shows the typical steps required to set up the sequencer to take measurements. After the device is booted, the sequencer, command memory, and data FIFO must be configured. The following steps are required for this configuration: 1. Configure the command memory. 2. Load the sequences into SRAM. 3. Set the Sequence 0 (SEQ0) to Sequence 3 (SEQ3) information sequences. 4. Configure the data FIFO. 5. Configure the sleep wake-up timer. 6. Configure the GPIO pin mux. 7. Configure the interrupts. 8. Configure the sleep and wake-up method. Command Memory The command memory stores the sequence commands and provides a link between the external microcontroller and the sequencer. The command memory can be configured to use the 2 kB, 4, kB, and 6 kB SRAM memory sizes, which are selected using the CMDDATACON, Bits[2:0]. The large amount of memory available for the command memory facilitates the creation of larger, more complex sequences. Determine the number of commands in a sequence by reading SEQxINFO, Bits[26:16]. The command memory is unidirectional. The host microcontroller specifies the destination address of the command by writing to the CMDFIFOW ADDR register and writes the command contents to the CMDFIFOWRITE register. The sequencer reads the commands from memory for execution. There are a number of interrupts associated with the command FIFO, including the FIFO threshold interrupt, the FIFO empty interrupt, and the FIFO full interrupt. Refer to the Interrupts section for more information. Loading Sequences The sequence commands are written to SRAM by writing to two registers. The address in SRAM for the command is written to the CMDFIFOW ADDR register. The command content is written to the CMDFIFOWRITE register. After all the commands are written to SRAM, set the SEQ0 to SEQ3 information sequences by writing to the SEQxINFO registers. Each information sequence from SEQ0 to SEQ3 requires a start address in SRAM and a total number or commands for that sequence. The number of commands is written to SEQxINFO, Bits[26:16]. The start address is written to SEQxINFO, Bits[10:0]. Ensure there is no overlap between the four sequences. There is no hardware mechanism in place to warn the user of overlapping sequences. There are a number of interrupt sources associated with the sequencer, including the following:

Sequence timeout error.
Sequencer timeout command finished.
End of sequence interrupt. For this interrupt to be asserted, SEQCON, Bit 0, must be cleared at the end of the sequencer command. Refer to the Interrupts section for more information. Data FIFO The data FIFO provides a buffer for the output of the analog and DSP blocks before it is read by the external controller. The memory available for the data FIFO can be selected in the DATA_MEM_SEL bits in the CMDDATACON register. The available options are 2 kB, 4 kB, and 6 kB. The data FIFO and command memory share the same block of 6 kB SRAM. Therefore, ensure there is no overlap between the command memory and data FIFO. The data FIFO can be configured in FIFO mode or stream mode via CMDDATACON, Bits[11:9]. In stream mode, when the FIFO is full, old data is discarded to make room for new data. In FIFO mode, when the FIFO is full, new data is discarded. Never let the FIFO overflow when in FIFO mode. All new data are then lost. The data FIFO is always unidirectional. A selectable source in the AFE block writes data and the external microcontroller reads data from DATAFIFORD. Select the data source for the data FIFO in DATAFIFOSRCSEL (FIFOCON, Bits[15:13]). The available options are as follows: ADC data, DFT result, sinc2 filter result, statistic block mean result, and statistic block variance result. There a number of interrupt flags associated with the data FIFO, including the following: empty, full, overflow, underflow, and threshold. These interrupts are user readable using the INTCFLAGx registers (see the Interrupts section for more details). Each flag has an associated maskable interrupt. The overflow and underflow flags only activate for one clock period. The data FIFO is enabled by writing a 1 to FIFOCON, Bit 11. The data FIFO threshold value is set by writing to the DATAFIFOTHRES register. At any time, the host microcontroller can read the number of words in the data FIFO by reading FIFOCNTSTA, Bits[26:16]. Reading data from the data FIFO when empty returns 0x00000000. In addition, the underflow flag, FLAG27, in the INTCFLAGx register is asserted.

Table 94. Sequence and FIFO Registers Summary Table 95. Bit Descriptions for SEQCON Register is useful to reduce the code size when generating arbitrary waveforms. The clock source for the timer is ACLK.

1 Sequencer stops if command FIFO is empty and sequencer attempts to

read (in an underflow condition). 0 Sequencer continues to attempt to read, even if the FIFO is empty. command FIFO and executes the commands. 0 Sequencer disabled (default).

Table 96. Bit Descriptions for FIFOCON Register lowest two bits are fractional because the ADC is 16 bits. 011 Sinc2 filter output. Data is 16 bits. 100 Variance. Variance is 30-bit data, which uses two addresses. 101 Mean result. Mean is 16 bits of data. indicates that the FIFO is empty. 1 Normal operation. The FIFO is not reset. The SEQCRC register forms the checksum value calculated from all the commands executed by the sequencer. Table 97. Bit Descriptions for SEQCRC Register Table 98. Bit Descriptions for SEQTIMEOUT Register Table 99. Bit Descriptions for DATAFIFORD Register 0x00000000. See Figure 43 and Figure 44 for 32-bit word format. Table 100. Bit Descriptions for CMDFIFOWRITE Register ignored and all current commands are not affected.

The SEQSLPLOCK register protects the SEQTRGSLP register. Table 101. Bit Descriptions for SEQSLPLOCK Register accidentally triggering a sleep state. 0x0000 Write any value other than 0xA47E5 to lock the SEQTRGSLP register. 0xA47E5 Write this value to this register to unlock the SEQTRGSLP register. The SEQTRGSLP register is protected by the SEQSLPLOCK register. Table 102. Bit Descriptions for SEQTRGSLP Register Table 103. Bit Descriptions for SEQ0INFO Register Table 104. Bit Descriptions for SEQ2INFO Register Table 105. Bit Descriptions for CMDFIFOWADDR Register

Table 106. Bit Descriptions for CMDDATACON Register Table 107. Bit Descriptions for DATAFIFOTHRES Register Table 108. Bit Descriptions for SEQ3INFO Register Table 109. Bit Descriptions for SEQ1INFO Register

Table 110. Bit Descriptions for FIFOCNTSTA Register Table 111. Bit Descriptions for SYNCEXTDEVICE Register GPIOx high. Writing 0 sets the corresponding GPIOx to 0. Table 112. Bit Descriptions for TRIGSEQ Register

Table 113. Waveform Generator for High Speed DAC Registers Summary Table 114. Bit Descriptions for WGCON Register factory trim and stored in the DACGAIN register. 0 Bypass DAC gain correction. 1 Perform DAC gain correction. 0 Bypass DAC offset correction. power and high power mode, respectively, when LPDACCON0, Bit 0 = 1. 00 Direct write to the DAC. User code writes to the HSDACDAT register directly. 0 Disable reset of the trapezoid waveform generator. 1 Enable reset of the trapezoid waveform generator. Table 115. Bit Descriptions for WGDCLEVEL1 Register

Table 116. Bit Descriptions for WGDCLEVEL2 Register Table 117. Bit Descriptions for SEQCNT Register this register also to clear the SEQCRC register. Table 118. Bit Descriptions for WGDELAY1 Register Table 119. Bit Descriptions for WGSLOPE1 Register update rate. For trapezoid generation, the DAC update rate is fixed to 320 kHz. Table 120. Bit Descriptions for WGDELAY2 Register update rate. For trapezoid generation, the DAC update rate is fixed to 320 kHz. Table 121. Bit Descriptions for WGSLOPE2 Register update rate. For trapezoid generation, the DAC update rate is fixed to 320 kHz.

Table 122. Bit Descriptions for WGFCW Register in the ADCFILTERCON register (see Table 43). If the DFT input data rate = 800 kHz, the ADC output data rate must be set to 800 kHz. Refer to the ADCSAMPLERATE bit in the ADCFILTERCON register = 1 (see Table 43). in the ADCFILTERCON register (see Table 43). For more information, see the High Performance ADC Circuit section. Table 123. Bit Descriptions for WGPHASE Register example, to obtain a 45° phase offset, SINEOFFSET, Bits[19:0] = 45/360 × 220. and the WAVEGENEN bit in the AFECON register. Table 124. Bit Descriptions for WGOFFSET Register register and the WAVEGENEN bit in the AFECON register. Table 125. Bit Descriptions for WGAMPLITUDE Register WGCON register and the WAVEGENEN bit in the AFECON register.

AD5940/AD5941 are CS, SCLK, MOSI, and MISO. AD5940/AD5941. The maximum clock speed is 16 MHz. to the host during a read transaction.

SCLK is always slower than the system clock on the AD5940/AD5941, which is 16 MHz.
When the CS signal is brought low, a multiple of eight clock cycles must be generated by the host.
Transfers over the SPI slave are always byte aligned.
In every octet, the most significant bit (Bit 7) is transmitted and received first.
If the CS signal is brought high at any time by the host, the AD5940/AD5941 is ready to accept new SPI transactions when the CS signal is brought low again by the host. The minimum time between CS going high and going low again is t10 (see Table 4). COMMAND BYTE The first byte sent from the host to the AD5940/AD5941 in an SPI transaction is the command byte. The command byte specifies the SPI protocol used for the SPI transaction. The available commands are detailed in Table 126.

Table 126. SPI Commands reading data from the data FIFO.

Write the command byte and configure the register

b. Send 8-bit command byte: SPICMD_SETADDR.

Write the data to the register.

c. Write either 16-bit or 32-bit data to the register.

Read the data from the register.

b. Send 8-bit command byte: SPICMD_READREG. d. Read returning 16-bit or 32-bit data.

describes this protocol and is illustrated in Figure 48.

Send an 8-bit command byte: SPICMD_READFIFO.
Transmit six dummy bytes on the SPI bus before valid data
Continuously read the DATAFIFORD register until only
Read back the last two data points using a nonzero offset.

the APB reads Data C when the SPI bus is transferring Data B. FIFO underflows, which causes an underflow error. Figure 48. Data FIFO Read Protocol

6 DUMMY READS BEFORE VALID DATA

the end of the last sequence. Code is the code value for the SEQxWUPx register. ClkFreq is frequency of the internal oscillator in Hz. Time is required timeout duration in seconds. Table 127. Sleep and Wake-Up Timer Registers Summary The CON register is the wake-up timer control register. Table 128. Bit Descriptions for CON Register 0 The sleep and wake-up timer stops at Sequence A and then goes back to Sequence A. 1 The sleep and wake-up timer stops at Sequence B and then goes back to Sequence A. 10 The sleep and wake-up timer stops at Sequence C and then goes back to Sequence A. 11 The sleep and wake-up timer stops at Sequence D and then goes back to Sequence A. 100 The sleep and wake-up timer stops at Sequence E and then goes back to Sequence A. 101 The sleep and wake-up timer stops at Sequence F and then goes back to Sequence A. 110 The sleep and wake-up timer stops at Sequence G and then goes back to Sequence A. 111 The sleep and wake-up timer stops at Sequence H and then goes back to Sequence A.

0 Enables the sleep and wake-up timer. 1 Disables the sleep and wake-up timer. The SEQORDER register controls the command sequence execution order. Table 129. Bit Descriptions for SEQORDER Register

Table 130. Bit Descriptions for SEQxWUPL Registers the device stays in sleep mode. When this time elapses, the device wakes up. Table 131. Bit Descriptions for SEQxWUPH Registers The SEQxSLEEPL registers define the device active time for SEQ0 to SEQ3. The counter is 20 bits. These registers set the 16 LSBs. Table 132. Bit Descriptions for SEQxSLEEPL Registers The SEQxSLEEPH registers define the device active time for SEQ0 to SEQ3. The counter is 20 bits. These registers set the four MSBs.

Table 133. Bit Descriptions for SEQxSLEEPH Registers Table 134. Bit Descriptions for TMRCON Register ability of the sleep and wake-up timer to wake up the chip.

GPIOx pin in response to an interrupt event. consists of an INTCSELx register and an INTCFLAGx register. GPIOx pin in response to an interrupt event. source, write to the corresponding bit in the INTCCLR register. register when using the SPI has no effect.

Rising edge. The logic detects a transition from low to high and generates a pulse.
Falling edge. The logic detects a transition from high to low and generates a pulse.
Rising or falling edge. The logic detects a transition from low to high or high to low and generates a pulse.
High level. The logic detects a high level. The interrupt line is held asserted until the external source deasserts.
Low level. The logic detects a low level. The interrupt line is held asserted until the external source deasserts. The external interrupt detection unit block allows an external event to wake up the AD5940/AD5941 when it is in hibernate mode.

Table 135. Interrupt Sources Summary FLAG0 ADC result IRQ status. FLAG1 DFT result IRQ status. FLAG2 Sinc2 filter result ready IRQ status. FLAG3 Temperature result IRQ status. FLAG4 ADC minimum fail IRQ status. FLAG5 ADC maximum fail IRQ status. FLAG6 ADC delta fail IRQ status. FLAG13 Bootload done IRQ status. FLAG15 End of sequence IRQ status. FLAG16 Sequencer timeout finished IRQ status. See the Timer Command section. FLAG17 Sequencer timeout command error IRQ status. See the Timer Command section. FLAG23 Data FIFO full IRQ status. FLAG24 Data FIFO empty IRQ status. FLAG25 Data FIFO threshold IRQ status. Threshold value set in DATAFIFOTHRES register. FLAG26 Data FIFO overflow IRQ status. FLAG27 Data FIFO underflow IRQ status. FLAG29 Outlier IRQ status. Detects when an outlier is detected. running. This interrupt indicates that Sequence B is ignored.

Table 136. Interrupt Registers Summary Table 137. Bit Descriptions for INTCPOL Register 0 Output negative edge interrupt. 1 Output positive edge interrupt. Table 138. Bit Descriptions for INTCCLR Register

Table 139. Bit Descriptions for INTCSEL0 and INTCSEL1 Registers

Rev. C | Page 109 of 134 Bits Bit Name Settings Description Reset Access 12 INTSEL12 Custom IRQ3 enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 11 INTSEL11 Custom IRQ 2 enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 10 INTSEL10 Custom IRQ 1 enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 9 INTSEL9 Custom IRQ 0 enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 8 INTSEL8 Variance IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 7 INTSEL7 Mean IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 6 INTSEL6 ADC delta fail IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 5 INTSEL5 ADC maximum fail IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 4 INTSEL4 ADC minimum fail IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 3 INTSEL3 Temperature result IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 2 INTSEL2 Sinc2 filter result ready IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 1 INTSEL1 DFT result IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled. 0 INTSEL0 ADC result IRQ enable. 0x0 R/W 0 Interrupt disabled. 1 Interrupt enabled.

Table 140. Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers Sequence A is running, indicating that Sequence B is ignored.

Rev. C | Page 111 of 134 Bits Bit Name Settings Description Reset Access 12 FLAG12 Custom Interrupt 3 status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 11 FLAG11 Custom Interrupt 2 status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 10 FLAG10 Custom Interrupt 1 status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 9 FLAG9 Custom Interrupt 0 status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 8 FLAG8 Variance IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 7 FLAG7 Mean IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 6 FLAG6 ADC delta fail IRQ status. When this bit is set, it is indicated that the difference between two consecutive ADC results is greater than the value specified by the ADCDELTA register. If this bit is clear, it is indicated that no difference between two consecutive ADC values greater than the limit is detected since the last time this bit was cleared. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 5 FLAG5 ADC maximum fail IRQ status. When this bit is set, it is indicated that an ADC result is above the maximum value specified by the ADCMAX register. If this bit is clear, it is indicated that no ADC value above the maximum is detected. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 4 FLAG4 ADC minimum fail IRQ status. When this bit is set, it is indicated that an ADC result is below the minimum value as specified by the ADCMIN register. If this bit is clear, it is indicated that no ADC value below the limit is detected since the last time this bit was cleared. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 3 FLAG3 Temperature result IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 2 FLAG2 Sinc2 filter result ready IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 1 FLAG1 DFT result IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted. 0 FLAG0 ADC result IRQ status. 0x0 R 0 Interrupt not asserted. 1 Interrupt asserted.

to this register using the SPI has no effect. Reading this register using the SPI does not return meaningful data. Table 141. Bit Descriptions for AFEGENINTSTA Register program. Write 1 to this bit to trigger an interrupt. program. Write 1 to this bit to trigger an interrupt. program. Write 1 to this bit to trigger an interrupt. program. Write 1 to this bit to trigger an interrupt. Table 142. External Interrupt Registers Summary Table 143. Bit Descriptions for EI0CON Register mode to enable the ability of GPIO3 to wake up the device. 0 External Interrupt 3 disabled. 1 External Interrupt 3 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). mode to enable the ability of GPIO2 to wake up the device. 0 External Interrupt 2 disabled. 1 External Interrupt 2 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011).

mode to enable the ability of GPIO1 to wake up the device. 0 External Interrupt 1 disabled. 1 External Interrupt 1 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). mode to enable the ability of GPIO0 to wake up the device. 0 External Interrupt 0 disabled. 1 External Interrupt 0 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). Table 144. Bit Descriptions for EI1CON Register to enable the ability of GPIO7 to wake up the device. 0 External Interrupt 7 disabled. 1 External Interrupt 7 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). to enable the ability of GPIO6 to wake up the device. 0 External Interrupt 6 disabled. 1 External Interrupt 6 enabled.

101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). to enable the ability of GPIO5 to wake up the device. 0 External Interrupt 5 disabled. 1 External Interrupt 5 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). to enable the ability of GPIO4 to wake up the device. 0 External Interrupt 4 disabled. 1 External Interrupt 4 enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011). Table 145. Bit Descriptions for EI2CON Register mode to enable the ability of the SPI to wake up the device. 0 Bus interrupt wake-up disabled. 1 Bus interrupt wake-up enabled. 101 Falling edge (same as 001). 110 Rising or falling edge (same as 010). 111 High level (same as 011).

Table 146. Bit Descriptions for EICLR Register cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware. is cleared automatically by the hardware.

contains multiple functions that are configurable by user code. Figure 52. Digital Input/Output Diagram resistors disabled to reduce power consumption. register, the GPIO input levels are available in the GP0IN register. GP0OUT register are reflected on the GPIOs. The GP0 port has a corresponding bit set register, GP0SET. data outputs without affecting other outputs within the port. is set. The remaining GPIOs are unaffected. The GP0 port has a corresponding bit clear register, GP0CLR. cleared. The remaining GPIOs are unaffected. The GP0 port has a corresponding bit toggle register, GP0TGL. equal to 1 is toggled. The remaining GPIOs are unaffected. on the corresponding GPIOx pins. Each GPIOx pin can be configured to react to external events. mapped to certain GPIOx pins (see the GP0CON register). the interrupt controller register (see the Interrupts section). register and sync must be selected in the GP0CON register.

Table 147. GPIOx Multiplex Options Table 148. GPIO Registers Summary The GP0CON register configures the configuration for each of the eight GPIOs. Table 149. Bit Descriptions for GP0CON Register 00 General-purpose input/output. 01 Sequence 3 trigger signal input from the microcontroller unit (MCU) side. 10 Synchronizes External Device 7 output signal. 00 General-purpose input/output. 01 Sequence 2 trigger signal input from the MCU side. 10 Synchronizes External Device 6 output signal. 00 General-purpose input/output. 01 Sequence 1 trigger signal input from the MCU side. 10 Synchronizes External Device 5 output signal. 11 External clock input (EXTCLK). 00 General-purpose input/output. 01 Sequence 0 trigger signal input from the MCU side. 10 Synchronizes External Device 4 output signal.

00 General-purpose input/output. 01 Sequence 3 trigger signal input from the MCU side. 10 Synchronizes External Device 3 output signal. 01 Sequence 2 trigger signal input from the MCU side. 10 Synchronizes External Device 2 output signal. 11 External clock input (EXTCLK). 00 General-purpose input/output. 01 Sequence 1 trigger signal input from the MCU side. 10 Synchronizes External Device 1 output signal. command to put the AD5940/AD5941 back in sleep mode. 01 Sequence 0 trigger signal input from the MCU side. 10 Synchronizes External Device 0 output signal. 11 General-purpose input/output. The GP0OEN register enables the output for each GPIO. Table 150. Bit Descriptions for GP0OEN Register particular pin. Each bit is cleared to disable the output for each pin. Table 151. Bit Descriptions for GP0PE Register Table 152. Bit Descriptions for GP0IEN Register the input path for the GPIOx pin.

Table 153. Bit Descriptions for GP0IN Register Table 154. Bit Descriptions for GP0OUT Register user to drive the corresponding GPIOx low. Table 155. Bit Descriptions for GP0SET Register [7:0] Set Set the output high. Set by user code to drive the corresponding GPIOx high. Clearing this bit has no effect. Table 156. Bit Descriptions for GP0CLR Register [7:0] CLR Set the output low. Each bit is set to drive the corresponding GPIOx pin low. Clearing this bit has no effect. Table 157. Bit Descriptions for GP0TGL Register

External reset.
POR.
Software reset of the digital part of the device. The low power, potentiostat amplifier and low power TIA circuitry is not reset. The AD5940/AD5941 is reset during an external hardware reset or POR. The external reset or hardware reset is connected to the external RESET pin. When this pin is pulled low, a reset occurs. All circuits and control registers return to their default state. The host microcontroller can trigger a software reset to the AD5940/AD5941 by clearing SWRSTCON, Bit 0. It is recommends to connect the RESET pin of the AD5940/AD5941 to a GPIO pin on the host processor to give the controller control over hardware resets. The AD5940/AD5941 reset status register is RSTSTA. Read this register to identify the source of the reset to the chip. Software resets can be bypassed to ensure the circuits used to bias an external sensor are not disturbed. These circuits include the ultra low power DACs, potentiostat amplifier, and TIAs. The programmable switches circuits can also be configured to maintain their states in the event of a reset. ANALOG DIE RESET REGISTERS

Table 158. Analog Die Reset Registers Summary Table 159. Bit Descriptions for RSTCONKEY Register register before writing to the SWRSTCON register returns the protection to the lock state. Table 160. Bit Descriptions for SWRSTCON Register Table 161. Bit Descriptions for RSTSTA Register register. Clear this bit by writing 1.

(<80 kHz), hibernate mode, and shutdown mode.

32 MHz oscillator is selected to drive the high speed DAC and

Set the system clock divider to 2 and set the ADC clock
Switch the oscillator to 32 MHz.
Set ADCFILTERCON, Bit 0 = 1 to enable a 1.6 MHz ADC

oscillator (PWRMOD, Bits[1:0] = 0x1). kHz oscillator remains active. The watchdog timer is also active. remain active to maintain the bias of an external sensor. However, current consumption increases. expected to power-down the low power analog blocks. powers down the high power reference. protected by the LPMODKEY register. Table 162. Power Mode Registers Summary Table 163. Bit Descriptions for PWRMOD Register 0 RAM is not retained during hibernate mode. 1 RAM is retained during hibernate mode. 0 ADC power switch turned off during hibernate mode. 1 ADC power switch turned on during hibernate mode.

0 Disables the sequencer autosleep function. 1 Enables the sequencer autosleep function. 0 Disables the sleep and wake-up timer autosleep function. 1 Enables the sleep and wake-up timer autosleep function. optionally power down blocks by disabling their input clock. (low power DACs and references can remain active to bias an external sensor). powered down. Only the low speed clock is powered up. Table 164. Bit Descriptions for PWRKEY Register writing to PWRMOD returns the protection to the lock state. The LPMODEKEY register protects the LPMODECLKSEL and LPMODECON registers. Table 165. Bit Descriptions for LPMODEKEY Register registers. The key prevents accidental writing to the registers. 0xC59D6 Clocks related registers via a sequencer write. 0xC59D6 to lock the sequencer read/write clock related registers. The LPMODECLKSEL register is protected by the LPMODKEY register. Table 166. Bit Descriptions for LPMODECLKSEL Register bit to switch to the 32 kHz oscillator. Clear this bit to switch to the 16 MHz oscillator.

The LPMODECON register is protected by the LPMODEKEY register. Table 167. Bit Descriptions for LPMODECON Register

A low frequency, 32 kHz internal oscillator (LFOSC). This is used to clock the sleep/wakeup timer.
A high frequency, 16 MHz or 32 MHz internal oscillator (HFOSC). The 32 MHz setting only is designed to clock the HSDAC, HSTIA and ADC circuits for high bandwidth measurements > 80 kHz.
An external 16 MHz or 32 MHz crystal option. If a 32 MHz crystal is used, ensure that SYSCLKDIV, Bits [5:0] = 2 in the CLKCON0 register. This limits the digital die clock source to 16 MHz. The ADC clock cannot be divided. Thus, if using a

32 MHz crystal, the ADC is always running on a 32 MHz

2 mA when using a 32 MHz clock compared to a 16 MHz.

An external clock input option on GPIO2 or GPIO5 (GPIO5 is available on AD5940 only). If a 32 MHz source is used, ensure that SYSCLKDIV , Bits [5:0] = 2 in CLKCON0 register. This limits the digital die clock source to 16 MHz. The ADC clock cannot be divided. Thus, if using a 32 MHz crystal the ADC is always running on a 32 MHz clock. The current consumption of the ADC increases by 2 mA when using a 32 MHz clock compared to a 16 MHz. At power-up, the internal high frequency oscillator is selected as the AFE system clock with a 16 MHz setting. The user code can divide the clock by a factor of 1 to 32 to reduce power consumption. Note that the system performance is only validated with AFE system clock rate of 16 MHz. The clock architecture diagram is shown in Figure 53.

Figure 53. AD5940/AD5941 System Clock Architecture Table 168. Clock Registers Summary

Table 169. Bit Descriptions for CLKCON0KEY Register Table 170. Bit Descriptions for CLKCON0 Register clock frequency (fSYS) = root clock/SYSCLKDIV. The value range is from 1 to 32. as divide by 1. The fSYS frequency must be ≤16 MHz. Table 171. Bit Descriptions for CLKSEL Register 0 Internal high frequency oscillator clock. 1 External high frequency crystal clock. 10 Internal low frequency oscillator clock (not recommended). 0 Internal high frequency oscillator clock. 1 External high frequency crystal clock. 10 Internal low frequency oscillator clock (not recommended). Table 172. Bit Descriptions for CLKEN0 Register 0 Turn on sleep wake-up timer clock. 1 Turn off sleep wake-up timer clock.

Table 173. Bit Descriptions for CLKEN1 Register analog interface and digital signal processing. Table 174. Bit Descriptions for OSCKEY Register write to any other register before writing to this register returns the protection to the lock state. Table 175. Bit Descriptions for OSCCON Register indicate a subsequent loss of stability. 0 Oscillator is not yet stable or is disabled. 1 Oscillator is enabled and is stable and ready for use. subsequent loss of stability. 0 Oscillator is not yet stable or is disabled. 1 Oscillator is enabled and is stable and ready for use. subsequent loss of stability. 0 Oscillator is not yet stable or is disabled. 1 Oscillator is enabled and is stable and ready for use.

SYSRESETREQ system reset can be initiated. 0 The high frequency crystal oscillator is disabled and placed in a low power state. 1 The high frequency crystal oscillator is enabled. the SYSRESETREQ system reset can be initiated. 0 The high frequency oscillator is disabled and placed in a low power state. 1 The high frequency oscillator is enabled. oscillator. The oscillator must be stable before use. 0 The low frequency oscillator is disabled and placed in a low power state. 1 The low frequency oscillator is enabled. Table 176. Bit Descriptions for HSOSCCON Register oscillator to 32 MHz. Refer to the SYSCLKDIV bit in the CLKCON0 register. Table 177. Bit Descriptions for RSTCONKEY Register before writing to SWRSTCON returns the protection to the lock state. Table 178. Bit Descriptions for LOSCTST Register adjusting the charging capacitors.

70 μA. For details, see the AN-1557 Application Note. Figure 54. Low Frequency, 2-Wire, Bioimpedance Loop (Maximum Bandwidth = 300 Hz)

Figure 55. High Frequency, 4-Wire, Bioimpedance Loop (Maximum Bandwidth = 200 kHz)

Figure 56. Using a High Bandwidth AFE Loop in Potentiostat Mode

disconnects the AD8232 and AD8233 from the electrodes. be read by the host controller. Figure 57. Body Composition and ECG System Solution Using the AD5940/AD5941 with the AD8232 and the AD8233

buffering purposes before conversion by the ADC. preprogrammed, smart water measurements. Figure 58. Typical Water Analysis Application Using the AD5940/AD5941

Figure 59. 56-Ball Wafer Level Chip Scale Package [WLCSP] Figure 60. 48-Lead Lead Frame Chip Scale Package [LFCSP]

2.40 REF

2.80 REF

0.20 MIN

0.02 NOM

0.203 REF

5.50 REF

Rev. C | Page 134 of 134 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option AD5940BCBZ-RL −40°C to +85°C 56-Ball Wafer Level Chip Scale Package [WLCSP] CB-56-3 AD5940BCBZ-RL7 −40°C to +85°C 56-Ball Wafer Level Chip Scale Package [WLCSP] CB-56-3 AD5941BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-4 AD5941BCPZ-RL7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-4 AD5941WBCPZ-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-4 EVAL-AD5940BIOZ Bi oelectric Evaluation Board EVAL-AD5940ELCZ E lectrochemical Evaluation Board for AD5940 EVAL-AD5941ELCZ E lectrochemical Evaluation Board for AD5941 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5941W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2019-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16778-5/22(C)

Product Information

AD5941BCPZ-RL7 specifications and overview.

Summary

High Precision, Impedance, and Electrochemical Front End

Description

High Precision, Impedance, and Electrochemical Front End

Source title AD5941BCPZ-RL7 Datasheet(PDF) - Analog Devices

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