AD5932

AD5932 (Rev. C)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

Programmable Frequency Scan Waveform Generator Data Sheet AD5932 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Programmable frequency profile No external components necessary Output frequency up to 25 MHz Preprogrammable frequency profile minimizes number of DSP/microcontroller writes Sinusoidal/triangular/square wave outputs Automatic or single pin control of frequency stepping Power-down mode: 20 µA Power supply: 2.3 V to 5.5 V Automotive temperature range: −40°C to +125°C 16-lead, Pb-free TSSOP

APPLICATIONS

Network/impedance measurements Incremental frequency stimulus Sensory applications Proximity and motion GENERAL DESCRIPTION The AD59321 is a waveform generator offering a programmable frequency scan. Utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency-stepped waveforms. Because frequency profiles are preprogrammed, continuous write cycles are eliminated, thereby freeing up valuable DSP/microcontroller resources. Waveforms start from a known phase and are incremented phase-continuously, which allows phase shifts to be easily determined. Consuming only 6.7 mA, the AD5932 provides a convenient low power solution to waveform generation. The AD5932 outputs each frequency in the range of interest for a defined length of time and then steps to the next frequency in the scan range. The length of time the device outputs a particular frequency is preprogrammed, and the device increments the frequency automatically; or, alternatively, the frequency is incremented externally via the CTRL pin. At the end of the range, the AD5932 continues to output the last frequency until the device is reset. The AD5932 also offers a digital output via the MSBOUT pin. (continued on Page 3) FUNCTIONAL BLOCK DIAGRAM AD5932 DVDD CAP/2.5V DGND INTERRUPT STANDBY AGND AVDD VCC 2.5V SYNC MCLK CTRL FSYNC SYNCOUT MSBOUT VOUT COMP SCLK SDATA DATA AND CONTROL FREQUENCY CONTROLLER INCREMENT CONTROLLER CONTROL REGISTER ON-BOARD REFERENCE FULL-SCALE CONTROL 24-BIT PIPELINED DDS CORE 10-BIT DAC SERIAL INTERFACE REGULATOR DATA INCR BUFFER BUFFER /24 05416-001 Figure 1. 1 Protected by U.S. patent number 6747583.

Rev. C | Page 3 of 28 GENERAL DESCRIPTION (continued from Page 1) To program the AD5932, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. The fre- quency scan profile is initiated, started, and executed by toggling the CTRL pin. The AD5932 is written to via a 3-wire serial interface that operates at clock rates up to 40 MHz. The device operates with a power supply from 2.3 V to 5.5 V . Note that the AVDD and DVDD are independent of each other and can be operated from different voltages. The AD5932 also has a standby function that allows sections of the device that are not in use to be powered down. The AD5932 is available in a 16-lead, Pb-free TSSOP.

Rev. C | Page 4 of 28 SPECIFICATIONS AVDD = DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Y Grade1 Parameter Min Typ Max Unit Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate 50 MSPS VOUT Peak-to-Peak 0.58 V Internal 200 Ω resistor to GND VOUT Offset 56 mV From 0 V to the trough of the waveform VMIDSCALE 0.32 V Voltage at midscale output VOUT TC 200 ppm/°C DC Accuracy Integral Nonlinearity (INL) ±1.5 LSB Differential Nonlinearity (DNL) ±0.75 LSB DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio 53 60 dB fMCLK = 50 MHz, fOUT = fMCLK/4096 Total Harmonic Distortion −60 −53 dBc fMCLK = 50 MHz, fOUT = fMCLK/4096 Spurious-Free Dynamic Range (SFDR) Wide Band (0 to Nyquist) −56 −52 dBc fMCLK = 50 MHz, fOUT = fMCLK/50 Narrow Band (±200 kHz) −74 −70 dBc fMCLK = 50 MHz, fOUT = fMCLK/50 Clock Feedthrough −50 dBc Up to 16 MHz out Wake-Up Time 1.7 ms From standby OUTPUT BUFFER VOUT Peak-to-Peak 0 DVDD V Typically, square wave on MSBOUT and SYNCOUT Output Rise/Fall Time2 12 ns VOLTAGE REFERENCE Internal Reference 1.15 1.18 1.26 V Reference TC2 90 ppm/°C LOGIC INPUTS2 Input Current 0.1 ±2 µA Input High Voltage, VINH 1.7 V DVDD = 2.3 V to 2.7 V 2.0 V DVDD = 2.7 V to 3.6 V 2.8 V DVDD = 4.5 V to 5.5 V Input Low Voltage, VINL 0.6 V DVDD = 2.3 V to 2.7 V 0.7 V DVDD = 2.7 V to 3.6 V 0.8 V DVDD = 4.5 V to 5.5 V Input Capacitance, CIN 3 pF LOGIC OUTPUTS2 Output High Voltage, VOH DVDD − 0.4 V V ISINK = 1 mA Output Low Voltage, VOL 0.4 V ISINK = 1 mA Floating-State O/P Capacitance 5 pF POWER REQUIREMENTS fMCLK = 50 MHz, fOUT = fMCLK/7 AVDD/DVDD 2.3 5.5 V IAA 3.8 4 mA IDD 2.4 2.7 mA IAA + IDD 6.2 6.7 mA

1 Operating temperature range is as follows: Y version: −40°C to +125°C; typical specifications are at +25°C. 2 Guaranteed by design, not production tested. Figure 2. Test Circuit Used to Test the Specifications

Figure 6. SYNCOUT Timing

Rev. C | Page 8 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to AGND −0.3 V to +6.0 V DVDD to DGND −0.3 V to +6.0 V AGND to DGND −0.3 V to +0.3 V CAP/2.5 V to DGND −0.3 V to +2.75 V Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature +150°C TSSOP (4-Layer Board) θJA Thermal Impedance 112°C/W θJC Thermal Impedance 27.6°C/W Reflow Soldering (Pb-Free) 300°C Peak Temperature 260(+0/−5)°C Time at Peak Temperature 10 sec to 40 sec Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

Figure 7. Pin Configuration Table 4. Pin Function Descriptions 1 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD. capacitor should be connected between AVDD and AGND. capacitor should be connected between DVDD and DGND. to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD. 5 DGND Ground for All Digital Circuitry. 6 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. the control register (SYNCOP bit). This pin must be enabled by setting the SYNCOUTEN bit in the control register to 1. setting the MSBOUTEN bit in the control register to 1. internal MCLK, which resets internal state machines. This results in the DAC output going to midscale. the MSB to LSBs of the data. 12 SCLK Serial Clock Input. Data is clocked into the AD5932 on each falling SCLK edge. the internal logic is informed that a new word is being loaded into the device. standby, as this results in a shutdown current of typically 20 µA. 15 AGND Ground for All Analog Circuitry. filter and to reduce clock feedthrough.

Rev. C | Page 14 of 28 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale and full scale. The error is expressed in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic that is present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD5932, THD is defined as: 65432 V VVVVVTHD 22222 log20)dB( ++++= where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonic. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in dB. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD5932 output spectrum.

Setting Up the Frequency Scan section. operating modes, as shown in the following bit map. individual bits of the control register. Table 5. Register Addresses Table 6. Description of Bits in the Control Register D15 to D12 ADDR Register address bits. D11 B24 Two write operations are required to load a complete word into the FSTART register and the Δf register. so the register never holds an intermediate value. independently of the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. for the appropriate addresses. D10 DAC ENABLE When DAC ENABLE = 1, the DAC is enabled. the MSB of the DAC input data (available at the MSBOUT pin). D9 SINE/TRI The function of this bit is to control what is available at the VOUT pin. resulting in a sinusoidal signal at the output. When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC. D8 MSBOUTEN When MSBOUTEN = 1, the MSBOUT pin is enabled. When MSBOUTEN = 0, the MSBOUT is disabled (three-state). D7 Reserved This bit must be set to 1. D6 Reserved This bit must be set to 1. D5 INT/EXT INCR When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin. When INT/EXT INCR = 0, the frequency increments are triggered automatically. D4 Reserved This bit must be set to 1. at the start of the subsequent scan. When SYNCSEL= 0, the SYNCOUT outputs a pulse of 4 × TCLOCK only at each frequency increment. D2 SYNCOUTEN When SYNCOUTEN = 1, the SYNC output is available at the SYNCOUT pin. When SYNCOUTEN = 0, the SYNCOP pin is disabled (three-state). D1 Reserved This bit must be set to 1. D0 Reserved This bit must be set to 1.

certain registers to be programmed to enable a frequency scan. must be performed: one to the LSBs and the other to the MSBs. (D11) should be set to 1, with the LSBs programmed first. and the MSBs of this register are shown in the following bit map. scan and is added incrementally to the current output frequency. thereby giving an increasing or decreasing frequency scan. register is output. Next, the frequency (FSTART + Δf ) is output. both the MSB and LSB registers of the Δf word. Table 7. Δf Register Bits the address shown in the following bit map. representing the maximum number of increments (4095). Table 8. N 0000 0000 0011 Three frequency increments. 0000 0000 0100 Four frequency increments. 1111 1111 1110 4094 frequency increments. 1111 1111 1111 4095 frequency increments.

• The duration is a multiple of cycles of the output frequency.
• The duration is a multiple of MCLK periods. The desired choice is selected by Bit D13 in the t INT register as shown in the following bit map. D15 D14 D13 D12 D11 D10 to D0 0 1 0 x x 11 bits <10…0> Fixed number of output waveform cycles. 0 1 1 x x 11 bits <10…0> Fixed number of clock periods. Programming of this register is in binary form, with the minimum number being decimal 2. Note that 11 bits, D10 to D0, of the register are available to program the time interval. As an example, if MCLK = 50 MHz, then each clock period/base interval is (1/50 MHz) = 20 ns. If each frequency must be output for 100 ns, then <00000000101> or decimal 5 must be pro- grammed to this register. Note that the AD5930 can output each frequency for a maximum duration of 211 − 1 (or 2047) times the increment interval.

applications, this maximum time of 40 µs may be insufficient. Table 9. Time-Base Multiplier Values for a minimum of 40 ns up to a maximum of 20.5 ms. that the same equally applies to fixed numbers of clock cycles.

• Auto-increment
• External increment Auto-Increment Control The value in the tINT register is used to control the scan. The AD5932 outputs each frequency for the length of time pro- grammed in the TINT register, before moving on to the next frequency. To set up the AD5932 to this mode, INT/EXT INCR (Bit D5) must be set to 0. External Increment Control In this case, the time interval, tINT, is set by the pulse rate on the CTRL pin. The first 0 to 1 transition on the pin starts the scan. Each subsequent 0 to 1 transition on the CTRL pin increments the output frequency by the value programmed into the ∆f register. To set up the AD5932 to this mode, INT/EXT INCR (Bit D5) must be set to 1. INTERRUPT Pin This function is used as an interrupt during a frequency scan. A low-to-high transition on this pin is sampled by the internal MCLK, thereby resetting internal state machines, which results in the output going to midscale. STANDBY Pin Sections of the AD5932 that are not in use can be powered down to minimize power consumption. This is done by using the STANDBY pin. For optimum power savings, it is recom- mended to reset the AD5932 before entering standby. Doing so reduces the power-down current to 20 μA. When this pin is high, the internal MCLK is disabled, and the reference, DAC, and regulator are powered down. When in this state, the DAC output of the AD5932 remains at its present value, because the NCO is no longer accumulating. When the device is taken back out of standby mode, the MCLK is re- activated, and the scan continues. To ensure correct operation for new data, it is recommended that the device be internally reset, using a control register write or using the INTERRUPT pin, and then restarted.

Rev. C | Page 22 of 28 EVALUATION BOARD The AD5932 evaluation board allows designers to evaluate the high performance AD5932 DDS modulator with minimum effort. The evaluation board interfaces to the USB port of a PC. It is possible to power the entire board from the USB port. All that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. The DDS evaluation kit includes a populated and tested AD5932 printed circuit board. The E VA L-AD5932EB kit is shipped with a CD-ROM that includes self-installing software. The PC is connected to the evaluation board using the supplied cable. The software is compatible with Microsoft® Windows® 2000 and Windows XP . A schematic of the evaluation board is shown in Figure 38 and Figure 39. Using the AD5932 Evaluation Board The AD5932 evaluation kit is a test system designed to simplify the evaluation of the AD5932. An application note is also available with the evaluation board that gives full information on operating the evaluation board. Prototyping Area An area is available on the evaluation board for the user to add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. XO vs. External Clock The AD5932 can operate with master clocks up to 50 MHz. A 50 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock can be connected to the part.

Figure 38. Page 1 of EVAL-AD5932EB Schematic

Figure 39. Page 2 of EVAL-AD5932EB Schematic

Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. C | Page 26 of 28 NOTES

Rev. C | Page 27 of 28 NOTES

Rev. C | Page 28 of 28 NOTES ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05416-0-4/17(C)