AD5734R

AD5724R/AD5734R/AD5754R (Rev. G)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 33

Technical content

Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs Data Sheet AD5724R/AD5734R/AD5754R Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Complete, quad, 12-/14-/16-bit DACs Operates from single/dual supplies Software programmable output range INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 µs typical Integrated reference: ±5 ppm/°C maximum Integrated reference buffers Output control during power-up/brownout Simultaneous updating via LDAC Asynchronous CLR to zero scale/midscale DSP/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: −40°C to +85°C iCMOS® process technology

APPLICATIONS

Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers GENERAL DESCRIPTION The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages of +4.5 V up to +16.5 V or dual supply voltages from ±4.5 V up to ±16.5 V . Nominal full-scale output range is software selectable from +5 V, + 1 0 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided. The devices offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, 10 µs typical settling time, and an on-chip +2.5 V reference. The AD5724R/AD5734R/AD5754R use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/2sCOMP) and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or mid- scale output. The devices are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range. Table 1. Pin Compatible Devices

AD5724R/AD5734R/AD5754R Data Sheet Rev. G | Page 2 of 33 TABLE OF CONTENTS

REVISION HISTORY

2/2017—Rev. F to Rev. G Added Alternative Power-Up Sequence Support Section, 2/2016—Rev. E to Rev. F 7/2011—Rev. D to Re v. E Changes to t 5/2011—Rev. C to Rev. D Changes to Configuring the AD5724R/AD5734R/ 7/2010—Rev. B to Rev. C 5/2010—Rev. A to Rev. B 3/2009—Rev. 0 to Rev. A Changes to Resolution and Integral Nonlinearity (INL) Added Ideal Output Voltage to Input Code 1/2009—Revision 0: Initial Version

Data Sheet AD5724R/AD5734R/AD5754R Rev. G | Page 3 of 33 FUNCTIONAL BLOCK DIAGRAM DAC C DAC D DAC B INPUT REGISTER A INPUT REGISTER B INPUT REGISTER C n n n n DAC A LDAC REFIN/REFOUT VOUTD VOUTC VOUTB VOUTA REFERENCE BUFFERS SDIN SCLK SYNC SDO CLR DVCC 2.5V REFERENCE GND BIN/2sCOMP DAC_GND (2) SIG_GND (2) AD5724R/AD5734R/AD5754R INPUT SHIFT REGISTER AND CONTROL LOGIC AVDDAVSS INPUT REGISTER D DAC REGISTER A DAC REGISTER B DAC REGISTER C DAC REGISTER D 06465-001 n AD5724R: n = 12-BIT AD5734R: n = 14-BIT AD5754R: n = 16-BIT Figure 1.

AD5724R/AD5734R/AD5754R Data Sheet Rev. G | Page 4 of 33 SPECIFICATIONS RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5754R 16 Bits AD5734R 14 Bits AD5724R 12 Bits Total Unadjusted Error (TUE) −0.1 +0.1 % FSR ±10 V range Integral Nonlinearity (INL)2 AD5754R −16 +16 LSB AD5734R −4 +4 LSB AD5724R −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic Bipolar Zero Error −6 +6 mV ±10 V range , TA = 25°C, error at other temperatures obtained using bipolar zero TC Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV ±10 V range , TA = 25°C, error at other temperatures obtained using zero-scale TC Zero-Scale TC3 ±4 ppm FSR/°C Offset Error −6 +6 mV ±10 V range , TA = 25°C, error at other temperatures obtained using offset error TC Offset Error TC3 ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, TA = 25°C, error at other temperatures obtained using gain TC Gain Error3 −0.065 0 +10 V and +5 V ranges, TA = 25°C, error at other temperatures obtained using gain TC Gain Error3 0 +0.08 ±5 V range, TA = 25°C, error at other temperatures obtained using gain TC Gain TC3 ±4 ppm FSR/°C DC Crosstalk3 120 µV REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 µA Reference Range 2 3 V Reference Output Output Voltage 2.497 2.501 V TA = 25°C Reference TC3, 4 1.8 5 ppm/°C TA = 0°C to 85°C 2.2 10 ppm/°C TA = −40°C to +85°C Output Noise (0.1 Hz to 10 Hz)3 5 µV p-p Noise Spectral Density3 75 nV/√Hz At 10 kHz OUTPUT CHARACTERISTICS3 Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V −12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±12 ppm FSR/500 hr ±15 ppm FSR/1000 hr Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω

Data Sheet AD5724R/AD5734R/AD5754R Rev. G | Page 5 of 33 Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DVCC = 2.7 V to 5.5 V, JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO)3 Output Low Voltage, VOL 0.4 V DVCC = 5 V ± 10%, sinking 200 µA Output High Voltage, VOH DVCC − 1 V DVCC = 5 V ± 10%, sourcing 200 µA Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 µA Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 µA High Impedance Leakage Current ±1 µA High Impedance Output Capacitance 5 pF POWER REQUIREMENTS AVDD 4.5 16.5 V AVSS −4.5 −16.5 V DVCC 2.7 5.5 V Power Supply Sensitivity3 ∆VOUT/∆ΑVDD −65 dB 200 mV sine wave superimposed on AVSS/AVDD at

50 Hz/60 Hz

AIDD 2.5 mA/channel Outputs unloaded 1.75 mA/channel AVSS = 0 V, outputs unloaded AISS 2.2 mA/channel Outputs unloaded DICC 0.5 3 µA VIH = DVCC, VIL = GND, 0.5 µA typical Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW +16.5 V operation, outputs unloaded Power-Down Currents All DAC channels and internal reference powered-down AIDD 40 µA AISS 40 µA DICC 300 nA 1 For specified performance, headroom requirement is 0.9 V. 2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5754R, AD5734R, and AD5724R respectively. 3 Guaranteed by characterization; not production tested. 4 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

AD5724R/AD5734R/AD5754R Data Sheet Rev. G | Page 6 of 33 AC PERFORMANCE CHARACTERISTICS CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 µs 20 V step to ±0.03 % FSR 7.5 8.5 µs 10 V step to ±0.03 % FSR 5 µs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/µs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise

0.1 Hz to 10 Hz Bandwidth 15 µV p-p 0x8000 DAC code

100 kHz Bandwidth 80 µV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, headroom requirement is 0.9 V. 2 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS CLOAD = 200 pF, all specifications are TMIN to TMAX, unless otherwise noted. Table 4. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t14 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t7 7 ns min Data setup time t8 2 ns min Data hold time t9 20 ns min LDAC falling edge to SYNC falling edge t10 130 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t12 10 µs typ DAC output settling time t13 20 ns min CLR pulse width low t14 2.5 µs max CLR pulse activation time t155 13 ns min SYNC rising edge to SCLK falling edge t165 40 ns max SCLK rising edge to SDO valid (CL SDO6 = 15 pF) t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 To accommodate t16, in readback and daisy-chain modes the SCLK cycle time must be increased to 90 ns. 5 Daisy-chain and readback mode. 6 CL SDO = capacitive load on SDO output.

Figure 2. Serial Interface Timing Diagram

0 B D3 2 B D 0 B D3 2 B D

Figure 3. Daisy-Chain Timing Diagram

0 B D3 2 B D0 B D3 2 B D

Figure 4. Readback Timing Diagram

Data Sheet AD5724R/AD5734R/AD5754R Rev. G | Page 9 of 33 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter Rating AVDD to GND −0.3 V to +17 V AVSS to GND +0.3 V to −17 V DVCC to GND −0.3 V to +7 V Digital Inputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) Digital Outputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) REFIN/REFOUT to GND −0.3 V to +5 V VOUTx to GND AVSS to AVDD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ max 150°C 24-Lead TSSOP θJA Thermal Impedance 42°C/W θJC Thermal Impedance 9°C/W Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE

FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration Table 6. Pin Function Descriptions 2, 6, 12, 13 NC No Connect. Do not connect to these pins. 3 VOUTA Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 4 VOUTB Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin should not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable). 14 DVCC Digital Supply Pin. Voltage range is from 2.7 V to 5.5 V. 15 GND Ground Reference Pin. clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV at 25°C. 18, 19 DAC_GND Ground reference pins for the four digital-to-analog converters. 20, 21 SIG_GND Ground reference pins for the four output amplifiers. 22 VOUTD Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 23 VOUTC Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 24 AVDD Positive Analog Supply Pin. Voltage range is from 4.5 V to 16.5 V. plane for enhanced thermal performance.

20 DEVICES SHOWN

Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C)

AD5724R/AD5734R/AD5754R Data Sheet Rev. G | Page 18 of 33 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ AD5734R/AD5754R are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 21. Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Zero-Scale Error/Negative Full-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale − 1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure 20. Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. It is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of full-scale settling time can be seen in Figure 25. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 22. Gain TC Gain TC is a measure of the change in gain error with changes in temperature. It is expressed in ppm FSR/°C. Total Unadjusted Error (TUE) Tot a l unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 29. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in millivolts and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 29. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs.

Data Sheet AD5724R/AD5734R/AD5754R Rev. G | Page 19 of 33 DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in LSBs. Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given tempera- ture range expressed in ppm/°C as follows; 610× −= TempRangeV VVTC REFnom REFminREFmax where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range, either 0°C to 85°C or −40°C to +85°C.

simultaneous updating of all DACs. Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC update now occurs on the falling edge of LDAC. remains at the cleared value until a new value is programmed. command in the control register. on the required channels and the internal reference, if required. either offset binary or twos complement. D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. output range selected by the user as shown in Table 7. Table 7. Internal Gain Values

Table 8. Bipolar Output, Offset Binary Coding Table 9. Bipolar Output, Twos Complement Coding Table 10. Unipolar Output, Straight Binary Coding

Table 11. Bipolar Output, Offset Binary Coding Table 12. Bipolar Output, Twos Complement Coding Table 13. Unipolar Output, Straight Binary Coding

Table 14. Bipolar Output, Offset Binary Coding Table 15. Bipolar Output, Twos Complement Coding Table 16. Unipolar Output, Straight Binary Coding

Table 17. AD5754R Input Register Format Table 18. Input Register Bit Functions

(see Table 20), and DB15 to DB4 for the AD5724R (see Table 21). Table 19. Programming the AD5754R DAC Register Table 20. Programming the AD5734R DAC Register Table 21. Programming the AD5724R DAC Register range bits (R2, R1, R0) select the required output range (see Table 22 and Table 23). Table 22. Programming the Required Output Range Table 23. Output Range Options

control function selected. The control register options are shown in Table 24 and Table 25. Table 24. Programming the Control Register Table 25. Control Register Functions NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR select See Table 26 for a description of the CLR select operation. overcurrent; the current is clamped at 20 mA. Cleared by the user to disable the current-limit clamp. The channel powers down on detection of overcurrent. Table 26. CLR Select Options

1 Midscale Negative full scale

power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 27 and Table 28. Table 27. Programming the Power Control Register Table 28. Power Control Register Functions is cleared, DAC A powers down automatically on detection of an overcurrent, and PUA is cleared to reflect this. is cleared, DAC B powers down automatically on detection of an overcurrent, and PUB is cleared to reflect this. is cleared, DAC C powers down automatically on detection of an overcurrent, and PUC is cleared to reflect this. is cleared, DAC D powers down automatically on detection of an overcurrent, and PUD is cleared to reflect this. internal reference in power-down mode (default). OCA DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. OCB DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. OCC DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set. OCD DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.

6.40 BSC

0.10 COPLANARITY

1.20 MAX

Figure 53. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] registered trademarks are the property of their respective owners.