AD5722/AD5732/AD5752 (Rev. F)
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- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 31
Technical content
Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs Data Sheet AD5722/AD5732/AD5752 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) Operates from single/dual supplies Software programmable output range INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs typical Integrated reference buffers Output control during power-up/brownout Simultaneous updating via LDAC Asynchronous CLR to zero scale or midscale DSP-/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: −40°C to +85°C iCMOS process technology
APPLICATIONS
Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers GENERAL DESCRIPTION The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial input, voltage output, digital-to-analog converters. They operate from single-supply voltages from +4.5 V up to +16.5 V or dual- supply voltages from ±4.5 V up to ±16.5 V . Nominal full-scale output range is software-selectable from +5 V , +10 V , +10.8 V , ±5 V , ±10 V , or ±10.8 V . Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided. The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, and 10 μs typical settling time. The AD5722/AD5732/AD5752 use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/2sComp ), and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range. The AD5722/AD5732/AD5752 are pin compatible with the AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/ 16-bit, serial input, unipolar/bipolar voltage output DACs. FUNCTIONAL BLOCK DIAGRAM DAC B INPUT REGISTER A INPUT REGISTER B DAC A LDAC REFIN VOUTB VOUTA REFERENCE BUFFERS SDIN SCLK SYNC SDO DVCC GND DAC_GND (2) SIG_GND (2) AD5722/AD5732/AD5752 INPUT SHIFT REGISTER AND CONTROL LOGIC AVDDAVSS DAC REGISTER A DAC REGISTER B CLR BIN/2sCOMP 06467-001 12/14/16 12/14/16 12/14/16 Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance.
AD5722/AD5732/AD5752 Data Sheet Rev. F | Page 2 of 31 TABLE OF CONTENTS
REVISION HISTORY
2/2017—Rev. E to Rev. F Added Alternative Power-Up Sequence Support Section, 2/2016—Rev. D to Rev. E 7/2011—Rev. C to Rev. D 3/2011—Rev. B to Rev. C Changes to Configuring the AD5722/AD5732/AD5752 Section .. 20 8/2010—Rev. A to Rev. B 5/2010—Rev. 0 to Rev. A Changes to Junction T emperature, T J max Parameter, Table 4 ... 8 10/08—Revision 0: Initial Version
Data Sheet AD5722/AD5732/AD5752 Rev. F | Page 3 of 31 SPECIFICATIONS CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5752 16 Bits AD5732 14 Bits AD5722 12 Bits Total Unadjusted Error (TUE) B Version −0.1 +0.1 % FSR ±10 V range A Version −0.3 +0.3 % FSR ±10 V range Integral Nonlinearity (INL)2 AD5752 A, B Versions −16 +16 LSB AD5732 A Version −4 +4 LSB AD5722 A Version −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, all versions, guaranteed monotonic Bipolar Zero Error −6 +6 mV ±10 V range, TA = 25°C, error at other temperatures obtained using bipolar zero TC Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV ±10 V range, TA = 25°C, error at other temperatures obtained using zero-scale TC Zero-Scale TC3 ±4 ppm FSR/°C Offset Error −6 +6 mV +10 V range, TA = 25°C, error at other temperatures obtained using zero-scale TC Offset Error TC ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, TA = 25°C, error at other temperatures obtained using gain TC Gain Error3 −0.065 0 +10 V and +5 V ranges, TA = 25°C, error at other temperatures obtained using gain TC Gain Error3 0 0.08 ±5 V range, TA = 25°C, error at other temperatures obtained using gain TC Gain TC3 ±4 ppm FSR/°C DC Crosstalk3 120 μV REFERENCE INPUT3 Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 μA Reference Range 2 3 V OUTPUT CHARACTERISTICS3 Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V −12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom Required 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±50 ppm FSR Drift after 1000 hours of life test @ 125°C Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω
AD5722/AD5732/AD5752 Data Sheet Rev. F | Page 4 of 31 Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DV CC = 2.7 V to 5.5 V, JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 μA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO)3 Output Low Voltage, VOL 0.4 V DV CC = 5 V ± 10%, sinking 200 μA Output High Voltage, VOH DV CC − 1 V DVCC = 5 V ± 10%, sourcing 200 μA Output Low Voltage, VOL 0.4 V DV CC = 2.7 V to 3.6 V, sinking 200 μA Output High Voltage, VOH DV CC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage Current −1 +1 μA High Impedance Output Capacitance 5 pF POWER REQUIREMENTS AVDD 4.5 16.5 V AVSS −4.5 −16.5 V DVCC 2.7 5.5 V Power Supply Sensitivity3 ∆VOUT/∆ΑVDD −65 dB AIDD 3.25 mA/channel Outputs unloaded 2.4 mA/channel AVSS = 0 V, outputs unloaded AISS 2.5 mA/channel Outputs unloaded DICC 0.5 3 μA VIH = DVCC, VIL = GND Power Dissipation 190 mW ±16.5 V operation, outputs unloaded 79 mW 16.5 V operation, AVSS = 0 V, outputs unloaded Power-Down Currents AIDD 40 μA AISS 40 μA DICC 300 nA 1 For specified performance, the maximum headroom requirement is 0.9 V. 2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively. 3 Guaranteed by characterization; not production tested.
Data Sheet AD5722/AD5732/AD5752 Rev. F | Page 5 of 31 AC PERFORMANCE CHARACTERISTICS CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 μs 20 V step to ±0.03% FSR 7.5 8.5 μs 10 V step to ±0.03% FSR 5 μs 512 LSB step se ttling (16-bit resolution) Slew Rate 3.5 V/μs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise
0.1 Hz to 10 Hz Bandwidth 15 μV p-p 0x8000 DAC code
100 kHz Bandwidth 80 μV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, the maximum headroom requirement is 0.9 V. 2 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS 200 pF; all specifications tMIN to tMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 Limit at t MIN, tMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t7 7 ns min Data setup time t8 2 ns min Data hold time t9 20 ns min LDAC falling edge to SYNC falling edge t10 130 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t12 10 μs max DAC output settling time t13 20 ns min CLR pulse width low t14 2.5 μs max CLR pulse activation time t154 13 ns min SYNC rising edge to SCLK falling edge t164 40 ns max SCLK rising edge to SDO valid (C L SDO5 = 15 pF) t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output.
Figure 4. Readback Timing Diagram
AD5722/AD5732/AD5752 Data Sheet Rev. F | Page 8 of 31 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AVDD to GND −0.3 V to +17 V AVSS to GND +0.3 V to −17 V DVCC to GND −0.3 V to +7 V Digital Inputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) Digital Outputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) REFIN to GND −0.3 V to +5 V VOUTA or VOUTB to GND AVSS to AVDD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ max 150°C 24-Lead TSSOP Package θJA Thermal Impedance 42°C/W θJC Thermal Impedance 9°C/W Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
- IT IS RECOMMENDED THAT THE
Figure 5. Pin Configuration Table 5. Pin Function Descriptions NC Do not connect to these pins. 3 V OUTA Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV CC or GND. transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. LDAC. The LDAC pin should not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable). 14 DV CC Digital Supply. Voltage ranges from 2.7 V to 5.5 V. out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. 18, 19 DAC_GND Ground Reference for the Two Digital-to-Analog Converters (DACs). 20, 21 SIG_GND Ground Reference for the Two Output Amplifiers. 23 V OUTB Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 24 AV DD Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
AD5722/AD5732/AD5752 Data Sheet Rev. F | Page 16 of 31 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5722/AD5732/ AD5752 are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 23. Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Zero-Scale Error or Negative Full-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale − 1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure 22. Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale TC is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time required for the output to settle to a specified level for a full-scale input change. A plot for full-scale settling time can be seen in Figure 27. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/μs. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 24. Gain TC Gain TC is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/°C. Tot a l Una dju ste d E r ror ( T UE ) Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in LSBs.
Data Sheet AD5722/AD5732/AD5752 Rev. F | Page 17 of 31 Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec.
only if SYNC is held low for the correct number of clock cycles. register to the addressed register. updated by taking LDAC low while SYNC is high. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 40. Daisy Chaining the AD5722/AD5732/AD5752 register. The serial clock can be a continuous or a gated clock. output contains the data from the previously addressed register. readback diagram in Figure 4 shows the readback sequence. bits, DB15 to DB0, are don’t care bits.
- Follow this with a second write, a NOP condition, 0x180000.
Table 7. Bipolar Output, Offset Binary Coding Table 8. Bipolar Output, Twos Complement Coding Table 9. Unipolar Output, Straight Binary Coding
Table 10. Bipolar Output, Offset Binary Coding Table 11. Bipolar Output, Twos Complement Coding Table 12. Unipolar Output, Straight Binary Coding
Table 13. Bipolar Output, Offset Binary Coding Table 14. Bipolar Output, Twos Complement Coding Table 15. Unipolar Output, Straight Binary Coding
Table 16. Input Register Format Table 17. Input Register Bit Functions R/W Indicates a read from or a write to the addressed register. select register, the power control register, or the control register. A2, A1, A0 These DAC address bits are used to decode the DAC channels.
AD5732 (see Table 19), and DB15 to DB4 for the AD5722 (see Table 20). Table 18. Programming the AD5752 DAC Register Table 19. Programming the AD5732 DAC Register Table 20. Programming the AD5722 DAC Register range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22). Table 21. Programming the Required Output Range Table 22. Output Range Options
control function selected. The control register options are shown in Table 23 and Table 24. Table 23. Programming the Control Register Table 24. Explanation of Control Register Options NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC regi sters to the clear code and updates the outputs. Load Addressing this function updates the DA C registers and, consequently, the DAC outputs. SDO Disable Set by the user to disabl e the SDO output. Cleared by the user to enable the SDO output (default). CLR Select See Table 25 for a description of the CLR select operation. current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. TSD Enable Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 25. CLR Select Options
1 Midscale Negative full-scale
power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register Table 27. Power Control Register Functions is cleared, DAC A powers down automatically on detection of an overcurrent, and PUA is cleared to reflect this. is cleared, DAC B powers down automatically on detection of an overcurrent, and PUB is cleared to reflect this. TSD Thermal shutdown alert (read-only bit). In the event of an overtemperature situation, both DACs are powered down and this bit is set. OCA DAC A overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC A, this bit is set. OCB DAC B overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC B, this bit is set.
Table 28. Some Precision References Recommended for Use with the AD5722/AD5732/AD5752
6.40 BSC
0.10 COPLANARITY
1.20 MAX
Figure 47. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] registered trademarks are the prop erty of their respective owners.