AD5725

AD5725 (Rev. C)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

Quad, 12-Bit, Parallel Input, Unipolar/Bipolar, Voltage Output DAC Data Sheet AD5725 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

+5 V to ±15 V operation Unipolar or bipolar operation ±0.5 LSB max INL error, ±1 LSB max DNL error Settling time: 10 µs max (10 V step) Double-buffered inputs Simultaneous updating via LDAC Asynchronous CLR to zero/mid scale Readback Operating temperature range: −40°C to +85°C iCMOS® process technology

APPLICATIONS

Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers FUNCTIONAL BLOCK DIAGRAM DAC C DAC D DAC B DAC A DGND AD5725 VOUTA VOUTB VOUTC VOUTD I/O REGISTER AND CONTROL LOGIC VREFPAVDDAVSS VL R/W CS DB0 TO DB11 VREFNLDACCLR INPUT REG A INPUT REG B INPUT REG C INPUT REG D DAC REG A DAC REG B DAC REG C DAC REG D 06442-001 Figure 1. GENERAL DESCRIPTION The AD5725 is a quad, 12-bit, parallel input, voltage output digital-to-analog converter that offers guaranteed monotonicity, integral nonlinearity (INL) of ±0.5 LSB maximum and 10 µs maximum settling time. Output voltage swing is set by two reference inputs, VREFP and VREFN. By setting the VREFN input to 0 V and the VREFP to a positive voltage, the DAC provides a unipolar positive output range. A similar configuration with VREFP at 0 V and VREFN at a negative voltage provides a unipolar negative output range. Bipolar outputs are configured by connecting both VREFP and VREFN to nonzero voltages. This method of setting output voltage ranges has advantages over the bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. Digital controls allow the user to load or read back data from any DAC, load any DAC, and transfer data to all DACs at one time. The AD5725 is available in a 28-lead SSOP package. It can be operated from a wide variety of supply and reference voltages, with supplies ranging from single +5 V to ±15 V , and references from +2.5 V to ±10 V . Power dissipation is less than 270 mW with ±15 V supplies and only 40 mW with a +5 V supply. Operation is specified over the temperature range of −40°C to +85°C. iCMOS® Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.

Rev. C | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

8/13—Rev. B to Rev. C Change Junction Temperature from 105°C to 150°C; Changed Power Dissipation Package Condition from Derate 10 mW/°C 4/13—Rev. A to Rev. B 12/08—Rev. 0 to Rev. A 7/07—Revision 0: Initial Version Power Dissipation Package (Derate 10 mW/°C Above 60°C)

Rev. C | Page 3 of 20 SPECIFICATIONS AVDD = +15 V , A VSS = −15 V , DGND = 0 V; VREFP = +10 V; VREFN = −10 V, VL = 5 V. All specifications TMIN to TMAX, unless otherwise noted.1 Table 1. Parameter Value Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 12 Bits Relative Accuracy (INL) ±0.5 LSB max B grade ±1 LSB max A grade Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Zero-Scale Error ±2 LSB max RL = 2 kΩ Zero-Scale TC2 ±15 ppm FSR/°C typ RL = 2 kΩ Full-Scale Error ±2 LSB max RL = 2 kΩ Full-Scale TC2 ±20 ppm FSR/°C typ RL = 2 kΩ REFERENCE INPUT VREFP Reference Input Range3 VREFN + 2.5 V min AVDD − 2.5 V max Input Current ±2.75 mA max Typically 1.5 mA VREFN Reference Input Range3 −10 V min VREFP − 2.5 V max Input Current2 0 mA max Typically −2 mA −2.75 mA min Large Signal Bandwidth2 160 kHz typ −3 dB, VREFP = 0 V to 10 V p-p OUTPUT CHARACTERISTICS2 Output Current ±5 mA max RL = 2 kΩ, CL = 100 pF DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant VIH, Input High Voltage 2.4 V min TA = 25°C VIL, Input Low Voltage 0.8 V max TA = 25°C Input Current2 1 µA max Input Capacitance2 8 pF typ DIGITAL OUTPUTS (SDO) VOH, Output High Voltage 4 V min IOH = 0.4 mA VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity2 30 ppm FSR/V max 14.25 V ≤ AVDD ≤ 15.75 V AIDD 3 mA/channel max Outputs unloaded, VREFP = 2.5 V, typically 2.125 mA AISS 2.5 mA/channel max Outputs unloaded, typically 1.625 mA Power Dissipation 270 mW max 1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies. 2 Guaranteed by design and characterization, not production tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

Rev. C | Page 4 of 20 AVDD = +5 V , A VSS = −5 V/0 V, DGND = 0 V; VREFP = +2.5 V; VREFN = −2.5 V/0 V, VL = 5 V . All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Value Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 12 Bits Relative Accuracy (INL) ±0.5 LSB max B grade ±1 LSB max A grade ±1 LSB max B grade, AVSS = 0 V1 ±2 LSB max A grade, AVSS = 0 V1 Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Zero-Scale Error ±5 LSB max AVSS = −5 V ±10 LSB max AVSS = 0 V Zero-Scale TC2 100 ppm FSR/°C typ Full-Scale Error ±5 LSB max AVSS = −5 V ±10 LSB max AVSS = 0 V Full-Scale TC2 100 ppm FSR/°C typ REFERENCE INPUT VREFP Reference Input Range3 VREFN + 2.5 V min AVDD − 2.5 V max Input Current2 ±0.5 mA max Code 0x0000 VREFN Reference Input Range3 −2.5 V min AVSS = −5 V

0 V min AVSS = 0 V

VREFP − 2.5 V max Large Signal Bandwidth2 450 kHz typ −3 dB, VREFP = 0 V to 2.5 V p-p OUTPUT CHARACTERISTICS2 Output Current ±1.25 mA max RL = 2 kΩ, CL = 100 pF DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant VIH, Input High Voltage 2.4 V min TA = 25°C VIL, Input Low Voltage 0.8 V max TA = 25°C Input Current2 1 µA max Input Capacitance2 8 pF typ DIGITAL OUTPUTS (SDO) VOH, Output High Voltage 4 V min IOH = 0.4 mA VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity2 100 ppm FSR/V typ AIDD 2 mA/channel max Outputs unloaded. AISS 1.5 mA/channel max Outputs unloaded, AVSS = −5 V Power Dissipation 70 mW max AVSS = −5 V 40 mW max AVSS = 0 V 1 For single supply operation only (VREFN = 0 V, AVSS = 0 V): Due to internal offset errors, INL and DNL are measured beginning at code 0x005. 2 Guaranteed by design and characterization, not production tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

Rev. C | Page 5 of 20 AC PERFORMANCE CHARACTERISTICS1 AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, DGND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter A Grade B Grade Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 10 µs typ To 0.01%, 10 V step, RL = 1 kΩ 7 7 µs typ To 0.01%, 2.5 V step, RL = 1 kΩ Slew Rate 2.2 2.2 V/µs typ 10% to 90% Analog Crosstalk 72 72 dB typ Digital Feedthrough 5 5 nV-s typ 1 Guaranteed by design and characterization, not production tested.

Rev. C | Page 6 of 20 TIMING CHARACTERISTICS1, 2 AVDD = +5 V/+15 V , AVSS = −5 V/0 V/−15 V , DGND = 0 V; VREFP = +2.5 V/+10 V; VREFN = −2.5 V/0 V/−10 V, VL = 5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Limit at TMIN, TMAX Unit Description tWCS 10 ns min Chip Select Write Pulse Width tWS 0 ns min Write Setup, tWCS = 10 ns tWH 0 ns min Write Hold, tWCS = 10 ns tAS 0 ns min Address Setup tAH 0 ns min Address Hold tLS 5 ns min Load Setup tLH 5 ns min Load Hold tWDS 5 ns min Write Data Setup, tWCS = 10 ns tWDH 0 ns min Write Data Hold, tWCS = 10 ns tLDW 10 ns min Load Data Pulse Width tRESET 10 ns min Reset Pulse Width tRCS 30 ns min Chip Select Read Pulse Width tRDH 0 ns min Read Data Hold, tRCS = 30 ns tRDS 0 ns min Read Data Setup, tRCS = 30 ns tDZ 15 ns max Data to High-Z, CL = 10 pF tCSD 35 ns max Chip Select to Data, CL = 100 pF 1 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 Guaranteed by design and characterization, not production tested.

Rev. C | Page 8 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter Rating AVSS to DGND +0.3 V to −16.5 V AVDD to DGND −0.3 V to +16.5 V AVSS to AVDD +0.3 V to −33 V VL to DGND −0.3 V to +7 V Current into Any Pin ±15 mA Digital Pin Voltage to DGND −0.3 V to +7 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 28-Lead SSOP Package θJA Thermal Impedance 100°C/W θJC Thermal Impedance 39°C/W Power Dissipation Package (Derate 10 mW/°C Above 60°C) 900 mW Reflow Soldering Time at Peak Temperature 10 sec to 40 sec Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 6. Pin Configuration Diagram Table 6. Pin Function Descriptions 1 VREFP Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage. Allowable range is AVDD − 2.5 V to VREFN + 2.5 V. 2 VOUTB Buffered Analog Output Voltage of DAC B. 3 VOUTA Buffered Analog Output Voltage of DAC A. 4 AVSS Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V. 7 LDAC Active Low Load DAC Input. 23 CS Active Low Chip Select Pin. 24 VL Voltage Supply for Readback Function. Can be left open circuit if not used. 25 AVDD Positive Analog Supply Pin. Voltage ranges from +5 V to +15 V. 26 VOUTD Buffered Analog Output Voltage of DAC D. 27 VOUTC Buffered Analog Output Voltage of DAC C. 28 VREFN Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output voltage. Allowable range is AVSS to VREFP − 2.5 V.

Rev. C | Page 14 of 20 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 16. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 17. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5725 is monotonic over its full operating temperature range. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be V REFP − 1 LSB. Full-scale error is expressed in LSBs. A plot of full-scale error vs. temperature can be seen in Figure 11. Full-Scale Error TC Full-scale error TC is a measure of the change in full-scale error with a change in temperature. Full-scale error TC is expressed in ppm FSR/°C. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC register. Ideally, the output voltage should be VREFN. A plot of zero-scale error vs. temperature can be seen in Figure 12. Zero-Scale Error TC Zero-scale error TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage- output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. Analog Crosstalk Analog crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in dB.

Rev. C | Page 15 of 20 THEORY OF OPERATION The AD5725 is a quad voltage output, 12-bit parallel input DAC featuring a 12-bit data bus with readback capability. The AD5725 operates from single or dual supplies ranging from +5 V up to ±15 V . The output voltage range is set by the reference voltages applied at the VREFP and VREFN pins. DAC ARCHITECTURE Each of the four DACs is a voltage switched, high impedance (50 kΩ), R-2R ladder configuration. Each 2R resistor is driven by a pair of switches that connect the resistor to either VREFH or VREFL. OUTPUT AMPLIFIERS The output amplifiers are capable of generating both unipolar and bipolar output voltages. They are capable of driving a load of 2 kΩ in parallel with 500 pF to DGND. The source and sink capabilities of the output amplifiers can be seen in Figure 23 and Figure 24. The slew rate is 2.2 V/µs with a full-scale settling time of 10 µs. The amplifiers are short-circuit protected. Careful attention to grounding is important for accurate operation of the AD5725. With four outputs and two references there is potential for ground loops. Since the AD5725 has no analog ground, the ground must be specified with respect to the reference. REFERENCE INPUTS All four DACs share common positive reference (VREFP) and negative reference (VREFN) inputs. The voltages applied to these reference inputs set the output high and low voltage limits on all four of the DACs. Each reference input has voltage restrictions with respect to the other reference and to the power supplies. V REFN can be any voltage between AVSS and VREFP − 2.5 V and VREFP can be any value between AVDD – 2.5 V and VREFN + 2.5 V . Note that because of these restrictions, the AD5725 references cannot be inverted (VREFN cannot be greater than VREFP). It is important to note that the AD5725 VREFP input both sinks and sources current. Also, the input current of both VREFP and VREFN are code dependent. Many references have limited current sinking capability and must be buffered with an amplifier to drive VREFP. The VREFN reference input has no such special requirements. It is recommended that the reference inputs be bypassed with 0.2 µF capacitors when operating with ±10 V references. This limits the reference bandwidth. PARALLEL INTERFACE See Table 7 for the digital control logic truth table. The parallel interface consists of a 12-bit bidirectional data bus, two register select inputs, A0 and A1, a R/W input, a chip select (CS), and a load DAC (LDAC) input. Control of the DACs and bus direction is determined by these inputs as shown in Table 7. Digital data bits are labeled with the MSB defined as Data Bit 11 and the LSB as Data Bit 0. All digital pins are TTL/CMOS compatible. The register select inputs A0 and A1 select individual DAC Register A (Binary Code 00) through Register D (Binary Code 11). Decoding of the registers is enabled by the CS input. When CS is high, no decoding takes place, and neither the writing nor the reading of the input registers is enabled. The loading of the second bank of registers is controlled by the asynchronous LDAC input. By taking LDAC low while CS is high, all output registers can be updated simultaneously. Note that the tLDW required pulse width for updating all DACs is a minimum of 10 ns. The R/W input, when enabled by CS, controls the writing to and reading from the input register. DATA CODING The AD5725 uses binary coding. The output voltage can be calculated as follows: ( ) 4096 DVVVV REFNREFP REFNOUT ×−+= where D is the digital code in decimal. CLR The CLR function can be used either at power-up or at any time during the DACs operation. The CLR function is independent of CS. This pin is active low and sets the DAC registers to either midscale code (0x800) for the AD5725 or zero code (0x000) for the AD5725-1. The CLR to midscale code is most useful when the DAC is configured for bipolar references and an output of 0 V is desired.

Table 7. AD5725 Logic Truth Table

supply; its operating range is between +5 V and +15 V. VL is the digital output supply voltage for the readback function. digital outputs when the readback function is used. either symmetrical or nonsymmetrical. Figure 27. Unipolar +10 V Operation Figure 28. Symmetrical Bipolar Operation potentiometer to attain a DAC output voltage of 9.9976 V . Figure 28 should be used whenever ±10 V references are used. 200 Ω for the loading of a single AD5725. whereas with a single reference, most drifts will track.

10 V full-scale output, the circuit can be configured as shown in

Figure 29. In this configuration, the full-scale value is set first by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

0.05 MIN

0.65 BSC

2.00 MAX

Figure 31. 28-Lead Shrink Small Outline Package [SSOP]

Rev. C | Page 20 of 20 NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06442-0-8/13(C)