AD5721R

AD5761R/AD5721R (Rev. C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

Multiple Range, 16-/12-Bit, Bipolar/Unipolar Voltage Output DACs with 2 ppm/°C Reference Data Sheet AD5761R/AD5721R Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

8 software-programmable output ranges: 0 V to +5 V, 0 V to +10 V, 0 V to +16 V, 0 V to +20 V, ±3 V, ±5 V, ±10 V, and −2.5 V to +7.5 V; 5% overrange Low drift 2.5 V reference: ±2 ppm/°C typical Total unadjusted error (TUE): 0.1% FSR maximum 16-bit resolution: ±2 LSB maximum INL Guaranteed monotonicity: ±1 LSB maximum Single channel, 16-/12-bit DACs Settling time: 7.5 μs typical Integrated reference buffers Low noise: 35 nV/√Hz Low glitch: 1 nV-sec (0 V to 5 V range) 1.7 V to 5.5 V digital supply range Asynchronous updating via LDAC Asynchronous RESET to zero scale/midscale DSP-/microcontroller-compatible serial interface Robust 4 kV HBM ESD rating 16-lead, 3 mm × 3 mm LFCSP package 16-lead TSSOP package Operating temperature range: −40°C to +125°C

APPLICATIONS

Instrumentation, data acquisition Open-/closed-loop servo control, process control Programmable logic controllers GENERAL DESCRIPTION The AD5761R/AD5721R are single channel, 16-/12-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages from +4.75 V to +30 V or dual supply voltages from −16.5 V to 0 V V SS and +4.75 V to +16.5 V VDD. The integrated output amplifier, reference buffer, and reference provide a very easy to use, universal solution. The devices offer guaranteed monotonicity, integral nonlinearity (INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling time on selected ranges. The AD5761R/AD5721R use a serial interface that operates at clock rates of up to 50 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the asynchronous updating of the DAC output. The input coding is user-selectable twos complement or straight binary. The asynchronous reset function resets all registers to their default state. The output range is user selectable, via the RA[2:0] bits in the control register. The devices available in a 3 mm × 3 mm LFCSP package and a 16-lead TSSOP package offer guaranteed specifications over the −40°C to +125°C industrial temperature range. FUNCTIONAL BLOCK DIAGRAM 12-BIT/ 16-BIT DAC LDAC VOUT REFERENCE BUFFERS SDI SCLK SYNC SDO RESET VDD VSS DVCC INPUT SHIFT REGISTER AND CONTROL LOGIC DGND AGND AD5761R/AD5721R CLEAR INPUT REG DAC REG 12/1612/16 2.5V REFERENCE ALERT VREFIN/VREFOUT DNC NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 12355-001 0V TO 5V 0V TO 10V 0V TO 16V 0V TO 20V ±3V ±5V ±10V −2.5V TO +7.5V Figure 1.

AD5761R/AD5721R Data Sheet Rev. C | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

1/2018—Rev. B to Rev. C Change to DB[15:11] Column, Table 11 and RA[2:0] 10/2016—Rev. A to Rev. B 5/2015—Rev. 0 to Rev. A Changes to Digital-to-Analog Converter Section and Internal Changes to Asynchronous Clear Function (CLEAR Changes to Power Supply Considerations Section and 11/2014—Revision 0: Initial Version

Data Sheet AD5761R/AD5721R Rev. C | Page 3 of 36 SPECIFICATIONS for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF , all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter2 Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE External reference3 and internal reference, outputs unloaded Programmable Output Ranges 0 5 V 0 10 V 0 16 V 0 20 V −2.5 +7.5 V −3 +3 V −5 +5 V −10 +10 V AD5761R Resolution 16 Bits Relative Accuracy, INL A Grade −8 +8 LSB External reference3 and internal reference B Grade4 −2 +2 LSB All ranges except 0 V to 16 V and 0 V to 20 V, VREFIN/VREFOUT = 2.5 V external and internal reference Differential Nonlinearity, DNL −1 +1 LSB AD5721R Resolution 12 Bits Relative Accuracy, INL B Grade −0.5 +0.5 LSB External reference3 and internal reference Differential Nonlinearity, DNL −0.5 +0.5 LSB Zero-Scale Error −6 +6 mV All ranges except ±10 V and 0 V to 20 V, external reference3 −10 +10 mV 0 V to 20 V, ±10 V ranges, external reference3 −6 +6 mV All ranges except ±5 V, ±10 V and 0 V to 20 V, internal reference −8 +8 mV ±5 V range, internal reference −9 +9 mV 0 V to 20 V range, internal reference −13 +13 mV ±10 V range, internal reference Zero-Scale Temperature Coefficient (TC)5 ±5 µV/°C Unipolar ranges, external reference3 and internal reference ±15 µV/°C Bipolar ranges, external reference3 and internal reference Bipolar Zero Error −5 +5 mV All bipolar ranges except ±10 V −7 +7 mV ±10 V output range Bipolar Zero TC5 ±2 µV/°C ±3 V range, external reference3 and internal reference ±5 µV/°C All bipolar ranges except ±3 V range, external reference3 and internal reference Offset Error −6 +6 mV All ranges except ±10 V and 0 V to 20 V, external reference3 −10 +10 mV 0 V to 20 V, ±10 V ranges, external reference3 −6 +6 mV All ranges except ±5 V, ±10 V, and 0 V to 20 V; internal reference −8 +8 mV ±5 V range, internal reference −9 +9 mV 0 V to 20 V range, internal reference −13 +13 mV ±10 V range, internal reference

AD5761R/AD5721R Data Sheet Rev. C | Page 4 of 36 Parameter2 Min Typ Max Unit Test Conditions/Comments Offset Error TC5 ±5 µV/°C Unipolar ranges, external reference3 and internal reference ±15 µV/°C Bipolar ranges, external reference3 and internal reference Gain Error −0.1 +0.1 % FSR External reference3 −0.15 +0.15 % FSR Internal reference Gain Error TC5 ±1.5 ppm FSR/°C External reference3 and internal reference TUE −0.1 +0.1 % FSR External reference3 −0.15 +0.15 % FSR Internal reference REFERENCE INPUT (EXTERNAL)5 Reference Input Voltage (VREF) 2.5 V ±1% for specified performance Input Current −2 ±0.5 +2 µA Reference Range 2 3 V REFERENCE OUTPUT (INTERNAL)5 Output Voltage 2.5 V ±3 mV, at ambient temperature Voltage Reference TC 2 5 ppm/°C Output Impedance 25 kΩ Output Voltage Noise 6 µV p-p 0.1 Hz to 10 Hz Noise Spectral Density 10 nV/√Hz At ambient; f = 10 kHz Line Regulation 6 µV/V At ambient Thermal Hysteresis 80 ppm First temperature cycle Start-Up Time 3.5 ms Coming out of power-down mode with a 10 nF capacitor on the VREFIN/VREFOUT pin to improve noise performance; outputs unloaded OUTPUT CHARACTERISTICS5 Output Voltage Range −VOUT +VOUT See Table 7 for the different output voltage ranges available −10 +10 V VDD/VSS = ±11 V, ±10 V output range −10.5 +10.5 V VDD/VSS = ±11 V, ±10 V output range with 5% overrange Capacitive Load Stability 1 nF Headroom 0.5 1 V RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V to 20 V ranges (RLOAD = 2 kΩ) Output Voltage TC ±3 ppm FSR/°C ±10 V range, external reference Short-Circuit Current 25 mA Short on the VOUT pin Resistive Load 1 kΩ All ranges except 0 V to16 V and 0 V to 20 V 2 kΩ 0 V to 16 V, 0 V to 20 V ranges Load Regulation 0.3 mV/mA Outputs unloaded DC Output Impedance 0.5 Ω Outputs unloaded LOGIC INPUTS5 DVCC = 1.7 V to 5.5 V, JEDEC compliant Input Voltage High, VIH 0.7 × DVCC V Low, VIL 0.3 × DVCC V Input Current Leakage Current −1 +1 µA SDI, SCLK, SYNC −1 +1 µA LDAC, CLEAR, RESET pins held high −55 µA LDAC, CLEAR, RESET pins held low Pin Capacitance 5 pF Per pin, outputs unloaded

Data Sheet AD5761R/AD5721R Rev. C | Page 5 of 36 Parameter2 Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (SDO, ALERT)5 Output Voltage Low, VOL 0.4 V DVCC = 1.7 V to 5.5 V, sinking 200 µA High, VOH DVCC − 0.5 V DVCC = 1.7 V to 5.5 V, sourcing 200 µA High Impedance, SDO Pin Leakage Current −1 +1 µA Pin Capacitance 5 pF POWER REQUIREMENTS VDD 4.75 30 V VSS −16.5 0 V DVCC 1.7 5.5 V IDD 5.1 6.5 mA Outputs unloaded, external reference ISS 1 3 mA Outputs unloaded DICC 0.005 1 µA VIH = DVCC, VIL = DGND Power Dissipation 67.1 mW ±11 V operation, outputs unloaded, TSSOP package DC Power Supply Rejection Ratio (PSRR)5 0.1 mV/V VDD ± 10%, VSS = −15 V 0.1 mV/V VSS ±10%, VDD = +15 V AC PSRR5 65 dB VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, internal reference, CLOAD = 100 nF 65 dB VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, internal reference, CLOAD = 100 nF 80 dB VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, external reference, CLOAD = unloaded 80 dB VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, external reference, CLOAD = unloaded 1 For specified performance, headroom requirement is 1 V. 2 Temperature range: −40°C to +125°C, typical at +25°C. 3 External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange. 4 Integral nonlinearity error is specified at ±4 LSB (min/max) for 16 V and 20 V ranges with VREFIN/VREFOUT = 2.5 V external and internal, and for all ranges with VREFIN/VREFOUT = 2 V to 2.85 V with overrange and 2 V to 3 V without overrange. 5 Guaranteed by design and characterization, not production tested.

AD5761R/AD5721R Data Sheet Rev. C | Page 6 of 36 AC PERFORMANCE CHARACTERISTICS for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE3 Output Voltage Settling Time 9 12.5 µs 20 V step to 1 LSB at 16-bit resolution 7.5 8.5 µs 10 V step to 1 LSB at 16-bit resolution 5 µs 512 LSB step to 1 LSB at 16-bit resolution Digital-to-Analog Glitch Impulse 8 nV-sec ±10 V range 1 nV-sec 0 V to 5 V range Glitch Impulse Peak Amplitude 15 mV ±10 V range 10 mV 0 V to 5 V range Power-On Glitch 100 mV p-p Digital Feedthrough 0.6 nV-sec Output Noise

0.1 Hz to 10 Hz Bandwidth 15 µV p-p

100 kHz Bandwidth 45 µV rms 0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference 35 µV rms 0 V to 10 V, ±10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference 25 µV rms ±5 V range, 2.5 V external reference 15 µV rms 0 V to 5 V and ±3 V ranges, 2.5 V external reference Output Noise Spectral Density, at 10 kHz 80 nV/√Hz ±10 V range, 2.5 V external reference 35 nV/√Hz ±3 V range, 2.5 V external reference 70 nV/√Hz ±5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference 110 nV/√Hz 0 V to 20 V range, 2.5 V external reference 90 nV/√Hz 0 V to 16 V range, 2.5 V external reference 45 nV/√Hz 0 V to 5 V range, 2.5 V external reference Total Harmonic Distortion (THD)4 −87 dB 2.5 V external reference, 1 kHz tone Signal-to-Noise Ratio (SNR) 92 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz Peak Harmonic or Spurious Noise (SFDR) 92 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz Signal-to-Noise-and-Distortion (SINAD) Ratio 85 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz 1 For specified performance, headroom requirement is 1 V. 2 Temperature range: −40°C to +125°C, typical at +25°C. 3 Guaranteed by design and characterization, not production tested. 4 Digitally generated sine wave at 1 kHz.

DVCC = 1.7 V to 5.5 V , all specifications TMIN to TMAX, unless otherwise noted. 1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode. 2 CL_SDO is the capacitive load on the SDO output. Figure 2. Serial Interface Timing Diagram

Data Sheet AD5761R/AD5721R Rev. C | Page 9 of 36 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 200 mA do not cause silicon controlled rectifier (SCR) latch-up. Table 4. Parameter Rating VDD to AGND −0.3 V to +34 V VSS to AGND +0.3 V to −17 V VDD to VSS −0.3 V to +34 V DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) Digital Outputs to DGND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) VREFIN/VREFOUT to DGND −0.3 V to +7 V VOUT to AGND VSS to VDD AGND to DGND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ MAX 150°C 16-Lead TSSOP Package θJA Thermal Impedance 113°C/W1 θJC Thermal Impedance 28°C/W 16-Lead LFCSP Package θJA Thermal Impedance 75°C/W1 θJC Thermal Impedance 4.5°C/W2 Power Dissipation (TJ MAX − TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 4 kV 1 JEDEC 2S2P test board, still air (0 m/sec airflow). 2 Measured to exposed paddle, with infinite heat sink on package top surface. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. DNC = DO NOT CONNECT. DO NOT CONNECT

Figure 5. 16-Lead TSSOP Pin Configuration Table 5. 16-Lead TSSOP Pin Function Descriptions a hardware reset, for which a write to the control register asserts the pin high. selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. because there is an internal pull-up resistor. VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise. 5 AGND Ground Reference Pin for Analog Circuitry. unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND. 7 VOUT Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load. 9 DNC Do Not Connect. Do not connect to this pin. out on the rising edge of SCLK and is valid on the falling edge of SCLK. until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor. 12 SDI Serial Data Input. Data must be valid on the falling edge of SCLK. SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC. clock speeds of up to 50 MHz.

1. THE EXPOSED PAD MUST BE MECHANICALLY CONNECTED TO THE PCB

CAN BE LEFT ELECTRICALLY FLOATING. Figure 6. 16-Lead LFCSP Pin Configuration Table 6. 16-Lead LFCSP Pin Function Descriptions because there is an internal pull-up resistor. VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise. 3 AGND Ground Reference Pin for Analog Circuitry. unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND. 5 VOUT Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load. 7 DNC Do Not Connect. Do not connect to this pin. out on the rising edge of SCLK and is valid on the falling edge of SCLK. until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor. 10 SDI Serial Data Input. Data must be valid on the falling edge of SCLK. SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC. clock speeds of up to 50 MHz. a hardware reset, for which a write to the control register asserts the pin high. selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. performance. The exposed pad can be left electrically floating.

Figure 55. Full-Scale Settling Time at Various Capacitive Loads,

0 V to 5 V Range

Figure 56. Digital-to-Analog Glitch Energy, 5 V Range Figure 57. Digital-to-Analog Glitch Energy, ±10 V Range Figure 58. Power-Up Glitch Figure 59. Software Full Reset Glitch from Full Scale with Output Loaded, Figure 60. Software Full Reset Glitch from Midscale with Output Loaded,

5 V Range

Figure 61. Software Full Reset Glitch from Zero Scale with Output Loaded, Figure 62. Software Full Reset Glitch from Full Scale with Output Loaded, Figure 63. Software Full Reset Glitch from Midscale with Output Loaded, Figure 64. Software Full Reset Glitch from Zero Scale with Output Loaded, Figure 65. Output Range Change Glitch, 0 V to 5 V Range Figure 66. Output Range Change Glitch, ±10 V Range

Figure 67. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz

30 NOISE EXT REF

Figure 68. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth Figure 69. DAC Output Noise Spectral Density (NSD) vs. Frequency, Figure 70. Digital Feedthrough Figure 71. Total Harmonic Distortion

Data Sheet AD5761R/AD5721R Rev. C | Page 23 of 36 TERMINOLOGY T otal Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. DAC code plot is shown in Figure 7. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. The AD5761R/AD5721R are guaranteed monotonic. A typical DNL error vs. code plot is shown in Figure 11. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5761R/AD5721R are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding) for the AD5761R/AD5721R. Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in µV/°C. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage is negative full scale. A plot of zero-scale error vs. temperature is shown in Figure 21. Zero-Scale Error Temperature Coefficient (TC) Zero-scale error TC is a measure of the change in zero-scale error with a change in temperature. It is expressed in µV/°C. Offset Error Offset error is a measure of the difference between V OUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset Error T emperature Coefficient (TC) Offset error TC is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature is shown in Figure 24. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature. It is expressed in ppm FSR/°C. DC Power Supply Rejection Ratio (DC PSRR) DC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the DAC. It is measured for a given dc change in power supply voltage and is expressed in mV / V. AC Power Supply Rejection Ratio (AC PSRR) AC power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Full-scale settling time is shown in Figure 48 to Figure 51. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (see Figure 56 and Figure 57). Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Noise Spectral Density (NSD) Noise spectral density is a measurement of the internally generated random noise characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to full scale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density is shown in Figure 69.

AD5761R/AD5721R Data Sheet Rev. C | Page 24 of 36 Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C as follows: __ 10× −= RangeTempV VVTC NOMREF MINREFMAXREF where: VREF_MAX is the maximum reference output measured over the total temperature range. VREF_MIN is the minimum reference output measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V . Temp Range is the specified temperature range, −40°C to +125°C. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD5761R/AD5721R, it is defined as 2log20)( V VVVVVdBTHD ++++×= where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.

16 V , 0 V to 20 V

daisy-chaining and readback. M is the slope for a given output range. 0 to 4095 for the 12-bit device. 0 to 65,535 for the 16-bit device. C is the offset for a given output range. The values for M and C are as shown in Table 7. Table 7. M and C Values for Various Output Ranges

0 V to 20 V 8 0

0 V to 10 V 4 0

0 V to 5 V 2 0

offer a 2.5 V , 5 ppm/°C maximum internal reference on chip. Figure 72. DAC Architecture

6 MSBs of the 16-bit data-word are decoded to drive 63 switches,

amplified afterwards to provide the selected output voltage.

63 EQUAL SEGMENTS

Figure 73. DAC Ladder Structure corresponds to the mode of operation. The internal reference is available at the VRFEFIN/VREFOUT pin. is then buffered before it is applied to the DAC core.

the output amplifier are shown in Figure 45. is loaded in at the SCLK falling edge transition (see Figure 2). The input shift register is updated on the rising edge of SYNC. can be updated by taking LDAC low while SYNC is high. register, the no operation (NOP) function clocks out the data. the next device in the chain, a multidevice interface is constructed. the total number of AD5761R/AD5721R devices in the chain. into the input shift register. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 74. Daisy-Chain Block Diagram

four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively. Table 8. AD5761R 16-Bit Input Shift Register Format Table 9. AD5721R 12-Bit Input Shift Register Format Table 10. Input Shift Register Commands

ground, and power up the output buffer. before writing to the control register. Table 11. Write to Control Register Table 12. Control Register Functions CV[1:0] CLEAR voltage selection. (greater than the maximum rating of the device). 0: internal digital supply does not power down if die temperature exceeds 150°C. 1: internal digital supply powers down if die temperature exceeds 150°C. RA[2:0] Output range. Before an output range configuration, the device must be reset.

Table 13. Bipolar Output Range Possible Codes outlines the 24-bit shift register for this command, where the last 16 bits are don’t care bits. the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 14. Readback Control Register, 24-Bit Shift Register to the SDI Pin Table 15. Readback Control Register, 24-Bit Data Read from the SDO Pin Table 16. Readback Control Register Bit Descriptions SC Short-circuit condition. The SC bit is reset at every control register write. BO Brownout condition. The BO bit is reset at every control register write.

The update DAC register function loads the DAC register with the data saved in the input register and updates the DAC output voltage. This operation is equivalent to a software LDAC. Table 17 outlines how data is written to the DAC register. Table 17. Update DAC Register from Input Register MSB shifted out first. Table 19 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 18. Readback DAC Register, 24-Bit Shift Register to SDI Pin Table 19. Readback DAC Register, 24-Bit Data Read from SDO Pin from the input shift register, irrespective of the state of LDAC. Setting the register address to 0001 writes the input register with the data from the input shift register, clocked in MSB first on the SDI pin. Table 20. Write and Update DAC Register

MSB shifted out first. Table 22 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 21. Readback Input Register, 24-Bit Shift Register to the SDI Pin Table 22. Readback Input Register, 24-Bit Data Read from the SDO Pin The daisy-chain feature can be disabled to save the power consumed by the SDO buffer when this functionality is not required (see Table 23). When disabled, a readback request is not accepted because the SDO pin remains in tristate. Table 23. Disable Daisy-Chain Functionality Register Table 24. Disable Daisy-Chain Bit Description 0: daisy-chain functionality is enabled for the device. 1: daisy-chain functionality is disabled for the device. reset is specified by the PV[1:0] bits, which are set in the write to control register command (see Table 11 and Table 12). Table 25. Software Data Reset Register

to configure the device, remove the 1 kΩ resistor clamp to ground, and power up the output buffer. The software full reset command is also issued when the DAC output range is reconfigured during normal operation. Table 26. Software Full Reset Register The no operation registers are ignored and do not vary the state of the device (see Table 27). Table 27. No Operation Registers

Figure 78. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 79. 16-Lead Lead Frame Chip Scale Package [LFCSP]

AD5761R/AD5721R Data Sheet Rev. C | Page 36 of 36 ORDERING GUIDE Model1, 2 Resolution (Bits) Internal Reference (V) Temperature Range INL (LSB) Package

Description

AD5721RBRUZ 12 2.5 −40°C to +125°C ±0.5 16-Lead TSSOP RU-16 AD5721RBRUZ-RL7 12 2.5 −40°C to +125°C ±0.5 16-Lead TSSOP RU-16 AD5721RBCPZ-RL7 12 2.5 −40°C to +125°C ±0.5 16-Lead LFCSP CP-16-22 DHN AD5761RARUZ 16 2.5 −40°C to +125°C ±8 16-Lead TSSOP RU-16 AD5761RARUZ-RL7 16 2.5 −40°C to +125°C ±8 16-Lead TSSOP RU-16 AD5761RBRUZ 16 2.5 −40°C to +125°C ±2 16-Lead TSSOP RU-16 AD5761RBRUZ-RL7 16 2.5 −40°C to +125°C ±2 16-Lead TSSOP RU-16 AD5761RACPZ-RL7 16 2.5 −40°C to +125°C ±8 16-Lead LFCSP CP-16-22 DJ5 AD5761RBCPZ-RL7 16 2.5 −40°C to +125°C ±2 16-Lead LFCSP CP-16-22 DJ6 EVAL-AD5761RSDZ Evaluation Board EVAL-SDP-CB1Z SDP Controller Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD5761RSDZ can be used to evaluate the AD5721R. ©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12355-0-1/18(C)