AD5710R AD | Alldatasheet
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8-channel 16-bit Configurable IDAC/VDAC with On-Chip Reference Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.
FEATURES
►Octal channel, configurable as any combination of VDAC or IDAC ►Guaranteed monotonicity : ±1 LSB16 Max DNL ►50mA output current drive for IDAC and VDAC modes ►70mV max headroom for VDAC mode ►0.25V max headroom for IDAC mode ►2.5V internal voltage reference, 3ppm/°C typical ►Device addressable SPI interface ►Output supply range: +1.71V to +5.5V ►Diagnostic monitoring for output voltage, output current, and die temperature ►Ultra small form factor: 2.1mm × 2.2mm, 25-ball WLCSP ►Operating temperature range: −40 °C to +125 °C
APPLICATIONS
►Optical networking ►Instrumentation ►Data acquisition ►Automatic test equipment ►Process control and industrial automation GENERAL DESCRIPTION The AD5710R features eight DAC channels that can be independ- ently configured as either a current output digital-to-analog convert- er (IDAC) or a voltage output digital-to-analog converter (VDAC). The AD5710R includes an integrated 2.5V, 3ppm/°C reference. When the AD5710R outputs are configured as an IDAC, the output current range is 0mA to 50mA. When configured as a VDAC, the output voltage range is 0V to VREF or 0V to 2 × VREF. The AD5710R is available in a 25-ball wafer level chip scale packaging (WLCSP) and is specified over the −40°C to +125°C temperature range. FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram
analog.com Rev. 0 | 2 of 56 Cyclic Redundancy Check (CRC) Error Layout Guidelines and Assembly Guidelines...34
REVISION HISTORY
10/2025—Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS
analog.com Rev. 0 | 3 of 56 DC SPECIFICATIONS VREF = 2.5V (internal or external), all specifications are at TJ = −40°C to +125°C. Typical specifications at TA = 25°C, unless otherwise noted. RL = 2kΩ, CL = 200pF for VDAC channels. RL = 50Ω for IDAC channels. No capacitor on VREF. Table 1. DC Specifications
analog.com Rev. 0 | 4 of 56 Table 1. DC Specifications (Continued)
analog.com Rev. 0 | 5 of 56 1 Linearity is defined from code 256 to code 65535 for VDAC and IDAC channels. 2 Offset error is measured at code 6503 for VDAC channels and code 255 for IDAC channels. to GND, CL = 200pF to GND for VDAC channels. RL = 50Ω to GND for IDAC channels. No capacitor on VREF. Table 2. AC Specifications
analog.com Rev. 0 | 6 of 56 Table 2. AC Specifications (Continued)
analog.com Rev. 0 | 7 of 56 CH4 to CH7 share PVDD1 and are adjacent only to each other. 3 Impact caused by a code change in an IDAC channel on the output of a VDAC channel. 4 The peak glitch seen on the VDAC channels when any channel is monitored through MUX_OUT_SELECT Register. Table 3. Digital Interface Timing Specifications 1 Equivalent to 50MHz for write operation only. 2 Equivalent to 25MHz for read operation only.
Table 5. Absolute Maximum Ratings 1 Configured as the reference input pin. ing conditions for extended periods may affect product reliability. maximum power dissipation exists. directly on the top surface of the package during system operation. Table 6. Thermal Resistance
1 Simulation values on JEDEC 2S2P board with 4 thermal vias, still air (0m/sec
devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.
Figure 5. WLCSP Pin Configuration Table 7. Pin Function Descriptions this pin provides a 2.5V reference output. By default, no decoupling capacitor is needed from this pin to GND for specified performance in internal reference mode. A2 OUT3 AO Analog Voltage Output from VDAC 3/Current Output of IDAC 3. A3 OUT2 AO Analog Voltage Output from VDAC 2/Current Output of IDAC 2. A4 OUT1 AO Analog Voltage Output from VDAC 1/Current Output of IDAC 1. B4 OUT0 AO Analog Voltage Output from VDAC 0/Current Output of IDAC 0. B1 AVDD S Power Supply Input. Bypass to GND with a 0.1μF capacitor. B2 PVDD0 S PVDD Supply Voltage Input for the IDAC/VDAC Channels (OUT0 to OUT3). D2 PVDD1 S PVDD Supply Voltage Input for the IDAC/VDAC Channels (OUT4 to OUT7). D5 CS DI Active Low Control Input. This is the frame synchronization signal for the input data. device. Bypass to GND with a 0.1μF capacitor. edge of SCLK and is valid on the rising edge of SCLK. B5 SCLK DI Serial Clock Input. Data transfers at rates of up to 50MHz for write operation and 25MHz for read operation. GND S Ground Reference Point for All Circuitry on the Device. D4 OUT4 AO Analog Voltage Output from VDAC 4/Current Output of IDAC 4. E4 OUT5 AO Analog Voltage Output from VDAC 5/Current Output of IDAC 5. E3 OUT6 AO Analog Voltage Output from VDAC 6/Current Output of IDAC 6. E2 OUT7 AO Analog Voltage Output from VDAC 7/Current Output of IDAC 7. C4 RESET DI Asynchronous Reset. Active low logic input, low level triggered. A5 LDAC DI Asynchronous Load DAC. Active low logic input, falling edge sensitive. C2 A0 DI Logic Input: Programmable Address Bit 0. C1 A1 DI Logic Input: Programmable Address Bit 1.
analog.com Rev. 0 | 19 of 56 Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a meas- urement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. Offset Error Offset error is a measure of the difference between the actual output VOUT or IOUT and the ideal output VOUT or IOUT expressed in mV or μA in the linear region of the transfer function. It can be negative or positive. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. For a IDAC output, the offset error drift is expressed in µA/°C and for VDAC output is expressed as µV/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Gain Error Drift Gain error drift is a measurement of the change in gain error with a change in temperature. The gain error drift is expressed in ppm/°C. Zero-Code Error Zero-code error measures the deviation from the ideal value at zero scale, at 25°C. The error is expressed in mV for the VOUT channel. DC PSRR and AC PSRR DC PSRR quantifies how variations in the power supply affect the DAC output. It is defined as the ratio of the change in output voltage (VOUT) or output current (IOUT) to the change in supply voltage, measured at the DAC’s midscale output. For VOUTX, DC PSRR is expressed in mV/V and for IOUTX it is expressed in μA/V, with PVDDx varied independently by ±10%. The AC PSRR is measured in dB by injecting a ±100mV peak-to-peak AC sweep signal onto PVDDx. Output Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a given step change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. For VDAC, the glitch is normally specified as the area in nV·s and is measured when the digital input code changes by 1 LSB. For IDAC, it is specified as the area in nA·s under the same condition. Output Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Noise is measured at the DAC output when it is loaded with the midscale code. For VDAC is measured in nV/Hz and for IDAC is measured in nA/Hz . Total Unadjusted Error (TUE) Total unadjusted error (TUE) is a measure of the total output error versus the ideal . The Ideal output is based on an exact 5.000V reference. TUE consists of all the various error sources, namely INL error, offset error, and gain error and it is guaranteed over the temperature and supply range. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as shown in the following equation: TC = V RE F _ M A X − V REF _ MI N V RE F _ N OM × TEMP _ RANGE × 10 6 (1) ►where: ►VREF_MAX is the maximum reference output measured over the total temperature range. ►VREF_MIN is the minimum reference output measured over the total temperature range. ►VREF_NOM is the nominal reference output voltage, 2.5V. ►TEMP_RANGE is the specified temperature range, −40°C to +125°C. DC Crosstalk DC crosstalk is the DC change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring anoth- er DAC kept at midscale. It is expressed in μV for VDAC and μA for IDAC. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. For the IDAC, digital feedthrough is specified as the peak output glitch current in μA, measured during a full-scale code change on the data bus, which means from all 0s to all 1s and from all 1s to all 0s. For the VDAC, digital feedthrough is specified as the peak output glitch voltage in μV.
analog.com Rev. 0 | 20 of 56 DIGITAL CROSSTALK Digital crosstalk is the energy of the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (from all 0s to all 1s and vice versa) in the input register of another DAC. For a current-output DAC, digital crosstalk is specified as the current peak current of the output glitch in μA. For a voltage-output DAC, it is specified as the peak voltage of the output glitch in μV. Both are measured on one DAC channel at a time. DAC-TO-DAC CROSSTALK DAC-to-DAC crosstalk refers to the energy of the glitch impulse that is transferred to the output of one DAC when a digital code change is loaded into the DAC register of another channel, resulting in a corresponding analog output change. For a current-output DAC, this crosstalk is measured as the peak of the current output glitch in μA. For a voltage-output DAC, it is measured as the peak of the voltage output glitch in μV. Both measurements are taken during a full-scale change on one DAC output, by writing directly to the DAC register while monitoring the other DAC output, which is held at midscale. ANALOG CROSSTALK Analog crosstalk refers to the glitch impulse transferred to the output of one DAC when a digital code change is loaded into the input register of another channel and its output is updated via an LDAC transition. It is measured by applying a full-scale code change (from all 0s to all 1s and vice versa) to the input register of the active channel, performing an LDAC update, and monitoring the output of the channel whose code remains unchanged. It is expressed as the peak current in μA for a current-output DAC and as the peak voltage in μV for a voltage-output DAC.
diagram of a DAC channel is shown in Figure 53. with classic SPI. See the Digital Interface section for more details. Figure 53. DAC Channel Block Diagram capable of sourcing currents up to 50mA.
2 N × 50 m A (2)
N is the DAC resolution in bits. Z mode and the output stage of each channel is powered down. corresponding to each channel. is not possible to set different output ranges on a per channel basis.
2 N × G (3)
VOUTn is the output voltage seen at the selected DAC channel n. N is the DAC resolution in bits. writing 2'b00 to MODE_CH_x bits corresponding to each channel. ured by writing 2'b00 to the MODE_CH_x bits. internal output resistance of approximately 15 kΩ to GND.
Table 8. AD5710R Operating Modes except during switching between DAC output modes. Figure 54. Recommended Switching Between Operating Modes and VDAC/ equal to AVDD during power-up. Table 9. Multiplexer Channels Options
0 Power down (default)
1 Voltage monitor, CH0
2 Current monitor through RSENSE, CH0
3 PVDD0 for CH0
4 Voltage monitor, CH1
5 Current monitor through RSENSE, CH1
6 PVDD0 for CH1
7 Voltage monitor, CH2
8 Current monitor through RSENSE, CH2
9 PVDD0 for CH2
10 Voltage monitor, CH3
11 Current monitor through RSENSE, CH3
12 PVDD0 for CH3
13 Voltage monitor, CH4
14 Current monitor through RSENSE, CH4
15 PVDD1 for CH4
16 Voltage monitor, CH5
17 Current monitor through RSENSE, CH5
18 PVDD1 for CH5
19 Voltage monitor, CH6
20 Current monitor through RSENSE, CH6
21 PVDD1 for CH6
22 Voltage monitor, CH7
23 Current monitor through RSENSE, CH7
24 PVDD1 for CH7
25 Die Temperature
Table 9. Multiplexer Channels Options (Continued)
26 AGND
channel are provided in Table 10. Table 10. Full Scale Output Voltages VMEAS is the measured voltage output of the selected channel. MUX_OUT is the voltage output on the MUX_OUT pin in volts. TROL_0, Bit 2 (range) value. MUX_OUT is the voltage at the MUX_OUT pin in volts. PVDDx is the supply voltage. current IOUTₓ can be calculated using Equation 6. TMEAS is the measured internal die temperature in °C. MUX_OUT is the voltage at the MUX_OUT pin in volts.
updated in parallel with the data held in the input registers. does not affect the data stored in the input register. be updated with the data written to the MULTI_INPUT_CH register. See the DAC Update section for additional information. more DAC registers to be updated in a single write operation. the DAC Update section for more information. Table 3. An error flag is asserted when a DAC update write is on the STATUS_CONTROL_0 register. any input registers without affecting the DAC output. for the corresponding DAC channel. SLD_TRIG_B bit on the SW_LDAC_TRIG_B register. the corresponding DAC channel.
correct CRC is required for the write to clear to take effect. at fault conditions for Address 0x0000. address being accessed in the SPI transaction as the seed value. Table 12. CRC Seed Values FIG_A register, which retains its current configuration.
pull-down resistance until proper register configurations are set. tolerance unless otherwise specified. Table 13. External Passive Components data output signal (MOSI), and a synchronization signal (SS). Figure 73. ADuCM320 SPI Interface reduce the soft error rate (SER). and the ambient temperature.
Table 14. Thermal Considerations for AD5710R WLCSP Package Using the preceding equation, calculate the AD5710R PDISS as follows, and confirm PDISS is lower than the allowed PDISS_MAX. RLOAD = 25Ω and PVDDx = 1.71V, per channel.
list of the user configuration registers. write transaction writes a 1 to their location. Table 15. AD5710R Register Summary
Table 15. AD5710R Register Summary (Continued)
Table 30. Bit Descriptions for INTERFACE_STATUS_A (Continued) valid when strict register access is enabled. Figure 89. Address: 0x20, Reset: 0xFF, Name: OUTPUT_OPERATING_MODE_0 Table 31. Bit Descriptions for OUTPUT_OPERATING_MODE_0 01: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 10: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 11: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 01: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 10: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 11: Channel Disabled: VMODE: 15kΩ output impedance; IMODE: high-Z. 01: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z. 10: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z. 11: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z. 01: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z. 10: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z. 11: Channel Disabled: : VMODE: 15kΩ output impedance; IMODE: high-Z.
Table 35. Bit Descriptions for MUX_OUT_SELECT (Continued) 0xB: Sense IOUT3 through a sense resistor. 0xE: Sense IOUT4 through a sense resistor. 0x11: Sense IOUT5 through a sense resistor. 0x14: Sense IOUT6 through a sense resistor. 0x17: Sense IOUT7 through a sense resistor. 0x19: Die temperature. Sense voltage to measure internal die temperature. 0x1A: MUX_OUT pin internally tied to AGND. Figure 94. Address: 0xC2, Reset: 0x04, Name: STATUS_CONTROL_0 Table 36. Bit Descriptions for STATUS_CONTROL_0 0: Error 0. All updates successful. 1: Error 1. Overlapping updates attempted. 0: Warning 0. Reset warning flag cleared. 1: Warning 1. Reset event occurred. 0: Error 0. No interface error. 1: Error 1. Interface error.
Figure 95. Address: 0xD0, Reset: 0xFF, Name: HW_LDAC_EN_0 Table 37. Bit Descriptions for HW_LDAC_EN_0 0: Disable hardware LDAC on Channel 7. 1: Enable hardware LDAC on Channel 7. 0: Disable hardware LDAC on Channel 6. 1: Enable hardware LDAC on Channel 6. 0: Disable hardware LDAC on Channel 5. 1: Enable hardware LDAC on Channel 5. 0: Disable hardware LDAC on Channel 4. 1: Enable hardware LDAC on Channel 4. 0: Disable hardware LDAC on Channel 3. 1: Enable hardware LDAC on Channel 3. 0: Disable hardware LDAC on Channel 2. 1: Enable hardware LDAC on Channel 2. 0: Disable hardware LDAC on Channel 1. 1: Enable hardware LDAC on Channel 1. 0: Disable hardware LDAC on Channel 0. 1: Enable hardware LDAC on Channel 0.
Figure 96. Address: 0xD1, Reset: 0xFF, Name: SW_LDAC_EN_0 Table 38. Bit Descriptions for SW_LDAC_EN_0 0: Disable software LDAC on Channel 7. 1: Enable software LDAC on Channel 7. 0: Disable software LDAC on Channel 6. 1: Enable software LDAC on Channel 6. 0: Disable software LDAC on Channel 5. 1: Enable software LDAC on Channel 5. 0: Disable software LDAC on Channel 4. 1: Enable software LDAC on Channel 4. 0: Disable software LDAC on Channel 3. 1: Enable software LDAC on Channel 3. 0: Disable software LDAC on Channel 2. 1: Enable software LDAC on Channel 2. 0: Disable software LDAC on Channel 1. 1: Enable software LDAC on Channel 1. 0: Disable software LDAC on Channel 0. 1: Enable software LDAC on Channel 0.
Table 41. Bit Descriptions for MULTI_DAC_SEL_0 (Continued) the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH6. 0: MD Sel 0. Deselect DAC_CH6 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH6 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH5. 0: MD Sel 0. Deselect DAC_CH5 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH5 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH4. 0: MD Sel 0. Deselect DAC_CH4 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH4 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH3. 0: MD Sel 0. Deselect DAC_CH3 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH3 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH2. 0: MD Sel 0. Deselect DAC_CH2 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH2 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH1. 0: MD Sel 0. Deselect DAC_CH1 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH1 for MULTI_DAC_CH operation. the same data. If deselected, write operation on MULTI_DAC_CH does not affect DAC_CH0. 0: MD Sel 0. Deselect DAC_CH0 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH0 for MULTI_DAC_CH operation. Figure 100. Address: 0xE5, Reset: 0x00, Name: SW_LDAC_TRIG_A Table 42. Bit Descriptions for SW_LDAC_TRIG_A number as enabled by SW_LDAC_EN_0. Writing 0 does not have any effect.
Table 44. Bit Descriptions for MULTI_INPUT_SEL_0 (Continued) with the same data. If deselected, write operation on MULTI_DAC_CH does not affect INPUT_CH3. 0: MI Sel 0. Deselect INPUT_CH3 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH3 for MULTI_INPUT_CH operation. with the same data. If deselected, write operation on MULTI_DAC_CH does not affect INPUT_CH2. 0: MI Sel 0. Deselect INPUT_CH2 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH2 for MULTI_INPUT_CH operation. with the same data. If deselected, write operation on MULTI_DAC_CH does not affect INPUT_CH1. 0: MI Sel 0. Deselect INPUT_CH1 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH1 for MULTI_INPUT_CH operation. not affect MULTI_INPUT_SEL_CH0. 0: MI Sel 0. Deselect MULTI_INPUT_SEL_CH0 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select MULTI_INPUT_SEL_CH0 for MULTI_INPUT_CH operation. Figure 103. Address: 0xE9, Reset: 0x00, Name: SW_LDAC_TRIG_B Table 45. Bit Descriptions for SW_LDAC_TRIG_B number as enabled by SW_LDAC_EN_0. Writing 0 has no effect.
Figure 104. Address: 0xEA to 0xF8 (Increments of 2), Reset: 0x0000, Name: INPUT_CHn Table 46. Bit Descriptions for INPUT_CHn Figure 105. Address: 0xFF, Reset: 0x00, Name: CHN_VMODE_EN Table 47. Bit Descriptions for CHN_VMODE_EN
5 VMODE_EN_CH5 VMODE enable register 0x0 R/W
0 VMODE_EN_CH0 VMODE enable register 0x0 R/W
Table 47. Bit Descriptions for CHN_VMODE_EN (Continued)
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1.60 REF
Figure 106. 25-Ball Wafer Level Chip Scale Package [WLCSP] Dimensions shown in millimeters.