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Data Sheet AD5700/AD5700-1 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode Suitable for intrinsically safe applications Integrated receive band-pass filter Minimal external components required Clocking optimized for various system configurations Ultralow power crystal oscillator (60 µA maximum) External CMOS clock source Precision internal oscillator (AD5700-1 only) Buffered HART output—extra drive capability 8 kV HBM ESD rating 1.71 V to 5.5 V power supply 1.71 V to 5.5 V interface −40°C to +125°C operation 4 mm × 4 mm LFCSP package HART physical layer compliant UART interface
APPLICATIONS
PLC and DCS analog I/O modules HART network connectivity GENERAL DESCRIPTION The AD5700/AD5700-1 are single-chip solutions, designed and specified to operate as a HART® FSK half-duplex modem, complying with the HART physical layer requirements. The AD5700/AD5700-1 integrate all of the necessary filtering, signal detection, modulating, demodulating and signal generation functions, thus requiring few external components. The 0.5% precision internal oscillator on the AD5700-1 greatly reduces the board space requirements, making it ideal for line-powered applications in both master and slave configurations. The maxi- mum supply current consumption is 115 µA, making the AD5700/ AD5700-1 an optimal choice for low power loop-powered applica- tions. Transmit waveforms are phase continuous 1200 Hz and 2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate carrier detect circuitry and use a standard UART interface. Table 1. Related Products
AD5700/AD5700-1 Data Sheet Rev. D | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
5/13—Rev. C to Rev. D 2/13—Rev. B to Rev. C Changed 2 V to 5.5 V Power Supply to 1.71 V to 5.5 V Power Changes to Summary Statement, VCC Parameter, and Internal Reference Voltage Parameter Test Conditions/Comments, Changed VCC = 2 V to 5.5 V to VCC = 1.71 V to 5.5 V in the Changes to Pin 18 Description and EPAD Mnemonic and 7/12—Rev. A to Rev. B Removed VCC and IOVCC Current Consumption Text, Table 2 .. 3 Added Internal Oscillator and External Clock Parameters Added Transient Voltage Protection Section, Figure 26, and 4/12—Rev. 0 to Rev. A Change to Transmit Impedance Parameter, RTS Low, Table 2 ... 4 2/12—Revision 0: Initial Version
Data Sheet AD5700/AD5700-1 Rev. D | Page 3 of 24 SPECIFICATIONS VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external receive filter, internal reference; all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS2 VCC 1.71 5.5 V IOVCC 1.71 5.5 V VCC and IOVCC Current Consumption Demodulator 86 115 µA B model, external clock, −40°C to +85°C 179 µA B model, external clock, −40°C to +125°C 69 97 µA B model, external clock, −40°C to +85°C, external reference 157 µA B model, external clock, −40°C to +125 °C, external reference 260 µA A model, external clock, −40°C to +125°C Modulator 124 140 µA B model, external clock, −40°C to +85°C 193 µA B model, external clock, −40°C to +125°C 73 96 µA B model, external clock, −40°C to +85°C, external reference 153 µA B model, external clock, −40°C to +125°C, external reference 270 µA A model, external clock, −40°C to +125°C Crystal Oscillator3 33 60 µA External crystal, 16 pF at XTAL1 and XTAL2 44 71 µA External crystal, 36 pF at XTAL1 and XTAL2 Internal Oscillator4 218 285 µA AD5700-1 only, external crystal not required Power-Down Mode RESET = REF_EN = DGND 16 35 µA Internal reference disabled, −40°C to +85°C 75 µA Internal reference disabled, −40°C to +125°C INTERNAL VOLTAGE REFERENCE Internal Reference Voltage 1.47 1.5 1.52 V REF_EN = IOVCC to enable use of internal reference; VCC = 1.71 V minimum Load Regulation 18 ppm/µA Tested with 50 µA load OPTIONAL EXTERNAL VOLTAGE REFERENCE External Reference Input Voltage 2.47 2.5 2.53 V REF_EN = DGND to enable use of external reference, VCC = 2.7 V minimum External Reference Input Current Demodulator 16 21 µA Current required by external reference in receive mode Modulator 28 33 µA Current required by external reference in transmit mode Internal Oscillator 5.5 7 µA Current required by external reference if using internal oscillator Power-Down 4.6 8.6 µA DIGITAL INPUTS VIH, Input High Voltage 0.7 × IOVCC V VIL, Input Low Voltage 0.3 × IOVCC V Input Current −0.1 +0.1 µA Input Capacitance5 5 pF Per pin
AD5700/AD5700-1 Data Sheet Rev. D | Page 4 of 24 Parameter1 Min Typ Max Unit Test Conditions/Comments DIGITAL OUTPUTS VOH, Output High Voltage IOVCC − 0.5 V VOL, Output Low Voltage 0.4 V CD Assert6 85 100 110 mV p-p HART_IN INPUT5 Input Voltage Range 0 REF V External reference source 0 1.5 V Internal reference enabled HART_OUT OUTPUT Output Voltage 459 493 505 mV p-p AC-coupled (2.2 µF), measured at HART_OUT pin with 160 Ω load (worst-case load), see Figure 15 and Figure 16 for HART_OUT voltage vs. load Mark Frequency7 1200 Hz Internal oscillator Space Frequency7 2200 Hz Internal oscillator Frequency Error −0.5 +0.5 % Internal oscillator, −40°C to +85°C −1 +1 % Internal oscillator, −40°C to +125°C Phase Continuity Error5 0 Degrees Maximum Load Current5 160 Ω Worst-case load is 160 Ω, ac-coupled with 2.2 µF, see Figure 19 for recommended configuration if driving a resistive load Transmit Impedance 7 Ω RTS low, at the HART_OUT pin 70 kΩ RTS high, at the HART_OUT pin INTERNAL OSCILLATOR Frequency 1.2226 1.2288 1.2349 MHz −40°C to +85°C 1.2165 1.2288 1.2411 MHz −40°C to +125°C EXTERNAL CLOCK External Clock Source Frequency 3.6496 3.6864 3.7232 MHz 1 Temperature range: −40°C to +125°C; typical at 25°C. 2 Current consumption specifications are based on mean current values. 3 The demodulator and modulator currents are specified using an external clock. If using an external crystal oscillator, the crystal oscillator current specification must be added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode. 4 The demodulator and modulator currents are specified using an external clock. If using the internal oscillator, the internal oscillator current specification must be added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode. 5 Guaranteed by design and characterization, but not production tested. 6 Specification set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 21). 7 If the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.
Data Sheet AD5700/AD5700-1 Rev. D | Page 5 of 24 TIMING CHARACTERISTICS Table 3. Parameter1 Limit at TMIN, TMAX Unit Description t1 1 Bit time2 max Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See Figure 3. t2 1 Bit time2 max Carrier stop time. Time from RTS rising edge to carrier amplitude dropping below the minimum receive amplitude. t3 1 Bit time2 max Carrier decay time. Time from RTS rising edge to carrier amplitude dropping to ac zero. See Figure 4. t4 6 Bit times2 max Carrier detect on. Time from carrier on to CD rising edge. See Figure 5. t5 6 Bit times2 max Carrier detect off. Time from carrier off to CD falling edge. See Figure 6. t6 10 Bit times2 max Carrier detect on when switching from transmit mode to receive mode in the presence of a constant valid carrier. Time from RTS rising edge to CD rising edge. See Figure 7. t7 2.1 ms typ Crystal oscillator power-up time. On application of a valid power supply voltage at VCC or on enabling of the oscillator via the XTAL_EN pin. Crystal load capacitors = 8 pF. t8 6 ms typ Crystal oscillator power-up time. Crystal load capacitors = 18 pF. t9 25 µs typ Internal oscillator power-up time. On application of a valid power supply voltage at VCC or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins. t10 10 ms typ Reference power-up time. t11 30 µs typ Transition time from power-down mode to normal operating mode (external clock source, external reference). 1 Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter. 2 Bit time is the length of time to transfer one bit of data (1 bit time = 1/1200 Hz = 833.333 µs).
TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Figure 2. Pin Configuration Table 6. Pin Function Descriptions pins in configuring the required clock generation scheme. 3 CLK_CFG0 Clock Configuration Control. See Table 7. 4 CLK_CFG1 Clock Configuration Control. See Table 7. RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC. 6 CD Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected. 7 TXD Transmit Data—Digital Input. Data input to the modulator. enables the modulator and disables the demodulator. 10 RXD Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin. 0.1 μF capacitors (see the Supply Decoupling section). 13 REG_CAP Capacitor Connection for Internal Voltage Regula tor. Connect a 1 μF capacitor from this pin to ground. 14 HART_OUT HART FSK Signal Output. See the FSK Modula tor section and Figure 28 for typical connections. pin to ground. When supplying an external reference, the VCC supply requires a minimum voltage of 2.7 V. capacitor. If using an external band-pass filter as shown in Figure 21, do not connect to this pin. the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 21. 10 μF and 0.1 μF capacitors (see the Supply Decoupling section).
- THE EXPOSED PADDLE SHOULD BE CONNECTED
AD5700/AD5700-1 Data Sheet Rev. D | Page 8 of 24 Pin No. Mnemonic Description 19 AGND Analog Circuitry Ground Reference Connection. 20 XTAL2 Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator (AD5700-1 only) or an external clock source. 21 XTAL1 Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the internal RC oscillator (AD5700-1 only). 22 DGND Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to AGND. 23 REF_EN Reference Enable. A high state enables the internal 1.5 V reference and buffer. A low state disables the internal reference and input buffer, and a buffered external 2.5 V reference source must be applied at REF. If REF_EN is tied low, VCC must be greater than 2.7 V. 24 FILTER_SEL Band-Pass Filter Select. A high state enables the internal filter and the HART signal should be applied to the HART_IN pin. A low state disables the internal filter and an external band-pass filter must then be connected at the ADC_IP input pin. In this case, the HART signal should be applied to the ADC_IP pin. EPAD EPAD Exposed Pad. For typical operation, it is recommended to connect this pin to AGND.
AD5700/AD5700-1 Data Sheet Rev. D | Page 12 of 24 TERMINOLOGY VCC and IOVCC Current Consumption This specification gives a summation of the current consump- tion of both the VCC and the IOVCC supplies. Figure 11 shows separate measurements for VCC and IOVCC currents vs. varying capacitive loads, in transmit mode. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/µA. CD Assert The minimum value at which the carrier detect signal asserts is 85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD is already high (asserted) for HART input signals greater than 110 mV p-p. This specification was set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 21). HART_OUT Output Voltage This is the peak-to-peak HART_OUT output voltage. The specification in Table 2 was set using a worst-case load of 160 Ω, ac-coupled with a 2.2 µF capacitor. Figure 15 and Figure 16 show HART_OUT output voltages for both resistive and purely capacitive loads. Mark/Space Frequency A 1.2 kHz signal represents a digital 1, or mark, whereas a 2.2 kHz signal represents a 0, or space. Phase Continuity Error The DDS engine in this design inherently generates continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. This attribute is desirable for signals that are to be transmitted over a band limited channel, because discontinuities in a signal introduce wideband fre- quency components. As the name suggests, for a signal to be continuous, the phase continuity error must be 0o.
Table 7. Clock Configuration Options 125oC maximum temperature case. and 425 µA for transmit current. approximately 1.7 V until RESET is brought high again. switched off, and the device consumes a typical current of 16 µA. connecting the DUPLEX pin to logic high.
Figure 29. Loop-Powered Transmitter Diagram
Figure 30. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit
Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-8.
0.20 REF
0.25 MIN
0.05 MAX
0.02 NOM
AD5700/AD5700-1 Data Sheet Rev. D | Page 22 of 24 NOTES
Data Sheet AD5700/AD5700-1 Rev. D | Page 23 of 24 NOTES
AD5700/AD5700-1 Data Sheet Rev. D | Page 24 of 24 NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10435-0-5/13(D)