AD5623R_15 AD | Alldatasheet
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Dual 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference Data Sheet AD5623R/AD5643R/AD5663R Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface up to 50 MHz Hardware LDAC and CLR functions
APPLICATIONS
Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM INTERFACE LOGIC SCLK SYNC DIN CLR INPUT REGISTER INPUT REGISTER DAC REGISTER DAC REGISTER VDD GND POWER-ON RESET STRING DAC A STRING DAC B BUFFER BUFFER VREFIN /VREFOUT POWER-DOWN LOGIC VOUT A VOUT B AD5623R/AD5643R/AD5663R LDAC LDAC 05858-001 1.25V/2.5V REFERENCE Figure 1. Table 1. Related Devices 2.7 V to 5.5 V supply and are guaranteed monotonic by design. AD5623R/AD5643R/AD5663R have an on-chip reference. makes it ideally suited to portable, battery-operated equipment. enables rail-to-rail output swing to be achieved.
- On-chip 1.25 V/2.5 V , 5 ppm/°C reference.
- Available in 10-lead MSOP and 10-lead, 3 mm ×
- Low power; typically consumes 0.6 mW at 3 V and
- 4.5 μs maximum settling time for the
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 2 of 32 TABLE OF CONTENTS SYNC Using the AD5663R with a Galvanically Isolated Interface .. 27
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 3 of 32
REVISION HISTORY
9/15— Rev. F to Rev. G Changes to AD5623R/AD5643R/AD5663R to Blackfin® 2/13— Rev. E to Rev. F 4/12— Rev. D to Rev. E 4/11— Rev. C to Rev. D 6/10— Rev. B to Rev. C 4/10— Rev. A to Rev. B 12/06— Rev. 0 to Rev. A 4/06— Revision 0: Initial Version
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 4 of 32 SPECIFICATIONS AD5623R-5/AD5643R-5/AD5663R-5 VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5663R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy ±1 ±2 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.1 ±1 −0.1 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 ±1.5 % of FSR Zero-Scale Error Drift ±2 ±2 µV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale ; VDD = 5 V ± 10% DC Crosstalk (External Reference) 10 10 µV Due to full-scale output change; RL = 2 kΩ to GND or VDD 10 10 µV/mA Due to load current change 5 5 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 25 µV Due to full-scale output change; RL = 2 kΩ to GND or VDD 20 20 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V DD 0 V DD V Capacitive Load Stability 2 2 nF R L = ∞ 10 10 nF R L = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V DD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode; VDD = 5 V REFERENCE INPUTS Reference Current 170 200 170 200 µA V REF = VDD = 5.5 V Reference Input Range 0.75 VDD 0.75 VDD V Reference Input Impedance 26 26 kΩ
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 5 of 32 A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments REFERENCE OUTPUT Output Voltage 2.495 2.505 2.495 2.505 V At ambient Reference Temperature Coefficient3 ±10 ±5 ±10 ppm/°C MSOP package models ±10 ±10 ppm/°C LFCSP package models Output Impedance 7.5 7.5 kΩ LOGIC INPUTS3 Input Current ±2 ±2 µA All digital inputs Input Low Voltage (VINL) 0.8 0.8 V V DD = 5 V Input High Voltage (VINH) 2 2 V V DD = 5 V Pin Capacitance 3 3 pF DIN, SCLK, and SYNC 19 19 pF LDAC and CLR POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V IDD (Normal Mode)4 V IH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 0.8 1 0.8 1 mA Internal reference on IDD (All Power-Down Modes)5 VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA V IH = VDD and VIL = GND 1 Temperature range: A, B grade = −40°C to +105°C.
2 Linearity calculated using a reduced code range:
AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down.
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 6 of 32 AD5623R-3/AD5643R-3/AD5663R-3 VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. B Grade1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5663R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 % of FSR Zero-Scale Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 3 V ± 10% DC Crosstalk (External Reference) 10 µV Due to full-scale output change; RL = 2 kΩ to GND or VDD 10 µV/mA Due to load current change 5 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change; RL = 2 kΩ to GND or VDD 20 µV/mA Due to load current change 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V DD V Capacitive Load Stability 2 nF R L = ∞ 10 nF R L = 2 kΩ DC Output Impedance 0.5 Ω Short Circuit Current 30 mA V DD = 3 V Power-Up Time 4 µ s Coming out of power-down mode; VDD = 3 V REFERENCE INPUTS Reference Current 170 200 µA V REF = VDD = 3.6 V Reference Input Range 0.75 VDD V Reference Input Impedance 26 kΩ REFERENCE OUTPUT Output Voltage 1.247 1.253 V At ambient Reference Temperature Coefficient3 ±5 ±15 ppm/°C MSOP package models ±10 ppm/°C LFCSP package models Output Impedance 7.5 kΩ
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 7 of 32 B Grade1 Parameter Min Typ Max Unit Conditions/Comments LOGIC INPUTS3 Input Current ±2 µA All digital inputs VINL, Input Low Voltage 0.8 V V DD = 3 V VINH, Input High Voltage 2 V V DD = 3 V Pin Capacitance 3 pF DIN, SCLK, and SYNC 19 pF LDAC and CLR POWER REQUIREMENTS VDD 2.7 3.6 V IDD (Normal Mode)4 V IH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 200 425 µA Internal reference off VDD = 2.7 V to 3.6 V 800 900 µA Internal reference on IDD (All Power-Down Modes)5 VDD = 2.7 V to 3.6 V 0.2 1 µA V IH = VDD and VIL = GND 1 Temperature range: B grade = −40°C to +105°C. AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1, 2 Min Typ Max Unit Conditions/Comments3 Output Voltage Settling Time AD5623R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5643R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5663R 4 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 10 nV-sec 1 LSB change around major carry Digital Feedthrough 0.1 nV-sec Reference Feedthrough −90 dB V REF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz Digital Crosstalk 0.1 nV-sec Analog Crosstalk 1 nV-sec External reference 4 nV-sec Internal reference DAC-to-DAC Crosstalk 1 nV-sec External reference 4 nV-sec Internal reference Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p Total Harmonic Distortion −80 dB V REF = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 μ V p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range: A, B grade = −40°C to +105°C, typical at +25°C.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 9 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter Rating VDD to GND −0.3 V to +7 V VOUT to GND −0.3 V to VDD + 0.3 V VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 61°C/W θJA Thermal Impedance 142°C/W θJC Thermal Impedance 43.7°C/W Reflow Soldering Peak Temperature Pb-Free 260(+0/−5)°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
- EXPOSED PAD TIED TO GND ON
Figure 3. Pin Configuration Table 7. Pin Function Descriptions 1 V OUTA Analog Output Voltage from DAC A. The outp ut amplifier has rail-to-rail operation. 2 V OUTB Analog Output Voltage from DAC B. The outp ut amplifier has rail-to-rail operation. 3 GND Ground. Reference point for all circuitry on the part. 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. a write sequence, the write is aborted. 6 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 19 of 32 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9. Zero-Scale Error Zero-scale error is the measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V . The zero-scale error is always positive in the AD5623R/AD5643R/AD5663R because the output of the DAC cannot go below 0 V . It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-scale error is expressed in mV . A plot of zero-scale error vs. temperature is shown in Figure 26. Full-Scale Error Full-scale error is the measurement of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature is shown in Figure 25. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range. Zero-Scale Error Drift Zero-scale error drift is the measurement of the change in zero- scale error with a change in temperature. It is expressed in microvolts/°C (μV/°C). Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5623R/ AD5643R/AD5663R with code 512 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V , and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse The impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 38. Digital Feedthrough A measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, digital feedthrough is measured when the DAC output is not updated. It is specified in nV-sec, and it is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels (dB). Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. A plot of noise spectral density is shown in Figure 44. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts (μV). DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in microvolts/ milliamps (μV/mA).
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 20 of 32 Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolts-second (nV-sec). Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nanovolts-second (nV-sec). DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolts-second (nV-sec). Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in decibels (dB).
CLR during power-on reset are ignored. software reset mode of operation. Table 10. Software Reset Modes
0 DAC register
high, that SPI transaction is ignored. corresponding two bits (Bit DB1 and Bit DB0) to 1. to the value held in the DAC register before power-down. Table 11. Modes of Operation normally, with its normal power consumption of 250 µA at 5 V . the output of the amplifier to a resistor network of known values. resistor or left open-circuited (three-state) (see Figure 55). Figure 55. Output Stage During Power-Down Table 12. 24-Bit Input Shift Register Contents for Software Reset Command
Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function Table 14. 24-Bit Input Shift Register Contents for LDAC Setup Command relevant input register on completion of a valid write sequence. outputs will update simultaneously. thereby removing unnecessary digital crosstalk. low or pulsed as shown in Figure 2. registers are updated with the contents of the input register. pin. It effectively sees the LDAC pin as being pulled low. channels are synchronously updating. the LDAC register setup command. Table 15. LDAC Register Mode of Operation
1 X = don’t care The DAC registers are updated
how the state of the bit corresponds to the mode of operation. register during the internal reference setup command. Table 16. Reference Setup Register
0 Reference off (default)
1 Reference on
Table 17. 32-Bit Input Shift Register Contents for Reference Setup Function
Figure 60. REF195 as Power Supply to the AD5623R/AD5643R/AD5663R Figure 61. The circuit gives an output voltage range of ±5 V . AD820 or an OP295 as the output amplifier. where D represents the input code in decimal (0 to 65,535). Figure 61. Bipolar Operation with the AD5663R
5 V supply required for the
Figure 62. AD5663R with a Galvanically Isolated Interface
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 28 of 32 POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5663R should have separate analog and digital sections, each having its own area of the board. If the AD5663R is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5663R. The power supply to the AD5663R should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), which is found, for example, in common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
2.90 PIN 1
0.20 MIN
Figure 63. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
1.10 MAX
Figure 64. 10-Lead Mini Small Outline Package [MSOP]
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 30 of 32 ORDERING GUIDE Model1 Temperature Range Accuracy Internal Reference Package Description Package Option Branding AD5623RBCPZ-3R2 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85 AD5623RBCPZ-3REEL7 − 40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85 AD5623RBCPZ-5REEL7 − 40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 D86 AD5623RBRMZ-3 − 40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85 AD5623RBRMZ-3REEL7 − 40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85 AD5623RBRMZ-5 − 40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86 AD5623RBRMZ-5REEL7 − 40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86 AD5623RACPZ-5REEL7 − 40°C to +105°C ±2 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DKB AD5623RARMZ-5REEL7 − 40°C to +105°C ±2 LSB INL 2.5V 10-Lead MSOP RM-10 DKP AD5623RARMZ-5 −40°C to +105°C ±2 LSB INL 2.5V 10-Lead MSOP RM-10 DKP AD5643RBRMZ-3 − 40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81 AD5643RBRMZ-3REEL7 − 40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81 AD5643RBRMZ-5 − 40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q AD5643RBRMZ-5REEL7 − 40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q AD5663RBCPZ-3R2 − 40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S AD5663RBCPZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S AD5663RBCPZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 D7H AD5663RBRMZ-3 − 40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S AD5663RBRMZ-3REEL7 − 40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S AD5663RBRMZ-5 − 40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H AD5663RBRMZ-5REEL7 − 40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H EVAL-AD5663REBZ Evaluation Board 1 Z = RoHS Compliant Part.
Data Sheet AD5623R/AD5643R/AD5663R Rev. G | Page 31 of 32 NOTES
AD5623R/AD5643R/AD5663R Data Sheet Rev. G | Page 32 of 32 NOTES ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05858-0-9/15(G)