AD5602/AD5612/AD5622 (Rev.F)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 24
Technical content
2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit nanoDACs with I2C Compatible Interface in LFCSP and SC70 Rev. F DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Single 8-, 10-, 12-bit DACs, 2 LSB INL ►6-lead LFCSP and SC70 packages ►Micropower operation: 100 µA maximum at 5 V ►Power down to <150 nA at 3 V ►2.7 V to 5.5 V power supply ►Guaranteed monotonic by design ►Power-on reset to 0 V with brownout detection ►3 power-down functions ►I2C compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes ►On-chip output buffer amplifier, rail-to-rail operation ►AEC-Q100 qualified for automotive applications
APPLICATIONS
►Process control ►Data acquisition systems ►Portable battery-powered instruments ►Digital gain and offset adjustment ►Programmable voltage and current sources ►Programmable attenuators FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD5602/AD5612/AD5622, members of the nanoDAC® family, are single 8-, 10-, 12-bit buffered voltage-out digital-to-analog con- verters (DAC) that operate from a single 2.7 V to 5.5 V supply, consuming <100 µA at 5 V. These DACs come in tiny LFCSP and SC70 packages. Each DAC contains an on-chip precision output amplifier that allows rail-to-rail output swing to be achieved. The AD5602/AD5612/AD5622 use a 2-wire I2C compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. The references for AD5602/AD5612/AD5622 derive from the power supply inputs to give the widest dynamic output range. Each device incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The devices contain a power-down feature that reduces the current consumption of the devices to <150 nA at 3 V and pro- vides software selectable output loads while in power-down mode. The devices are put into power-down mode over the serial inter- face. The low power consumption of the AD5602/AD5612/AD5622 in normal operation makes them ideally suited for use in portable, battery operated equipment. The typical power consumption is 0.4 mW at 5 V. Table 1. Related Devices
- Available in 6-lead LFCSP and SC70 packages.
- Maximum 100 µA power consumption, single-supply operation.
them ideal for battery-powered applications.
- The on-chip output buffer amplifier allows the output of the DAC
to swing rail-to-rail with a typical slew rate of 0.5 V/µs.
- Reference derived from the power supply.
- Standard, fast, and high speed mode I2C interface.
- Designed for very low power consumption.
- Power-down capability. When powered down, the DAC typically
- Power-on reset and brownout detection.
Data Sheet AD5602/AD5612/AD5622 TABLE OF CONTENTS analog.com Rev. F | 2 of 24 INL, I2C Interface Modes Supported, and
REVISION HISTORY
10/2024—Rev. E to Rev. F
Data Sheet AD5602/AD5612/AD5622 SPECIFICATIONS analog.com Rev. F | 3 of 24 VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter A, B, W, Y Versions1 Unit Test Conditions/CommentsMin Typ Max STATIC PERFORMANCE DAC output unloaded Resolution Bits AD5602 8 AD5612 10 AD5622 12 Relative Accuracy2 AD5602 ±0.5 LSB B, Y versions AD5612 ±0.5 LSB B, Y versions ±4 LSB A version AD5622 ±2 LSB B, Y versions ±6 LSB A, W versions Differential Nonlinearity2 ±1 LSB Guaranteed monotonic by design Zero Code Error 0.5 10 mV All 0s loaded to DAC register Offset Error ±0.063 ±10 mV Full-Scale Error 0.5 mV All 1s loaded to DAC register Gain Error ±0.0004 ±0.037 % of FSR Zero Code Error Drift 5 µV/°C Gain Temperature Coefficient 2 ppm of FSR/°C OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VDD V Output Voltage Settling Time 6 10 µs Code ¼ to ¾ Slew Rate 0.5 V/µs Capacitive Load Stability 470 pF RL = ∞ 1000 pF RL = 2 kΩ Output Noise Spectral Density 120 nV/Hz DAC code = midscale, 10 kHz Noise 2 DAC code = midscale, 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.2 nV-sec DC Output Impedance 0.5 Ω Short Circuit Current 15 mA VDD = 3 V/5 V LOGIC INPUTS (SDA, SCL) IIN, Input Current ±1 µA VINL, Input Low Voltage 0.3 × VDD V VINH, Input High Voltage 0.7 × VDD V CIN, Pin Capacitance 2 pF VHYST, Input Hysteresis 0.1 × VDD V LOGIC OUTPUTS (OPEN DRAIN) VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating State Leakage Current ±1 µA Floating State Output Capacitance 2 pF POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) DAC active and excluding load current VDD = 4.5 V to 5.5 V 75 100 µA VIH = VDD and VIL = GND
Table 2. (Continued) 1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C. 2 Linearity calculated using a reduced code range 64 to 4032. 3 Guaranteed by design and characterization, not production tested.
Table 3. (Continued) 1 CB refers to the capacitance on the bus line. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. Figure 2. 2-Wire Serial Interface Timing Diagram
Data Sheet AD5602/AD5612/AD5622 ABSOLUTE MAXIMUM RATINGS analog.com Rev. F | 6 of 24 TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to GND –0.3 V to + 7.0 V Digital Input Voltage to GND –0.3 V to VDD + 0.3 V VOUT to GND –0.3 V to VDD + 0.3 V Operating Temperature Range −40°C to +125°C Storage Temperature Range –65°C to +160°C Maximum Junction Temperature 150°C θJA Thermal Impedance 332°C/W θJC Thermal Impedance 120°C/W θJA Thermal Impedance 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 2.0 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devi- ces and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Data Sheet AD5602/AD5612/AD5622 TERMINOLOGY analog.com Rev. F | 14 of 24 Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in least significant bits (LSB), from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum en- sures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 6. Zero Code Error Zero code error is due to a combination of the offset errors in the DAC and output amplifier; it is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 V. The zero code error is always positive in the AD5602/AD5612/AD5622 because the output of the DAC cannot go below 0 V. Zero code error is expressed in mV. A plot of zero code error vs. temperature can be seen in Figure 18. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register; it is expressed in percent of full-scale range. Ideally, the output is VDD – 1 LSB. A plot of full-scale error vs. temperature can be seen in Figure 18. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 11. Zero Code Error Drift Zero code error drift is a measure of the change in zero code error with a change in temperature. It is expressed in µV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 33). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa (see Figure 34).
issued, the devices return to standard/fast mode. Figure 49. Placing the AD5602/AD5612/AD5622 into High Speed Mode
choice of reference dependent upon the application requirement. noise performance at 3.4 µV p-p in the 0.1 Hz to 10 Hz range. drive multiple DACs in the one system, if required. Figure 50. ADR425 as Power Supply supplies to the AD5602/AD5612/AD5622 are shown in Table 9. Table 9. Recommended Precision References
0.1 Hz to 10 Hz Noise (µV
using an AD820 or an OP295 as the output amplifier. D represents the input code in decimal. n represents the bit resolution of the DAC. a −5 V output, and 0xFFF corresponding to a +5 V output. Figure 51. Bipolar Operation with the AD5602/AD5612/AD5622 consider the power supply and ground return layout on the board. close as possible to the AD5602/AD5612/AD5622. currents due to internal logic switching. a low impedance path and reduce glitch effects on the supply line. microstrip technique is not always possible with a 2-layer board.
1.30 BSC
0.10 MAX
0.65 BSC
Figure 52. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
0.00 MIN
0.65 REF
0.20 MIN
Figure 53. 6-Lead Lead Frame Chip Scale Package [LFCSP]
Table 10. (Continued) 2 W = Qualified for Automotive Applications; does not apply to the AD5622WKSZ-1500RL7 model.
Data Sheet AD5602/AD5612/AD5622 OUTLINE DIMENSIONS ©2005-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. F | 24 of 24 2 W = Qualified for Automotive Applications; does not apply to the AD5622WKSZ-1500RL7 model. AUTOMOTIVE PRODUCTS The AD5612WAKSZ-2REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).