AD5600

AD5600 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 14

Technical content

High Temperature, 16-Bit, Unbuffered Voltage Output DAC, SPI Interface Data Sheet AD5600 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

High temperature operation: −55°C to +175°C 16-bit resolution Fully monotonic 3-wire SPI Power-on reset feature Hardware LDAC feature 2.7 V to 5.5 V single-supply operation Small footprint 10-lead, 3 mm × 3 mm, monometallic wire bonding MSOP

1.8 V logic compatible

APPLICATIONS

Downhole drilling and instrumentation Heavy industrial High temperature environments FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER DAC REGISTER VDD DGND DIN SCLK CS LDAC AD5600 15708-001 IOVDD VOUT AGND INTERFACE LOGIC DAC VREF Figure 1. GENERAL DESCRIPTION The AD5600 is a single channel, 16-bit resolution, voltage output digital-to-analog converter (DAC) designed for high temperature operation. The AD5600 guarantees 16-bit monotonicity over the specified temperature range and operates from a single 2.7 V to 5.5 V voltage supply. For space constrained applications, the AD5600 is available in a 10-lead MSOP with operation specified from −55°C to +175°C. This package is designed for robustness at extreme temperatures, including monometallic wire bonding, and is qualified for up to 1000 hours of operation at the maximum temperature rating. The AD5600 uses a versatile 3-wire serial peripheral interface (SPI) that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface standards. The AD5600 is a member of a growing series of high temperature qualified products offered by Analog Devices, Inc. For a complete selection of available high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp. PRODUCT HIGHLIGHTS 1. 16-bit monotonic DAC 2. 2.7 V to 5.5 V single-supply operation 3. 1.8 V logic compatible 4. Wide operating temperature range: −55°C to +175°C

Rev. A | Page 2 of 14 TABLE OF CONTENTS

REVISION HISTORY

3/2020—Rev. 0 to Rev. A 10/2019—Revision 0: Initial Version

Rev. A | Page 3 of 14 SPECIFICATIONS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit STATIC PERFORMANCE Resolution 16 Bit Relative Accuracy (INL) ±0.5 ±17 LSB Differential Nonlinearity (DNL) Guaranteed monotonic ±0.5 ±1.0 LSB Zero-Scale Error 0.3 ±16 LSB Temperature Coefficient ±0.05 ppm/°C Gain Error 0.5 ±22 LSB Temperature Coefficient ±0.1 ppm/°C DC Power Supply Rejection Ratio (PSRR) ±1.2 LSB OUTPUT CHARACTERISTICS Voltage Range 0 VREF − 1 LSB V Impedance 6.25 kΩ VOLTAGE REFERENCE INPUT Impedance 9 kΩ Range 2 VDD V Capacitance 26 pF LOGIC INPUTS Input Current ±1.0 μA Input Voltage Low (VINL) IOVDD = 1.65 V to 5.5 V 0.4 V IOVDD = 2.7 V to 5.5 V 0.8 V High (VINH) IOVDD = 1.65 V to 5.5 V 1.3 V IOVDD = 2.7 V to 5.5 V 2.4 V Pin Capacitance 10 pF Hysteresis Voltage 0.15 V POWER REQUIREMENTS Power Supply VDD Voltage VINH = IOVDD or VINL = DGND 2.7 5.5 V IOVDD Voltage VINH = IOVDD or VINL = DGND 1.65 5.5 V Analog Current (AIDD) 125 130 μA IOVDD Current (IOIDD) 15 24 μA

Rev. A | Page 4 of 14 AC CHARACTERISTICS noted. Table 2. Parameter Min Typ Max Unit Test Condition OUTPUT VOLTAGE SETTLING TIME 30 µs To divide the LSB of the full scale in half, load capacitance (CL) = 18 pF SLEW RATE 7 V/µs CL = 18 pF, measured from 0% to 63% DIGITAL-TO-ANALOG GLITCH IMPULSE 1.5 nV-sec 1 LSB change around major carry REFERENCE −3 dB Bandwidth 1.2 MHz All 1s loaded, VREF capacitance (CREF) = 0.1 µF Feedthrough 1.4 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz DIGITAL FEEDTHROUGH 0.4 nV-sec SIGNAL-TO-NOISE RATIO 95 dB SPURIOUS-FREE DYNAMIC RANGE 80 dB Digitally generated sine wave at 1 kHz TOTAL HARMONIC DISTORTION 74 dB DAC code = 0xFFFF , frequency 10 kHz, VREF = 2.5 V ± 1 V p-p OUTPUT Noise Spectral Density 14 nV/√Hz DAC code = 0x0000, frequency = 1 kHz Noise 1.25 µV p-p 0.1 Hz to 10 Hz TIMING CHARACTERISTICS VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of IOVDD, VINL = 10% of IOVDD, AGND = DGND = 0 V, and−55°C < TA < +175°C, unless otherwise noted. Table 3. Parameter1, 2 Limit at 1.62 ≤ IOVDD ≤ 2.7 V Limit at 2.7 V ≤ IOVDD ≤ 5.5 V Unit Description fSCLK 14 50 MHz max SCLK cycle frequency t1 70 20 ns min SCLK cycle time t2 35 10 ns min SCLK high time t3 35 10 ns min SCLK low time t4 5 5 ns min CS low to SCLK high setup t5 5 5 ns min CS high to SCLK high setup t6 5 5 ns min SCLK high to CS low hold time t7 10 5 ns min SCLK high to CS high hold time t8 35 10 ns min Data setup time t9 5 4 ns min Data hold time (VINH = 90% of IOVDD, VINL = 10% of IOVDD) t9 5 5 ns min Data hold time (VINH = 3 V, VINL = 0 V) t10 20 20 ns min LDAC pulse width t11 10 10 ns min CS high to LDAC low setup t12 15 15 ns min CS high time between active periods 1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with rise time (tR) = fall time (tF) = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.

TA = 25°C, unless otherwise noted. 1 The digital inputs include SCLK, DIN, CS, and LDAC.

2 Qualified for up to 1000 hours of operation at the maximum temperature

PCB thermal design is required. Table 5. Thermal Resistance

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board. See JEDEC JESD-51.

Figure 2. Pin Configuration Table 6. Pin Function Descriptions 2 VOUT Analog Output Voltage from the DAC. 3 AGND Analog Ground. Ground reference point for all analog circuitry on the device. 4 VREF Voltage Reference Input. Connect this pin to an external voltage reference. 5 CS Chip Select Input Signal. CS frames the serial data input. 6 SCLK Serial Clock Input Signal. Data is clocked into the serial input register on the rising edge of SCLK. written to the input register on the rising edge of CS. 9 DGND Digital Ground. Ground reference point for all digital circuitry on the device.

Rev. A | Page 11 of 14 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 3. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. A typical DNL vs. code plot is shown in Figure 6. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as LSB. It is the deviation in slope of the DAC transfer characteristic from the ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. This temperature coefficient is expressed in ppm/°C. Zero-Scale Error Zero-scale error is a measure of the output error when zero scale is loaded to the DAC register. Zero-Scale Temperature Coefficient Zero-scale temperature coefficient is a measure of the change in zero-scale error with a change in temperature. This temperature coefficient is expressed in ppm/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. This impulse is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure 16. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC. However, this feedthrough is measured when the DAC output is not updated. CS is held high while the SCLK and DIN signals are toggled. Digital feedthrough is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical digital feedthrough plot is shown in Figure 15. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. The DC power supply rejection ratio is expressed in terms of the LSB number change in the output of the DAC. VDD is varied by ±10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.

device operates from a supply voltage range of 2.7 V to 5.5 V. that the DAC output register powers up to a known state. Figure 26. Simplified DAC Architecture with SPI, QSPI, MICROWIRE and DSP interface standards. The serial interface can operate at clock rates up to 50 MHz. first, on the rising edge of the serial clock (SCLK). bits remain from the previous word loaded in. transfer of data from the input shift register to the DAC register. LDAC pin are ignored while the CS pin is low. undefined data from power-up.

0.50 BSC

1.10 MAX

Figure 28. 10-Lead Mini Small Outline Package [MSOP] registered trademarks are the property of their respective owners.