AD5542A

AD5512A/AD5542A (Rev. C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 21

Technical content

2.7 V to 5.5 V, Serial-Input, Voltage-Output, 12-/16-Bit DAC Data Sheet AD5512A/AD5542A Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2010–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1 LSB INL

11.8 nV/√Hz noise spectral density 1 µs settling time 1.1 nV-sec glitch energy 0.05 ppm/°C temperature drift 5 kV HBM ESD classification 0.375 mW power consumption at 3 V 2.7 V to 5.5 V single-supply operation Hardware CLR and LDAC functions

50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface

Power-on reset clears DAC output to midscale Available in 3 mm × 3 mm, 10-/16-lead LFCSP and 16-lead TSSOP

APPLICATIONS

Precision source-measure instruments Data acquisition systems Medical and aerospace instrumentation Communication equipment GENERAL DESCRIPTION The AD5512A/AD5542A are single, 12-/16-bit, serial input, unbuffered voltage output digital-to-analog converters (DAC) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to V REF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C (AD5542A) or −40°C to +125°C (AD5512A). Offering unbuffered outputs, the AD5512A/AD5542A achieve a 1 μs settling time with low offset errors ideal for high speed open loop control. The AD5512A/AD5542A incorporate a bipolar mode of operation that generates a ±V REF output swing. The AD5512A/AD5542A also include Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD5512A/AD5542A are available in a 16-lead LFCSP with the AD5542A also available in a 10-lead LFCSP and a 16-lead TSSOP . The AD5512A/AD5542A use a versatile 3-wire interface that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface standards. FUNCTIONAL BLOCK DIAGRAM 16-BIT DAC 16-BIT DAC LATCH VDD DGND LDAC REFF VLOGIC CS DIN CLR VOUT INV RFB AD5512A/ AD5542A SCLK RFB RINV 09199-001 REFS AGNDF AGNDS CONTROL LOGIC SERIAL INPUT REGISTER Figure 1. 16-Lead TSSOP and 16-Lead LFCSP

7 INV

8 RFBAD5542A-1

Figure 2. 10-Lead LFCSP Table 1. Related Devices

1. 16-bit performance without adjustment.
2. 2.7 V to 5.5 V single supply operation.
3. Low 11.8 nV/√Hz noise spectral density.
4. Low 0.05 ppm/°C temperature drift.
5. 3 mm × 3 mm LFCSP and TSSOP packaging.

AD5512A/AD5542A Data Sheet Rev. C | Page 2 of 21 TABLE OF CONTENTS

REVISION HISTORY

2/2017—Rev. B to Rev. C 4/2015—Rev. A to Rev. B Deleted AD5512A/AD5542A to ADSP-2101 Interface Section .. 18 5/2011—Rev. 0 to Rev. A Changes to Table 3, Power Dissipation Value and Endnote 1 .... 4 10/2010—Revision 0: Initial Version

Data Sheet AD5512A/AD5542A Rev. C | Page 3 of 21 SPECIFICATIONS AD5512A Table 2. Parameter1 Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error +0.5 ±2 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero-Code Error 0.03 ±0.5 LSB Unipolar Zero-Code Temperature Coefficient ±0.05 ppm/°C Bipolar Resistor Matching 1 Ω/Ω RFB/RINV, typically RFB = RINV = 28 kΩ ±0.02 ±0.08 % Ratio error Bipolar Zero Offset Error ±0.07 ±2 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero-Code Offset Error ±0.02 ±0.5 LSB Bipolar Gain Error ±0.07 ±2 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF − 1 LSB V Unipolar operation −VREF +VREF − 1 LSB V Bipolar operation DAC Output Impedance 6.25 kΩ Tolerance typically 20% Power Supply Rejection Ratio ±1.0 LSB ΔVDD ± 10% Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x840 (AD5512A) or 0x8400 (AD5542A), frequency = 1 kHz, unipolar mode Output Noise 0.134 μV p-p 0.1 Hz to 10 Hz, unipolar mode DAC REFERENCE INPUT2 Reference Input Range 2.0 VDD V Reference Input Resistance3 9 kΩ Unipolar operation 7.5 kΩ Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0x3FFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.8 V VDD = 2.7 V to 5.5 V Input High Voltage, VINH 2.4 V VDD = 2.7 V to 5.5 V Input Capacitance2 10 pF Hysteresis Voltage2 0.15 V POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V, VLOGIC, or VDD IDD 125 150 µA VIH = VLOGIC or VDD and VIL = GND VLOGIC 1.8 5.5 V ILOGIC 15 24 µA All digital inputs at 0 V, VLOGIC, or VDD Power Dissipation 1.5 6.05 mW 1 Temperatures are as follows: A version −40°C to +125°C. 2 Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x855.

AD5512A/AD5542A Data Sheet Rev. C | Page 4 of 21 AD5542A Table 3. Parameter1 Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade ±2.0 A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error +0.5 ±2 LSB TA = 25°C ±3 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero-Code Error 0.3 ±0.7 LSB TA = 25°C ±1.5 LSB Unipolar Zero-Code Temperature Coefficient ±0.05 ppm/°C Bipolar Resistor Matching 1.000 Ω/Ω RFB/RINV, typically RFB = RINV = 28 kΩ ±0.0015 ±0.0076 % Ratio error Bipolar Zero Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero-Code Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF − 1 LSB V Unipolar operation −VREF +VREF − 1 LSB V Bipolar operation DAC Output Impedance 6.25 kΩ Tolerance typically 20% Power Supply Rejection Ratio ±1.0 LSB ΔVDD ± 10% Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x840 (AD5512A) or 0x8400 (AD5542A), frequency = 1 kHz, unipolar mode Output Noise 0.134 μV p-p 0.1 Hz to 10 Hz DAC REFERENCE INPUT2 Reference Input Range 2.0 VDD V Reference Input Resistance3 9 kΩ Unipolar operation 7.5 kΩ Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.8 V VDD = 2.7 V to 5.5 V Input High Voltage, VINH 2.4 V VDD = 2.7 V to 5.5 V Input Capacitance2 10 pF Hysteresis Voltage2 0.15 V POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V, VLOGIC, or VDD IDD 125 150 µA VIH = VLOGIC or VDD and VIL = GND VLOGIC 1.8 5.5 V ILOGIC 15 24 µA All digital inputs at 0 V, VLOGIC, or VDD Power Dissipation 0.625 0.825 mW 1 For 2.7 V ≤ VLOGIC ≤ 5.5 V, temperatures are as follows: A, B versions −40°C to +85°C. 2 Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x8555.

Data Sheet AD5512A/AD5542A Rev. C | Page 5 of 21 AC CHARACTERISTICS Table 4. Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF Slew Rate 17 V/µs CL = 10 pF, measured from 0% to 63% Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz Digital Feedthrough 0.2 nV-sec Signal-to-Noise Ratio 92 dB Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz Total Harmonic Distortion 74 dB DAC code = 0x3FFF (AD5512A) or 0xFFFF (AD5542A), frequency 10 kHz, VREF = 2.5 V ± 1 V p-p

VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. Figure 3. Timing Diagram

Data Sheet AD5512A/AD5542A Rev. C | Page 7 of 21 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter Rating VDD to AGND −0.3 V to +6 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V VOUT to AGND −0.3 V to VDD + 0.3 V AGNDF , AGNDS to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range AD5512A Industrial (A Version) −40°C to +125°C AD5542A Industrial (A, B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ max) 150°C Package Power Dissipation (TJ max − TA)/θJA Thermal Impedance, θJA TSSOP (RU-16) 113°C/W LFCSP (CP-16-22) 73°C/W LFCSP (CP-10-9) 74°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1 As per JEDEC Standard 20. 2 HBM classification.

9 DIN

1. THE EXPOSED PAD SHOULD BE TIED

Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration

10 GND

1. THE EXPOSED PAD SHOULD BE TIED

Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration Table 7. AD5512A/AD5542A Pin Function Descriptions 1 6 V OUT Analog Output Voltage from the DAC. 2 AGNDF Ground Reference Point for Analog Circuitry (Force). 3 AGNDS Ground Reference Point for Analog Circuitry (Sense). 6 2 CS Logic Input Signal. The chip select signal is used to frame the serial data input. are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale. contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. amps inverting input in bipolar mode. 14 V LOGIC Logic Power Supply. 15 9 V DD Analog Supply Voltage, 5 V ± 10%. 16 8 R FB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. EPAD EPAD Exposed Pad The exposed pad should be tied to the point of lowest potential, in this case, GND.

Figure 6. AD5542A 16-Lead TSSOP Pin Configuration Table 8. AD5542A Pin Function Descriptions 1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. 2 VOUT Analog Output Voltage from the DAC. 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 8 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale. 13 DGND Digital Ground. Ground reference for digital circuitry. 15 VLOGIC Logic Power Supply. 16 VDD Analog Supply Voltage, 5 V ± 10%.

Figure 19. AD5512A/AD5542A Digital Feedthrough Figure 20. AD5512A/AD5542A Digital-to-Analog Glitch Impulse

100 CS (5V/DIV)

Figure 21. AD5512A/AD5542A Large Signal Settling Time

100 VOUT (1V/DIV)

Figure 22. AD5512A/AD5542A Small Signal Settling Time Figure 23. AD5512A/AD5542A Analog Supply Current Histogram Figure 24. AD5512A/AD5542A Digital Supply Current Histogram

AD5512A/AD5542A Data Sheet Rev. C | Page 14 of 21 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures mono- tonicity. A typical DNL vs. code plot is shown in Figure 10. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/°C. Zero-Code Error Zero-code error is a measure of the output error when zero code is loaded to the DAC register. Zero-Code Temperature Coefficient This is a measure of the change in zero-code error with a change in temperature. It is expressed in mV/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure 20. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the SCLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical digital feedthrough plot is shown in Figure 19. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. The power supply rejection ratio is quoted in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by ±10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.

state, these parts are designed with a power-on reset function. The DAC architecture consists of two matched DAC sections. connects one of 15 matched resistors to either AGND or VREF. switches of a 12-bit voltage mode R-2R ladder network. Figure 30. DAC Architecture D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC.

5.2 DVOUT

with full scale loaded to the DAC. The LSB size is VREF/65,536. interface standards. The timing diagram is shown in Figure 3. These DACs are capable of driving unbuffered loads of 60 kΩ. provide a unipolar output swing ranging from 0 V to VREF. mode of operation is shown in Table 9. Figure 31. Unipolar Output Table 9. AD5542A Unipolar Code Table

OUT−UNI is the unipolar mode worst-case output. D is the code loaded to DAC. N is the resolution of the DAC. VREF is the reference voltage applied to the part. VGE is the gain error in volts. VZSE is the zero-scale error in volts. INL is the integral nonlinearity in volts. shows the transfer function for this output operating mode.

2.5 V reference and the AD8628 low offset and zero-drift

Table 10. AD5542A Bipolar Code Table VOUT−UNI is the unipolar mode worst-case output. VOS is the external op amp input offset voltage. RD is the RFB and RINV resistor matching error. A is the op amp open-loop gain. Figure 32. Bipolar Output

Data Sheet AD5512A/AD5542A Rev. C | Page 17 of 21 OUTPUT AMPLIFIER SELECTION For bipolar mode, a precision amplifier should be used and supplied from a dual power supply. This provides the ±VREF output. In a single-supply application, selection of a suitable op amp may be more difficult because the output swing of the ampli- fier does not usually include the negative rail, in this case, AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp must have a very low-offset voltage (the DAC LSB is 38 μV for the AD5542A with a 2.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 kΩ), adds to the zero-code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. FORCE SENSE AMPLIFIER SELECTION Use single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to ±20 mA. REFERENCE AND GROUND Because the input impedance is code-dependent, the refer- ence pin should be driven from a low impedance source. The AD5512A/AD5542A operate with a voltage reference ranging from 2 V to VDD. References below 2 V result in reduced accuracy. The full-scale output voltage of the DAC is determined by the reference. Table 9 and Table 10 outline the analog output voltage or particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5512A/AD5542A. If the application doesn’t require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. POWER-ON RESET The AD5512A/AD5542A have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register MSB is 1 and all other bits are 0 until the data is loaded from the serial register. However, the serial register is not cleared on power-up; therefore, its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5512A/AD5542A must be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs. POWER SUPPLY AND REFERENCE BYPASSING For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.50 BSC

0.20 MIN

Figure 41. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] registered trademarks are the property of their respective owners.