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2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs Data Sheet AD5541/AD5542 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2012 Analog Devices, Inc. All rights reserved.
FEATURES
3 V and 5 V single-supply operation
Low 0.625 mW power dissipation 1 µs settling time Unbuffered voltage output capable of driving 60 kΩ loads directly SPI-/QSPI-/MICROWIRE-compatible interface standards Power-on reset clears DAC output to 0 V (unipolar mode) 5 kV HBM ESD classification Low glitch: 1.1 nV-sec
APPLICATIONS
Digital gain and offset adjustment Automatic test equipment Data acquisition systems Industrial process control GENERAL DESCRIPTION The AD5541/AD5542 are single, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF. The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C. Offering unbuffered outputs, the AD5541/AD5542 achieve a 1 µs settling time with low power consumption and low offset errors. Providing a low noise performance of 11.8 nV/√Hz and low glitch, the AD5541/AD5542 is suitable for deployment across multiple end systems. The AD5542 can be operated in bipolar mode, which generates a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD5541/AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™ and DSP interface standards. The AD5541/AD5542 are available in 8-lead and 14-lead SOIC packages. FUNCTIONAL BLOCK DIAGRAMS 16-BIT DAC 16-BIT DAC LATCH SERIAL INPUT REGISITER VDD DGND DIN REF CS SCLK VOUT AGND AD5541 CONTROL LOGIC 07557-001 Figure 1. AD5541
13 INV
1 RFB
4 AGNDS
Figure 2. AD5542
- Single-Supply Operation. The AD5541 and AD5542 are fully
specified and guaranteed for a single 2.7 V to 5.5 V supply.
- Low Power Consumption. These parts consume typically
0.625 mW with a 5 V supply and 0.375 mV at 3 V .
- Unbuffered Output Capable of Driving 60 kΩ Loads. This
- Power-On Reset Circuitry.
Rev. F | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
3/12—Rev. E to Rev. F 3/11—Rev. D to Rev. E 2/11—Rev. C to Rev. D Changes to Features Section, General Description Section, Added Output Noise Spectral Density Parameter and Output 4/10—Rev. B to Rev. C 8/08—Rev. A to Rev. B 10/99—Rev. 0 to Rev. A
Rev. F | Page 3 of 20 SPECIFICATIONS Table 2. Parameter1 Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB L, C grades ±0.5 ±2.0 LSB B, J grades ±0.5 ±4.0 LSB A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic ±1.5 LSB J grade Gain Error +0.5 ±2 LSB TA = 25°C ±3 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero Code Error ±0.3 ±0.7 LSB TA = 25°C ±1.5 LSB Unipolar Zero Code Temperature Coefficient ±0.05 ppm/°C AD5542 Bipolar Resistor Matching 1.000 Ω/Ω RFB/RINV, typically RFB = RINV = 28 kΩ ±0.0015 ±0.0076 % Ratio error Bipolar Zero Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero Code Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Error +1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF − 1 LSB V Unipolar operation −VREF VREF − 1 LSB V AD5542 bipolar operation Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF Slew Rate 17 V/μs CL = 10 pF, measured from 0% to 63% Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, VREF = 2.5 V DAC Output Impedance 6.25 kΩ Tolerance typically 20% Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x8400, frequency = 1 kHz Output Noise 0.134 µV p-p 0.1 Hz to 10 Hz Power Supply Rejection Ratio ±1.0 LSB ΔVDD ± 10% DAC REFERENCE INPUT Reference Input Range 2.0 VDD V Reference Input Resistance2 9 kΩ Unipolar operation 7.5 kΩ AD5542, bipolar operation LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.8 V Input High Voltage, VINH 2.4 V Input Capacitance3 10 pF Hysteresis Voltage3 0.15 V REFERENCE 3 Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz Signal-to-Noise Ratio 92 dB Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF
1 Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C. 2 Reference input resistance is code-dependent, minimum at 0x8555. 3 Guaranteed by design, not subject to production test. +85°C, unless otherwise noted. 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. *AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED. Figure 3. Timing Diagram
Rev. F | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to AGND −0.3 V to +6 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V VOUT to AGND −0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (A, B, C Versions) −40°C to +85°C Commercial (J, L Versions) 0°C to 70°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ max) 150°C Package Power Dissipation (TJ max – TA)/θJA Thermal Impedance, θJA SOIC (R-8) 149.5°C/W SOIC (R-14) 104.5°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 As per JEDEC Standard 20. 2 HBM Classification.
Rev. F | Page 10 of 20 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures mono- tonicity. Figure 9 illustrates a typical DNL vs. code plot. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/°C. Zero Code Error Zero code error is a measure of the output error when zero code is loaded to the DAC register. Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the digital-to- analog glitch impulse is shown in Figure 19. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the CLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 18. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by ±10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
state, these parts are designed with a power-on reset function. the reference and analog ground are included on the AD5542. The DAC architecture consists of two matched DAC sections. Figure 22. DAC Architecture D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC.
5.2 DVOUT
full-scale loaded to the DAC. The LSB size is VREF/65,536. the input register on the rising edge of the serial clock, SCLK. can be loaded to the part only while CS is low. permanently low, the rising edge of CS loads the data to the DAC. These DACs are capable of driving unbuffered loads of 60 kΩ. for this mode of operation is shown in Table 7. Figure 23. Unipolar Output Table 7. Unipolar Code Table
VOUT−UNI is unipolar mode worst-case output. VREF is reference voltage applied to the part. VZSE is zero scale error in volts. INL is integral nonlinearity in volts. Kelvin connections to the analog ground inputs. Figure 24. Bipolar Output (AD5542 Only) Table 8. Bipolar Code Table VOUT-BIP is the bipolar mode worst-case output. VOUT−UNI is the unipolar mode worst-case output. VOS is the external op amp input offset voltage. RD is the RFB and RINV resistor matching error. A is the op amp open-loop gain. does not usually include the negative rail, in this case, AGND. unless the application does not use codes near zero. impedance (approximately 6 kΩ), adds to the zero code error. settling time of the combined DAC and amplifier. be able to handle dynamic currents of up to ±20 mA. scale output voltage of the DAC is determined by the reference. connections are provided on the AD5542. drops between the package leads and the internal die.
Rev. F | Page 13 of 20 POWER-ON RESET The AD5541/AD5542 have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541/AD5542 need to be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs. POWER SUPPLY AND REFERENCE BYPASSING For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
Rev. F | Page 17 of 20 ORDERING GUIDE Model1 INL DNL Temperature Range Package Description Package Option AD5541CR ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541CRZ ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541LR ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LR-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LRZ ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LRZ-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541BR ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541BRZ ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541BRZ-REEL ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541JR ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JRZ ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541AR ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541ARZ ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5542CR ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CR-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CRZ ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542LR ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542LRZ ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542BR ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542BRZ ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542BRZ-REEL7 ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542JR ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JRZ ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542AR ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542ARZ ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 EVAL-AD5541/42EBZ Evaluation Board 1 Z = RoHS Compliant Part.
Rev. F | Page 18 of 20 NOTES
Rev. F | Page 19 of 20 NOTES
Rev. F | Page 20 of 20 NOTES ©1999–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07557-0-3/12(F)