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2.7 V to 5.5 V, Serial-Input, Voltage Output, Unbuffered 16-Bit DAC Data Sheet AD5541A Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
11.8 nV/√Hz noise spectral density 1 µs settling time 1.1 nV-sec glitch energy 0.05 ppm/°C temperature drift 5 kV HBM ESD classification 0.375 mW power consumption at 3 V 2.7 V to 5.5 V single-supply operation Hardware CS and LDAC functions
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
Power-on reset clears DAC output to zero scale Available in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead MSOP
APPLICATIONS
Precision source-measure instruments Data acquisition systems Medical instrumentation Aerospace instrumentation Communications infrastructure equipment Industrial control FUNCTIONAL BLOCK DIAGRAMS 16-BIT DAC 16-BIT DAC LATCH SERIAL INPUT REGISTER VDD VLOGIC DGND DIN REF SCLK CS LDAC VOUT AGND AD5541A 08516-001 CONTROL LOGIC Figure 1. AD5541A Figure 2. AD5541A-1 single 2.7 V to 5.5 V supply. tling time with low power consumption and low offset errors. Table 1. Related Devices
- 16-bit performance without adjustment.
- 2.7 V to 5.5 V single operation.
- Low 11.8 nV/√Hz noise spectral density.
- Low 0.05 ppm/°C temperature drift.
- 3 mm × 3 mm LFCSP and MSOP packaging.
Rev. B | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
4/2018—Rev. A to Rev. B 3/2011—Rev. 0 to Rev. A Changes to Features, General Description, and Product Changed VREF to VREF – 1 LSB in Unipolar Output Operation 7/2010—Revision 0: Initial Version
Rev. B | Page 3 of 20 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C,1 unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade ±0.5 ±2.0 LSB A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error 0.5 ±2 LSB TA = 25°C ±3 LSB −40°C < TA < +85°C ±4 LSB −40°C < TA < +125°C Gain Error Temperature Coefficient ±0.1 ppm/°C Zero-Code Error 0.3 ±0.7 LSB TA = 25°C ±1.5 LSB −40°C < TA < +85°C ±3 LSB −40°C < TA < +125°C Zero-Code Temperature Coefficient ±0.05 ppm/°C DC Power Supply Rejection Ratio ±1 LSB ΔVDD ± 10% OUTPUT CHARACTERISTICS2 Output Voltage Range 0 VREF − 1 LSB V Unipolar operation DAC Output Impedance 6.25 kΩ Tolerance typically 20% DAC REFERENCE INPUT3 Reference Input Range 2.0 VDD V Reference Input Resistance 9 kΩ Unipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.4 V VLOGIC = 1.8 V to 5.5 V 0.8 V VLOGIC = 2.7 V to 5.5 V Input High Voltage, VINH 2.4 V VLOGIC = 4.5 V to 5.5 V 1.8 V VLOGIC = 2.7 V to 3.6 V 1.3 V VLOGIC = 1.8 V to 2.7 V Input Capacitance2 10 pF Hysteresis Voltage2 0.15 V POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V, VLOGIC, or VDD IDD 125 150 µA VIH = VLOGIC or VDD and VIL = GND VLOGIC 1.8 5.5 V ILOGIC 15 24 µA All digital inputs at 0 V, VLOGIC, or VDD Power Dissipation 0.625 0.825 mW 2 Guaranteed by design, but not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x8555.
Rev. B | Page 4 of 20 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time 1 μs To ½ LSB of full scale, CL = 10 pF Slew Rate 17 V/μs CL = 10 pF, measured from 0% to 63% Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz Digital Feedthrough 0.2 nV-sec Signal-to-Noise Ratio 92 dB Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz Total Harmonic Distortion 74 dB DAC code = 0xFFFF , frequency 10 kHz, VREF = 2.5 V ± 1 V p-p Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x0000, frequency = 1 kHz Output Noise 1.25 μV p-p 0.1 Hz to 10 Hz
1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. Figure 3. Timing Diagram
Rev. B | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to AGND −0.3 V to +6 V VLOGIC to DGND −0.3 V to +6 V Digital Input Voltage to DGND −0.3 V to VDD/VLOGIC + 0.3 V VOUT to AGND −0.3 V to VDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (A, B Versions) −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ max) 150°C Package Power Dissipation (TJ max − TA)/θJA Thermal Impedance, θJA LFCSP (CP-10-9) 50°C/W LFCSP (CP-8-11) 62°C/W MSOP (RM-10) 135°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV 1 As per JEDEC Standard 20. 2 Human body model (HBM) classification. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 4. AD5541A 10-Lead MSOP Pin Configuration Table 6. AD5541A Pin Function Descriptions 1 VDD Analog Supply Voltage. 2 VOUT Analog Output Voltage from the DAC. 3 AGND Ground Reference Point for Analog Circuitry. 5 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 9 DGND Digital Ground. Ground reference for digital circuitry. 10 VLOGIC Logic Power Supply.
- FOR INCREASED RELIABILITY OF THE SOLDER
Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration
10 V LOGIC
- FOR INCREASED RELIABILITY OF THE SOLDER
Figure 6. AD5541A 10-Lead LFCSP Pin Configuration Table 7. AD5541A-1 and AD5541A Pin Function Descriptions reference can range from 2 V to VDD. 2 5 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 3 6 SCLK Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. register on the rising edge of SCLK. register are cleared to zero scale. 6 2 V OUT Analog Output Voltage from the DAC. N/A1 9 DGND Digital Ground. Ground reference for digital circuitry. 7 1 V DD Analog Supply Voltage. 8 N/A 1 GND Ground Reference Point for Both Analog and Digital Circuitry. N/A1 3 AGND Ground Reference Point for Analog Circuitry. N/A1 10 V LOGIC Logic Power Supply. with the contents of the serial input register. capability, it is recommended that the pad be soldered to the substrate, GND.
Rev. B | Page 13 of 20 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures mono- tonicity. A typical DNL vs. code plot is shown in Figure 10. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/°C. Zero-Code Error Zero-code error is a measure of the output error when zero code is loaded to the DAC register. Zero-Code Temperature Coefficient This is a measure of the change in zero-code error with a change in temperature. It is expressed in mV/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure 20. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the SCLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical digital feedthrough plot is shown in Figure 19. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. The power supply rejection ratio is expressed in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by ±10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the V REF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
with a power-on reset function. The output is reset to 0 V. The DAC architecture consists of two matched DAC sections. Figure 30. DAC Architecture D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC.
5.2 DVOUT
full scale loaded to the DAC. The LSB size is VREF/65,536. CS transfers the contents into the serial input register only. words. Data can be loaded to the part only while CS is low.
Rev. B | Page 16 of 20 FORCE SENSE AMPLIFIER SELECTION Use single-supply, low noise amplifiers. A low output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to ±20 mA. REFERENCE AND GROUND Because the input impedance is code dependent, drive the refer- ence pin from a low impedance source. The AD5541A operates with a voltage reference ranging from 2 V to VDD. References below 2 V result in reduced accuracy. The full-scale output voltage of the DAC is determined by the reference. Table 8 outlines the analog output voltage or particular digital codes. If the application does not require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. POWER-ON RESET The AD5541A has a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up; therefore, its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541A must be interfaced with data shorter than 16 bits, pad the data with 0s at the LSBs. POWER SUPPLY AND REFERENCE BYPASSING For accurate high resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
analog signal channels. Figure 35 shows a typical circuit. Figure 35. Addressing Multiple DACs
0.50 BSC
1.10 MAX
Figure 36. 10-Lead Mini Small Outline Package [MSOP]
0.20 REF
0.05 MAX
0.02 NOM
0.20 MIN
Figure 37. 10-Lead Lead Frame Chip Scale Package [LFCSP]
0.203 REF
Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.