AD5535BKBC

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32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V Data Sheet AD5535B Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

32-channel, 14-bit denseDAC® with integrated high voltage output amplifier Guaranteed monotonic Housed in 15 mm × 15 mm CSP_BGA package Full-scale output voltage programmable from 50 V to 200 V via reference input 550 µA drive capability Integrated silicon diode for temperature monitoring DSP-/microcontroller-compatible serial interface

1.2 MHz channel update rate

Asynchronous RESET facility –10°C to +85°C temperature range

APPLICATIONS

Optical microelectromechanical systems (MEMS) Optical crosspoint switches Micropositioning applications using piezoelectric actuators Level setting in automotive test and measurement GENERAL DESCRIPTION The AD5535B is a 32-channel, 14-bit denseDAC® with an on-chip high voltage output amplifier. This device is targeted for optical micro-electromechanical systems. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V , and 0 V to 200 V when REF_IN = 4 V. Each amplifier can source 550 µA, which is ideal for the deflection and control of optical MEMS mirrors. The selected digital-to-analog converter (DAC) register is written to via the 3-wire interface. The serial interface operates at clock rates of up to 30 MHz and is compatible with DSP and micro- controller interface standards. The device is operated with AV CC = 4.75 V to 5.25 V , DVCC = REF_IN is buffered internally on the AD5535B and should be driven from a stable reference source. FUNCTIONAL BLOCK DIAGRAM Figure 1. RF RF RF RF R1INTERFACE CONTROL LOGIC DAC DAC DAC DAC DVCC AVCC SYNCDINSCLK DGND AGND DAC_GND RESET REF_IN VPP PGND V+ 14-BIT BUS ANODE CATHODE VOUT0 VOUT1 VOUT30 VOUT31 AD5535B 10852-001

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

4/13—Rev. 0 to Rev. A 1/13—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS VPP = 215 V; V+ = 5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V; all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 K Grade2 Unit Test Conditions/Comments Min Typ Max DC PERFORMANCE3 Resolution 14 Bits Integral Nonlinearity (INL) ±0.1 % of FSR Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Guaranteed monotonic Zero Code Voltage 0.5 1 V Output Offset Error –1 +1 V Offset Drift 0.5 mV/°C Voltage Gain 49 50 51 V/V Gain Temperature Coefficient 5 ppm/°C Due to DAC –200 ppm/°C Due to DAC and amplifier Channel-to-Channel Gain Match4 –5 +5 % OUTPUT CHARACTERISTICS Output Voltage Range3 1 VPP − 1 V Output Impedance 50 Ω Resistive Load4, 5 1 MΩ Capacitive Load4 200 pF Short-Circuit Current 0.55 mA DC Crosstalk4 3 4 LSB DC Power Supply Rejection (PSRR), VPP 70 dB Long-Term Drift 0.25 LSB Outputs at midscale, measured over 30 days at 25°C AC CHARACTERISTICS4 Settling Time ¼ to ¾ Scale Step 60 µs No load 60 µs 200 pF load

1 LSB Step 5 µs No load

5 µs 200 pF load Slew Rate 10 V/µs No load

3 V/µs 200 pF load

–3 dB Bandwidth 30 kHz Output Noise Spectral Density 4.5 µV/√Hz Measured at 10 kHz

0.1 Hz to 10 Hz Output Noise Voltage 1 mV p-p

Digital-to-Analog Glitch Impulse 1 LSB change around major carry Positive Transition 15 nV-sec Negative Transition 8 nV-sec Analog Crosstalk 2.5 µV-sec Digital Feedthrough 2 nV-sec VOLTAGE REFERENCE, REF_IN6 AVCC and V+ must exceed REF_IN by 1.15 V minimum Input Voltage Range4 1 4.096 V Input Impedance 60 kΩ

Rev. A | Page 4 of 16 Parameter1 K Grade2 Unit Test Conditions/Comments Min Typ Max TEMPERATURE MEASUREMENT DIODE4 Peak Inverse Voltage, PIV 5 V Cathode to anode Forward Diode Drop, VF 0.65 0.8 V IF = 100 µA, anode to cathode Forward Diode Current, IF 100 µA Anode to cathode VF Temperature Coefficient, TC −2.20 mV/°C Anode to cathode DIGITAL INPUTS4 Input Current ±5 ±10 µA Input Low Voltage 0.8 V Input High Voltage 2.0 V Input Hysteresis (SCLK and SYNC Only) 200 mV Input Capacitance 10 pF POWER SUPPLY VOLTAGES VPP (50 × REF_IN) + 1 225 V V+ 4.75 5.25 V AVCC 4.75 5.25 V DVCC 2.7 5.25 V POWER SUPPLY CURRENTS7 IPP All Channels at Full-Scale 50 60 µA/channel All Channels at Zero-Scale 25 35 µA/channel I+ 1.2 1.7 mA AICC 17.5 20 mA DICC 0.25 0.6 mA 1 See the Terminology section. 2 K Grade temperature range: −10°C to +85°C; typical = +25°C. 3 Linear output voltage range: 7 V to VPP − 1 V. 4 Guaranteed by design and characterization, not production tested. 5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section. 6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to VPP − 1 V. 7 Outputs unloaded.

to TMAX, unless otherwise noted. 2 Guaranteed by design and characterization, not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2. Figure 2. Serial Interface Timing Diagram

Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VPP to AGND 0.3 V to 240 V V+ to AGND −0.3 V to +7 V AVCC to AGND, DAC_GND −0.3 V to +7 V DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_GND −0.3 V to AVCC + 0.3 V VOUT0 to VOUT31 to AGND –0.3 V to VPP + 0.3 V ANODE/CATHODE to AGND, DAC_GND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V Operating Temperature Range Industrial −10°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 124-Lead CSP_BGA Package, θJA Thermal Impedance 40°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD Human Body Model 2.5 kV Machine Model 250 V Field Induced Charged Device Model 400 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION

Figure 3. Pin Configuration Table 4. Pin Assignments

Table 5. Pin Function Descriptions AVCC Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VPP Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 1 V to 225 V. V+ V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V. PGND Output Amplifier Ground Reference Pins. DVCC Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. DAC_GND Reference GND Supply for All DACs. scale output voltage from 50 V to 200 V. VOUT0 to VOUT31 Analog Output Voltages from the 32 Channels. ANODE Anode of Internal Diode for Diode Temperature Measurement. CATHODE Cathode of Internal Diode for Diode Temperature Measurement. upon the falling edge of SCLK. DIN Serial Data Input. Data must be valid upon the falling edge of SCLK. TEST For normal operation, tie this pin low. NC No Connect. Do not connect to these pins.

Rev. A | Page 11 of 16 TERMINOLOGY Integral Nonlinearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range. Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. Zero Code Voltage A measure of the output voltage present at the device output with all 0s loaded to the DAC. It includes the offset of the DAC and the output amplifier and is expressed in V . Offset Error Calculated by taking two points in the linear region of the transfer function, drawing a line through these points, and extrapolating back to the y-axis. It is expressed in V . Voltage Gain Calculated from the change in output voltage for a change in code, multiplied by 16,384, and divided by the REF_IN voltage. This is calculated between two points in the linear section of the transfer function. Gain Error A measure of the output error with all 1s loaded to the DAC, and the difference between the ideal and actual analog output range. Ideally, the output should be 50 × REF_IN. It is expressed as a percentage of full-scale range. DC Power Supply Rejection Ratio (PSRR) A measure of the change in analog output for a change in V PP supply voltage. It is expressed in dB, and VPP is varied ±5%. DC Crosstalk The dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSB. Output Voltage Settling Time The time taken from when the last data bit is clocked into the DAC until the output has settled to within ±0.5 LSB of its final value. Measured for a step change of ¼ to ¾ full scale. Digital-to-Analog Glitch Impulse The area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-sec when the digital code is changed Analog Crosstalk The area of the glitch transferred to the output (V OUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-sec. Digital Feedthrough A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to SYNC is high). It is specified in nV-sec and measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s and vice versa. Output Noise Spectral Density A measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in μV/√Hz.

loaded into the AD5535B input register via the serial interface. into an analog output voltage for this channel. At power-on, all the DAC registers are loaded with 0s.

50 DVV INREF

code, which is loaded to the DAC register. typically 60 µs with a load of up to 200 pF . the RESET pin low to implement the reset function.

• SYNC, which is the frame synchronization pin for the serial interface.
• SCLK, which is the serial clock input that operates at clock speeds of up to 30 MHz.
• DIN, which is the serial data input and data must be valid upon the falling edge of SCLK. To update a single DAC channel, a 19-bit data-word is written to the AD5535B input register. A4 to A0 Bits The A4 to A0 bits can address any one of the 32 channels. A4 is the MSB of the address, while A0 is the LSB. DB13 to DB0 Bits The DB13 to DB0 bits are used to write a 14-bit data-word into the addressed DAC register. Figure 2 is the timing diagram for a serial write to the AD5535B. The serial interface works with both a continuous and a discontinuous serial clock. The first falling edge of SYNC resets the serial clock counter to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC are ignored until the correct number of bits are shifted in. After 19 bits are shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. The user must allow 200 ns (minimum) between successive writes.

Figure 15. Serial Data Format SCLKs while TFS is low. Figure 16 shows the connection diagram. Figure 16. AD5535B-to-ADSP-BF527 Interface

Rev. A | Page 15 of 16 POWER SUPPLY DECOUPLING RECOMMENDATIONS On the AD5535B, it is recommended to tie all grounds together as close to the device as possible. If the number of supplies must be reduced, bring all supplies back separately and make a provision on the board via a link option to drive the AVCC and V+ pins from the same supply. Decouple all power supplies adequately with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors. GUIDELINES FOR PCB LAYOUT Design printed circuit boards such that the analog and digital sections are separated and confined to the designated analog and digital sections of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally the best for ground planes because it optimizes shielding of sensitive signal lines. Join digital and analog ground planes in one place only, at the AGND and DGND pins of the high resolution converter. To isolate the high frequency bus of the processor from the bus of the high resolution converters, buffer or latch data and address buses on the board. These act as a Faraday shield and increase the signal-to-noise performance of the converters by reducing the amount of high frequency digital coupling. Avoid running digital lines under the device because they couple noise onto the die. Allow the ground plane to run under the IC to avoid noise coupling. Use as large a trace as possible for the supply lines of the device to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield components, such as clocks with fast-switching signals, with digital ground to avoid radiating noise to other sections of the board. Never run clock signals near the analog inputs of the device. Avoid crossovers of digital and analog signals. Keep traces for analog inputs as wide and short as possible and shield with analog ground if possible. Run traces on opposite sides of the 2-layer PCB at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible to use with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Multilayer printed circuit boards with dedicated ground, power, and tracking layers offer the optimum solution in terms of obtaining analog performance, but at increased manufacturing costs. Good decoupling is vitally important when using high resolu- tion converters. Decouple all analog supplies with 10 µF tantalum capacitors in parallel with 0.1 µF ceramic capacitors to analog ground. To achieve the best results from the decoupling components, place them as close to the device as possible, ideally right up against the IC or the IC socket. The main aim of a bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thereby reducing the possibility of power supply spikes. Decouple digital supplies of high resolution converters with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors to the digital ground plane. Decouple the V + supply with a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor to AGND. Decouple all logic chips with 0.1 µF ceramic capacitors to digital ground to decouple high frequency effects associated with digital circuitry.

Figure 22. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

0.85 MIN

WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK. NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm.

1.70 MAX

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