AD5532B

AD5532B Data Sheet, (Rev. A)

Document overview

• Manufacturer or author: Analog Devices
• PDF pages: 16

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5532B* Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode FUNCTIONAL BLOCK DIAGRAM SYNC/ CS WR CALA4–A0SCLK OFFSET_SEL AD5532B DVCC VIN DIN DOUT ADDRESS INPUT REGISTER AVCC REF IN REF OUT OFFS IN INTERFACE CONTROL LOGIC OFFS OUT VOUT 31 VOUT 0 TRACK/RESET BUSY DAC GND AGND DGND SER / PAR VDD VSS DAC DAC ADC MUX DAC MODE 14-BIT BUS

FEATURES

High Integration: 32-Channel DAC in 12 mm /H11547 12 mm CSPBGA Guaranteed Monotonic to 14 Bits Infinite Sample-and-Hold Capability to /H115500.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error /H115502.5 mV Adjustable Voltage Output Range Readback Capability DSP/Microcontroller Compatible Serial Interface Output Impedance 0.5 /H9024 Output Voltage Span 10 V Temperature Range –40 /H11543C to +85 /H11543C

APPLICATIONS

Industrial Control Systems Data Acquisition Low Cost I/O GENERAL DESCRIPTION The AD5532B is a 32-channel, voltage output, 14-bit DAC with an additional precision infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial inter- face and V OUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is accomplished via address bits A0–A4. The output voltage range is deter mined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from V SS + 2 V to VDD – 2 V because of the headroom of the output amplifier. The device is operated with AVCC = +5 V ± 5%, DVCC = +2.7 V to +5.25 V, VSS = –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN. PRODUCT HIGHLIGHTS 1. 32-channel, 14-bit DAC in one package, guaranteed monotonic. 2. The AD5532B is available in a 74-lead CSPBGA with a body size of 12 mm /H11003 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of ±2.5 mV is achieved by laser-trimming on-chip resistors. *Protected by U.S. Patent No. 5,969,657.

REV. A–2– DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = OV; Output Range from V SS + 2 V to VDD – 2 V. All outputs unloaded. All specifications T MIN to TMAX, unless otherwise noted.) AD5532B–SPECIFICATIONS AD5532B-1 Parameter1 B Version2 Unit Conditions/ Comments DAC DC PERFORMANCE Resolution 14 Bits Integral Nonlinearity (INL) ±0.39 % of FSR max ±0.15% typ Differential Nonlinearity (DNL) ± 1 LSB max ±0.5 LSB typ Monotonic Offset 90/170/250 mV min/typ/max See Figure 6. Gain 3.52 typ Full-Scale Error –1/+0.5 % of FSR max ISHA DC PERFORMANCE VIN to VOUT Nonlinearity3 ±0.006 % typ After Offset and Gain Adjustment ±0.018 % max Total Unadjusted Error (TUE) ±2.5 mV typ See TPC 6. ±12 mV max Offset Error ± 1 mV typ ±10 mV max Gain 3.51/3.52/3.53 min/typ/max ISHA ANALOG INPUT (VIN) Input Voltage Range 0 to 3 V Nominal Input Range Input Lower Dead Band 70 mV max 50 mV typ. Referred to V IN. See Figure 7. Input Upper Dead Band 40 mV max 12 mV typ. Referred to V IN. See Figure 7. Input Current 1 µA max 100 nA typ. V IN acquired on one channel. Input Capacitance4 20 pF typ ANALOG INPUT (OFFS_IN) Input Current 1 µA max 100 nA typ Input Voltage Range 0/4 V min/max Output Range Restricted from VSS + 2 V to VDD – 2 V VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3.0 V typ Input Voltage Range 4 2.85/3.15 V min/max Input Current 1 µA max <1 nA typ REF_OUT Output Voltage 3 V typ Output Impedance4 280 k Ω typ Reference Temperature Coefficient 4 60 ppm/ °C typ ANALOG OUTPUTS (VOUT 0–31) Output Temperature Coefficient 4, 5 10 ppm/ °C typ DC Output Impedance4 0.5 Ω typ Output Range V SS + 2/VDD – 2 V min/max 100 µA Output Load Resistive Load4, 6 5k Ω min Capacitive Load4, 6 100 pF max Short-Circuit Current 4 7 mA typ DC Power-Supply Rejection Ratio 4 –70 dB V DD = +15 V ± 5% –70 dB V SS = /H1100215 V ± 5% DC Crosstalk4 250 µV max Outputs Loaded ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient 4, 5 10 ppm/ °C typ DC Output Impedance4 1.3 k Ω typ Output Range 50 to REF_IN – 12 mV typ Output Current 10 µA max Source Current Capacitive Load 100 pF max

REV. A –3– AD5532B AD5532B-1 Parameter1 B Version2 Unit Conditions/Comments DIGITAL INPUTS7 Input Current ±10 µA max ±5 µA typ Input Low Voltage

0.8 V max DV CC = 5 V ± 5%

0.4 V max DV CC = 3 V ± 10%

2.4 V min DV CC = 5 V ± 5%

2.0 V min DV CC = 3 V ± 10%

Input Hysteresis (SCLK and CS Only) 200 mV typ Input Capacitance 10 pF max DIGITAL OUTPUTS ( BUSY, DOUT)7 Output Low Voltage, DV CC = 5 V 0.4 V max Sinking 200 µA Output High Voltage, DV CC = 5 V 4.0 V min Sourcing 200 µA Output Low Voltage, DV CC = 3 V 0.4 V max Sinking 200 µA Output High Voltage, DV CC = 3 V 2.4 V min Sourcing 200 µA High Impedance Leakage Current ± 1 µA max D OUT Only High Impedance Output Capacitance 15 pF typ D OUT Only POWER REQUIREMENTS Power Supply Voltages VDD 8/16.5 V min/max VSS –4.75/–16.5 V min/max AVCC 4.75/5.25 V min/max DVCC 2.7/5.25 V min/max Power Supply Currents 8 IDD 15 mA max 10 mA typ. All channels full-scale. ISS 15 mA max 10 mA typ. All channels full-scale. AICC 33 mA max 26 mA typ DICC 1.5 mA max 1 mA typ Power Dissipation 8 280 mW typ V DD = +10 V, VSS = –5 V NOTES 1See Terminology section. 2B Version: Industrial temperature range –40 °C to +85°C; typical at +25 °C. 3Input range 100 mV to 2.96 V. 4Guaranteed by design and characterization, not production tested. 5AD780 as reference for the AD5532B. 6Ensure that you do not exceed T J (max). See Absolute Maximum Ratings section. 7Guaranteed by design and characterization, not production tested. 8Output unloaded. Specifications subject to change without notice.

REV. A–4– AD5532B-1 Parameter1 B Version2 Unit Conditions/Comments DAC AC CHARACTERISTICS 3 Output Voltage Settling Time 22 µs max 500 pF, 5 kΩ Load Full-Scale Change OFFS_IN Settling Time 10 µs max 500 pF, 5 k Ω Load; 0 V to 3 V Step Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry Digital Crosstalk 5 nV-s typ Analog Crosstalk 1 nV-s typ Digital Feedthrough 0.2 nV-s typ Output Noise Spectral Density @ 1 kHz 400 nV/ √Hz typ ISHA AC CHARACTERISTICS Output Voltage Settling Time 3 3 µs max Outputs Unloaded Acquisition Time 16 µs max AC Crosstalk3 5n V - s typ NOTES 1See Terminology section. 2B Version: Industrial temperature range –40 °C to +85°C; typical at +25 °C. 3Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. TIMING CHARACTERISTICS PARALLEL INTERFACE Limit at TMIN, TMAX Parameter1, 2 (B Version) Unit Conditions/Comments t1 0 ns min CS to WR Setup Time t2 0 ns min CS to WR Hold Time t3 50 ns min CS Pulsewidth Low t4 50 ns min WR Pulsewidth Low t5 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time t6 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time NOTES 1See Parallel Interface Timing Diagram. 2Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. SERIAL INTERFACE Limit at TMIN, TMAX Parameter1, 2 (B Version) Unit Conditions/Comments fCLKIN 3 14 MHz max SCLK Frequency t1 28 ns min SCLK High Pulsewidth t2 28 ns min SCLK Low Pulsewidth t3 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t4 50 ns min SYNC Low Time t5 15 ns min D IN Setup Time t6 5 ns min D IN Hold Time t7 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback 4 20 ns max SCLK Rising Edge to D OUT Valid 4 60 ns max SCLK Falling Edge to D OUT High Impedance t10 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback t11 400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write t12 5 7 ns min SCLK Falling Edge to SYNC Falling Edge for Readback NOTES 1See Serial Interface Timing Diagrams. 2Guaranteed by design and characterization, not production tested. 3In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns. 4These numbers are measured with the load circuit of Figure 2. 5SYNC should be taken low while SCLK is low for readback. Specifications subject to change without notice. AD5532B AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T MIN to TMAX, unless otherwise noted.) AC CHARACTERISTICS

REV. A AD5532B –6– ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C, unless otherwise noted.) Operating Temperature Range 74-Lead CSPBGA Package, θJA Thermal Impedance . . 41°C/W Reflow Soldering Max Continuous Load Current at T J = 70°C, NOTES

1 Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 This limit includes load power.

4 This maximum allowed continuous load current is spread over eight channels,

with channels grouped as follows: Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10 Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26 Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29 Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31 For higher junction temperatures, derate as follows: Max Continuous Load Current TJ (°C) per Group (mA) 70 1.55 90 9.025 100 6.925 110 5.175 125 3.425 135 2.55 150 1.5 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5532B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Output Output Impedance Voltage Span Package Package Model Function (Typ) (V) Description Option AD5532BBC-1 32 DACs, 32-Channel Precision ISHA 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-1* 32 DACs, 32-Channel ISHA 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-2* 32 DACs, 32-Channel ISHA 0.5 Ω 20 74-Lead CSPBGA BC-74 AD5532ABC-3* 32 DACs, 32-Channel ISHA 500 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-5* 32 DACs, 32-Channel ISHA 1 k Ω 10 74-Lead CSPBGA BC-74 AD5533ABC-1* 32-Channel ISHA Only 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5533BBC-1* 32-Channel Precision ISHA Only 0.5 Ω 10 74-Lead CSPBGA BC-74 EVAL-AD5532EB Evaluation Board *Separate Data Sheet.

REV. A AD5532B –7– PIN CONFIGURATION A B C D E F G H J K L A B C D E F G H J K L 123456789 1 0 1 1 123456789 1 0 1 1 74-Lead CSPBGA Ball Configuration CSPBGA Ball CSPBGA Ball CSPBGA Ball Number Name Number Name Number Name A1 NC * C10 AVCC1 J10 VO9 A2 A4 C11 REF_OUT J11 VO11 A3 A2 D1 VO20 K1 VO17 A4 A0 D2 DAC_GND2 K2 VO15 A5 CS/SYNC D10 AVCC2 K3 VO27 A6 DVCC D11 OFFS_OUT K4 VSS3 A7 SCLK E1 VO26 K5 VSS1 A8 OFFSET_SEL E2 VO14 K6 VSS4 A9 BUSY E10 AGND1 K7 VDD2 A10 TRACK/RESET E11 OFFS_IN K8 VO2 A11 NC * F1 VO25 K9 VO10 B1 VO16 F2 VO21 K10 VO13 B2 NC * F10 AGND2 K11 VO12 B3 A3 F11 VO6 L1 NC * B4 A1 G1 VO24 L2 VO28 B5 WR G2 VO8 L3 VO29 B6 DGND G10 VO5 L4 VO30 B7 D IN G11 VO3 L5 VDD3 B8 CAL H1 VO23 L6 VDD1 B9 SER/ PAR H2 VIN L7 VDD4 B10 DOUT H10 VO4 L8 VO31 B11 REF_IN H11 VO7 L9 VO0 C1 VO18 J1 VO22 L10 VO1 C2 DAC_GND1 J2 VO19 L11 NC * C6 NC * J6 VSS2 *NC = Not Connected

REV. A AD5532B –9– TERMINOLOGY DAC MODE Integral Nonlinearity (INL) This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale span. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ± 1 LSB maximum ensures monotonicity. Offset Offset is a measure of the output with all zeros loaded to the DAC and OFFS_IN = 0. Since each DAC is lifted off the ground by approximately 50 mV, this output will typically be: V GAIN mVOUT =× 50 Full-Scale Error This is a measure of the output error with all 1s loaded to the DAC. It is expressed as a percentage of full-scale range. It includes the offset error. See Figure 6. It is calculated as: Full Scale Error V Ideal Gain REFINOUT Full Scale- =× ()() – where Ideal Gain 3.52 for AD5532B 1=− Output Settling Time This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within ±0.39%. OFFS_IN Settling Time This is the time taken from a 0 V–3 V step change in input voltage on OFFS_IN until the output has settled to within ± 0.39%. Digital-to-Analog Glitch Impulse This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs. Analog Crosstalk This the area of the glitch transferred to the output (V OUT) of one DAC due to a full-scale change in the output (V OUT) of another DAC. The area of the glitch is expressed in nV-secs. Digital Feedthrough This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea- sured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/√Hz. Output Temperature Coefficient This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/ °C. DC Power Supply Rejection Ratio DC power supply rejection ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (V DD and VSS). It is expressed in dBs. V DD and VSS are varied ±5%. DC Crosstalk This is the change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of all other DACs. It is expressed in µV. ISHA MODE Total Unadjusted Error (TUE) This is a comprehensive specification that includes relative accuracy, gain and offset errors. It is measured by sampling a range of voltages on V IN and comparing the measured voltages on VOUT to the ideal value. It is expressed in mV. VIN to VOUT Nonlinearity This is a measure of the maximum deviation from a straight line passing through the endpoints of the V IN versus VOUT transfer function. It is expressed as a percentage of the full-scale span. Offset Error This is a measure of the output error when VIN = 70 mV. Ideally, with VIN = 70 mV: V Gain Gain V mVOUT OFFS IN=×() ( ) ×[]70 1–– _ Offset error is a measure of the difference between V OUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 7. Gain Error This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function expressed in mV. See Figure 7. It is calculated as: Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output – Offset Error where Ideal Full-Scale Output = (Gain /H11003 2.96) – [(Gain – 1) /H11003 VOFFS_IN] AC Crosstalk This is the area of the glitch that occurs on the output of one channel while another channel is acquiring. It is expressed in nV-secs. Output Settling Time This is the time taken from when BUSY goes high to when the output has settled to ±0.018%. Acquisition Time This is the time taken for the V IN input to be acquired. It is the length of time that BUSY stays low.

REV. A AD5532B –10– DAC CODE DNL ERROR – LSBs 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 2k 4k 6k 8k 10k 12k 16k 14k VREFIN = 3V VOFFS_IN = 0V TA = 25/H11543C TPC 1. Typical DNL Plot VOUT – V 3.515 6 3.520 3.525 3.530 420 – 2 –4 –6 SINK/SOURCE CURRENT – mA TA = 25/H11543C VREFIN = 3V VIN = 1V TPC 4. V OUT Source and Sink Capability VOUT ERROR – % –0.024 –0.020 –0.016 TA = 25/H11543C VREFIN = 3V VOFFS_IN = 0V –0.012 –0.008 –0.004 0.000 0.004 0.008 0.012 0.016 0.020 0.024 0.1 2.96 VIN – V TPC 7. V IN to VOUT Accuracy After Offset and Gain Adjustment (ISHA Mode) –Typical Performance Characteristics TEMPERATURE – /H11543C VOUT – V 5.370 –40 5.360 5.350 5.340 5.330 5.320 04 0 8 0 DAC LOADED TO MIDSCALE VREFIN = 3V VOFFS_IN = 0V TPC 3. V OUT vs. Temperature TOTAL UNADJUSTED ERROR /H11546 mV FREQUENCY –4 01 –3 –2 –1 2 3 4 5 6 7 8 TPC 6. TUE Distribution at 25 °C (ISHA Mode) VOUT – V FREQUENCY 5.2670 5.2676 5.2682 10k 20k 30k 40k 50k 60k 70k 63791 200 1545 TA = 25/H11543C VREFIN = 3V VIN = 1.5V VOFFS_IN = 0V TPC 9. ISHA Mode Repeatability (64 K Acquisitions) FSR – % 0.05 0.10 0.15 FREQUENCY TPC 2. INL Error Distribution at 25°C (DAC Mode) TIME BASE – 2/H9262s/DIV VOUT – V –2.0 0.0 2.0 4.0 6.0 8.0 10.0 TA = 25/H11543C VREFIN = 3V VOFFS_IN = 0.5V TPC 5. Full-Scale Settling Time 100 2/H9262s1V TA = 25/H11543C VREFIN = 3V VIN = 0 1.5V VOUT BUSY TPC 8. Acquisition Time and Output Settling Time (ISHA Mode)

offset) into an analog output voltage (V OUT0–VOUT31). loaded, the selected DAC converts the code. by the voltage on OFFS_IN pin. VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings. channel on the device itself. The offset can be set up in two ways. OUT is within maximum ratings. occur until a rising edge of TRACK. 2.96 V due to the upper dead band of 40 mV (max). Figure 8. Analog Input Circuit IN is free to change again without affecting this output value. not need to be acquired continuously while it is ramping up.

Figure 9. Typical ATE Circuit Using TRACK Input is then switched from V IN to the output of the DAC. Figure 10. Serial Interface Formats

00 I S HA Mode

01 DAC Mode

10 Acquire and Readback

11 Readback

VOUT31, offset channel or all channels). MSB is written first.

REV. A AD5532B –13– 2. DAC Mode In this standard mode, a selected DAC register is loaded serially. This requires a 24-bit write (10 bits to address the relevant DAC plus an extra 14 bits of DAC data). (See Figure 4.) MSB is written first. The user must allow 400 ns (min) between successive writes in DAC mode. 3. Acquire and Readback Mode This mode allows the user to acquire V IN and read back the data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and V IN is acquired in 16 µs (max). Following the acquisition, after the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the D OUT line in a 14-bit serial format. (See Figure 5.) The full acquisition time must elapse before the DAC register data can be clocked out. 4. Readback Mode Again, this is a readback mode but no acquisition is performed. The relevant channel is addressed (10-bit write, MSB first) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the D OUT line in a 14-bit serial format. (See Figure 5.) The user must allow 400 ns (min) between the last SCLK falling edge in the 10-bit write and the falling edge of SYNC in the 14-bit readback. The serial write and read words can be seen in Figure 10. This feature allows the user to read back the DAC register code of any of the channels. In DAC mode, this is useful in verification of write cycles. In ISHA mode, readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on V OUT. If the user requires this voltage again, the user can input the code directly to the DAC register without going through the acquisition sequence. INTERFACES SERIAL INTERFACE The SER/PAR pin is tied high to enable the serial interface and to disable the parallel interface. The serial interface is controlled by four pins as follows: SYNC, DIN, SCLK Standard 3-wire interface pins. The SYNC pin is shared with the CS function of the parallel interface. DOUT Data out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Mode Bits There are four different modes of operation as described above. Cal Bit In DAC mode, this is a test bit. When it is high it is used to load all zeros or all ones to the 32 DACs simultaneously. In ISHA mode, all 32 channels acquire V IN simultaneously when this bit is high. In ISHA mode, the acquisition time is then 45 µs (typ) and accuracy may be reduced. This bit is set low for normal operation. Offset_Sel Bit If this is set high, the offset channel is selected and Bits A4–A0 are ignored. *SPI and QSPI are trademarks of Motorola, Inc. Test Bit This must be set low for correct operation of the part. A4–A0 Bits Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB). DB13–DB0 Bits These are used to write a 14-bit word into the addressed DAC register. Clearly, this is only valid when in DAC mode. The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™, SPI™, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figures 3, 4, and 5 show the timing diagram for a serial read and write to the AD5532B. The serial interface works with both a con- tinuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct number of bits for the selected mode have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. In readback, the first rising SCLK edge after the falling edge of SYNC causes D OUT to leave its high impedance state and data is clocked out onto the D OUT line and also on subsequent SCLK rising edges. The D OUT pin goes back into a high impedance state on the falling edge of the fourteenth SCLK. Data on the D IN line is latched in on the first SCLK falling edge after the falling edge of the SYNC signal and on subsequent SCLK falling edges. During readback D IN is ignored. The serial interface will not shift data in or out until it r eceives the falling edge of the SYNC signal. PARALLEL INTERFACE (ISHA Mode Only) The SER/PAR bit must be tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by nine pins. CS Active low package select pin. This pin is shared with the SYNC function for the serial interface. WR Active low write pin. The values on the address pins are latched on a rising edge of WR. A4–A0 Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32). Offset_Sel Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is high, the offset channel is addressed. The address on A4–A0 is ignored in this case. Cal When this pin is high, all 32 channels acquire V IN simulta- neously. The acquisition time is then 45 µs (typ) and accuracy may be reduced.

09/19/02 2:30 PM_GS REV. A–16– C02709–0–9/02(A) PRINTED IN U.S.A. AD5532B The power supply lines of the AD5532B should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the D IN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). Note that it is essential to minimize noise on V IN and REFIN lines. Particularly for optimum ISHA performance, the V IN line must be kept noise-free. Depending on the noise performance of the board, a noise filtering capacitor may be required on the V IN line. If this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source that is driving V IN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double- sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process. OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 1.00 BSC

1.00 BSC

DETAIL A1.70 MAX

12.00 BSC

10.00 BSC

0.30 MIN

0.70 0.60 0.50

0.20 MAX

COMPLIANT TO JEDEC STANDARDS MO-192ABD-1

Revision History

9/02—Data Sheet changed from REV. 0 to REV. A.