AD5531BRUZ-REEL71

AD5530_07 AD | Alldatasheet

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Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters AD5530/AD5531 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

Pin-compatible 12-, 14-bit digital-to-analog converters Serial input, voltage output Maximum output voltage range of ±10 V Data readback 3-wire serial interface Clear function to a user-defined voltage Power-down function Serial data output for daisy-chaining 16-lead TSSOP

APPLICATIONS

General-purpose instrumentation FUNCTIONAL BLOCK DIAGRAM 00938-001 LDAC RBEN REFAGND SDIN POWER-DOWN CONTROL LOGIC DAC REGISTER REFIN 12-/14-BIT DACRR GND SCLK SYNC SDO R R VOUT DUTGND VDDVSS SHIFT REGISTER AD5530/AD5531 CLR PD Figure 1. GENERAL DESCRIPTION The AD5530/AD5531 are single 12- and 14-bit (respectively) serial input, voltage output digital-to-analog converters (DAC). They utilize a versatile 3-wire interface that is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data is presented to the part in a 16-bit serial word format. Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DAC register via the SDO pin. The DAC output is buffered by a gain of two amplifier and referenced to the potential at DUTGND. LDAC can be used to update the output of the DAC asynchronously. A power-down pin ( PD) allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to a user-defined voltage, the potential at DUTGND. The AD5530/AD5531 are available in 16-lead TSSOP .

Rev. B | Page 2 of 20 TABLE OF CONTENTS Daisy-Chaining Interface with Multiple AD5530s or

REVISION HISTORY

1/07—Rev. A to Rev. B 3/06—Rev. 0 to Rev. A 5/02—Revision 0: Initial Version

Rev. B | Page 3 of 20 SPECIFICATIONS VDD = 15 V ± 10%; VSS = −15 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 AD5530 AD5531 Unit Test Conditions/Comments ACCURACY Resolution 12 14 Bits Relative Accuracy ±1 ±2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Gain Error ±1 ±4 LSB typ Gain Temperature Coefficient2 0.5 0.5 ppm FSR/°C typ 10 10 ppm FSR/°C max REFERENCE INPUTS2 Reference Input Range 0 to 5 0 to 5 V min to V max Max output range ±10 V DC Input Resistance 100 100 MΩ typ Input Current ±1 ±1 μA max Per input, typically ±20 nA DUTGND INPUT2 DC Input Impedance 60 60 kΩ typ Max Input Current ±0.3 ±0.3 mA typ Input Range −4 to +4 −4 to +4 V min to V max Max output range ±10 V O/P CHARACTERISTICS2 Output Voltage Swing ±10 ±10 V max Short-Circuit Current 15 15 mA max Resistive Load 5 5 kΩ min To 0 V Capacitive Load 1200 1200 pF max To 0 V DC Output Impedance 0.5 0.5 Ω max DIGITAL I/O VINH, Input High Voltage 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current ±10 ±10 μA max Total for all pins CIN, Input Capacitance2 10 10 pF max 3 pF typical SDO VOL, Output Low Voltage 0.4 0.4 V max ISINK = 1 mA POWER REQUIREMENTS VDD/VSS +15/−15 +15/−15 V nom ±10% for specified performance Power Supply Sensitivity ΔFull Scale/ΔVDD 110 110 dB typ ΔFull Scale/ΔVSS 100 100 dB typ IDD 2 2 mA max Outputs unloaded ISS 2 2 mA max Outputs unloaded IDD in Power-Down 150 150 μA max Typically 50 μA 1 Temperature range for B Version: −40°C to +85°C. 2 Guaranteed by design, not subject to production test.

Rev. B | Page 4 of 20 VDD = 12 V ± 10%; VSS = −12 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 AD5530 AD5531 Unit Test Conditions/Comments ACCURACY Resolution 12 14 Bits Relative Accuracy ±1 ±2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Gain Error ±1 ±4 LSB typ Gain Temperature Coefficient2 0.5 0.5 ppm FSR/°C typ 10 10 ppm FSR/°C max REFERENCE INPUTS2 Reference Input Range 0 to 4.096 0 to 4.096 V min to V max Max output range ±8.192 V DC Input Resistance 100 100 MΩ typ Input Current ±1 ±1 μA max Per input, typically ±20 nA DUTGND INPUT2 DC Input Impedance 60 60 kΩ typ Max Input Current ±0.3 ±0.3 mA typ Input Range −3 to +3 −3 to +3 V min to V max Max output range ±8.192 V O/P CHARACTERISTICS2 Output Voltage Swing ±8.192 ±8.192 V max Short-Circuit Current 15 15 mA max Resistive Load 5 5 kΩ min To 0 V Capacitive Load 1200 1200 pF max To 0 V DC Output Impedance 0.5 0.5 Ω max DIGITAL I/O VINH, Input High Voltage 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current ±10 ±10 μA max Total for all pins CIN, Input Capacitance2 10 10 pF max 3 pF typical SDO VOL, Output Low Voltage 0.4 0.4 V max ISINK = 1 mA POWER REQUIREMENTS VDD/VSS +12/−12 +12/−12 V nom ±10% for specified performance Power Supply Sensitivity ΔFull Scale/ΔVDD 110 110 dB typ ΔFull Scale/ΔVSS 100 100 dB typ IDD 2 2 mA max Outputs unloaded ISS 2 2 mA max Outputs unloaded IDD in Power-Down 150 150 μA max Typically 50 μA 1 Temperature range for B Version: −40°C to +85°C. 2 Guaranteed by design, not subject to production test.

loaded with all 0s and all 1s. dependent on load conditions. Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test. Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC. 1 Guaranteed by design, not subject to production test. 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 1LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED. Figure 2. Timing Diagram for Standalone Mode

1 Guaranteed by design, not subject to production test. 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3 SDO; RPULLUP = 5 kΩ, CL = 15 pF

Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode

Rev. B | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to GND −0.3 V to +17 V VSS to GND +0.3 V to −17 V Digital Inputs to GND −0.3 V to VDD + 0.3 V SDO to GND −0.3 V to +6.5 V REFIN to REFAGND −0.3 V to +17 V REFIN to GND VSS − 0.3 V to VDD + 0.3 V ESD CAUTION REFAGND to GND VSS − 0.3 V to VDD + 0.3 V DUTGND to GND VSS − 0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ MAX) 150°C Package Power Dissipation (TJ MAX – TA)/θJA Thermal Impedance θJA TSSOP (RU-16) 150.4°C/W Lead Temperature (Soldering 10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C

Figure 4. Pin Configuration Table 7. Pin Function Descriptions 1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V. 2 REFIN This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output. register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC. 4 SDIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. 5 SYNC Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK. from the DAC register is shifted out on the SDO pin on each rising edge of SCLK. 7 SCLK Clock Input. Data is clocked into the input register on the falling edge of SCLK. 10 PD This allows the DAC to be put into a power-down state. 12 NC Do not connect anything to this pin. 13 VSS Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance. 14 DUTGND VOUT is referenced to the voltage applied to this pin. 16 VDD Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance.

Figure 17. Typical Power-Down Time

Rev. B | Page 12 of 20 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is a measure of the output error when all 0s are loaded to the DAC latch. Full-Scale Error This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF − 1 LSB. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.

The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.

5 V reference connected to the REFIN pin and REFAGND tied

operation transfers a 16-bit word to the AD5530/AD5531. clocked out on the falling edge of the serial clock with some delay. not affect the contents of the DAC register. Figure 19. AD5531 Input Shift Register Contents of the input loading circuitry is illustrated in Figure 20. matically after CLR is brought high.

1ADDITIONAL PINS OMITTED FOR CLARITY. D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. results in a bipolar output voltage ranging from −10 V to +10 V . Resistor R1 is provided (if required) for gain adjust. Figure 21. Bipolar ±10 V Operation

2 REFIN

Figure 22. Output Voltage vs. DAC Input Codes (Hex)

Rev. B | Page 16 of 20 LDAC is controlled by the PC6 port output. The DAC can be updated after each 2-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5. To read data back from the DAC register, the SDO line can be connected to MISO of the MC68HC11, with RBEN tied to another port output controlling and framing the readback data transfer.

Figure 29. 16-Lead Thin Shrink Small Outline Package (TSSOP)

Rev. B | Page 19 of 20 NOTES

Rev. B | Page 20 of 20 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00938-0-1/07(B)