AD5522

AD5522 (Rev. F)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 64

Technical content

Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs Data Sheet AD5522 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Quad parametric measurement unit (PMU) FV, FI, FN (high-Z), MV, MI functions 4 programmable current ranges (internal RSENSE) ±5 μA, ±20 μA, ±200 μA, and ±2 mA 1 programmable current range up to ±80 mA (external RSENSE)

22.5 V FV range with asymmetrical operation

Integrated 16-bit DACs provide programmable levels Gain and offset correction on chip Low capacitance outputs suited to relayless systems On-chip comparators per channel FI voltage clamps and FV current clamps Guard drive amplifier System PMU connections Programmable temperature shutdown SPI- and LVDS-compatible interfaces Compact 80-lead TQFP with exposed pad (top or bottom)

APPLICATIONS

Automated test equipment (ATE) Per-pin parametric measurement unit Continuity and leakage testing Device power supply Instrumentation Source measure unit (SMU) Precision measurement FUNCTIONAL BLOCK DIAGRAM DUTGND MEASVH[0:3] GUARD[0:3] CGALM SCLK SYNCSDISDO CPOL0/ SCLK CPOL2/ CPO0 CPOH2/ CPO1 CPOL3/ CPO2 CPOH3/ CPO3 SERIAL INTERFACE CPOH0/ SDI CPOL1/ SYNC CPOH1/ SDO SPI/ LVDS RESET BUSY CLAMP AND GUARD ALARM TEMP SENSOR POWER-ON RESET GUARDIN[0:3]/ DUTGND[0:3] DUT EXTERNAL RSENSE (CURRENTS UP TO ±80mA) EXTMEASIH[0:3] EXTMEASIL[0:3] FOH[0:3] EXTFOH[0:3] CFF[0:3] FIN CLH CLL AVSS AVDD AGND MEASOUT[0:3] DGND CPH COMPARATOR CCOMP[0:3] LOAD CPL INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) RSENSE – – ++ VREF SYS_FORCE SYS_SENSEDVCC X1 REG C REG M REG16 16 16 16-BIT FIN DAC ×5 or ×10 TMPALM AGND REFGND 16-BIT CLH DAC MEASOUT MUX AND GAIN ×1/×0.2 X1 REG C REG M REG X1 REG C REG M REG 16X1 REG C REG M REG OFFSET DAC 16-BIT OFFSET DAC TO ALL DAC OUTPUT AMPLIFIERS FORCE AMPLIFIER 16-BIT CLL DAC 16-BIT CPH DAC 16-BIT CPL DAC SW1 SW2 SW3 SW4 60Ω SW6 SW5 SW9 SW8SW10 SW11 MEASURE VOLTAGE IN-AMP MEASURE CURRENT IN-AMP TEMP SENSOR TO MEASOUT MUX SW12 X1 REG C REG M REG X2 REG X2 REG X2 REG X2 REG X2 REG AGND EN 1kΩ GUARD AMP SW13 SW14 AGND 10kΩ SW15 SW16 DUTGND VMID TO CENTER I RANGE 06197-001 AGND SW7 4kΩ 2kΩ MEASVH (Hi-Z) 4kΩ Figure 1.

Rev. F | Page 2 of 64 TABLE OF CONTENTS

Rev. F | Page 3 of 64

REVISION HISTORY

6/2018—Rev. E to Rev. F Changes to Choosing Power Supply Rails Section and Note 2, Changes to MV Transfer Function, Table 11 and Note 3, 5/2012—Rev. D to Rev. E 2/2011—Rev. C to Rev. D Changes to Measure Current, Gain Error Tempco Parameter .... 6 Changes to Force Current, Common Mode Error (Gain = 5) 5/2010—Rev. B to Rev. C Changes to Table 14 and Reducing Zero-Scale Error Section .. 38 Changes to Serial Interface Write Mode Section and BUSY E E and LOAD E E 10/2009—Rev. A to Rev. B 10/2008—Rev. 0 to Rev. A Changes to Table 15 and BUSY E E and LOAD E E Functions 7/2008—Revision 0: Initial Version

Rev. F | Page 4 of 64 GENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. Each per-pin parametric measurement unit (PPMU) channel includes five 16-bit, voltage output DACs that set the programmable input levels for the force voltage inputs, clamp inputs, and comparator inputs (high and low). Five programmable force and measure current ranges are available, ranging from ±5 µA to ±80 mA. Four of these ranges use on-chip sense resistors; one high current range up to ±80 mA is available per channel using off-chip sense resistors. Currents in excess of ±80 mA require an external ampli- fier. Low capacitance DUT connections (FOHx and EXTFOHx) ensure that the device is suited to relayless test systems. The PMU functions are controlled via a simple 3-wire serial interface compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Interface clocks of 50 MHz allow fast updating of modes. The low voltage differential signaling (LVDS) interface protocol at 83 MHz is also supported. Comparator outputs are provided per channel for device go-no-go testing and character- ization. Control registers allow the user to easily change force or measure conditions, DAC levels, and selected current ranges. The SDO (serial data output) pin allows the user to read back information for diagnostic purposes.

16 MEASVH0

Figure 2. Detailed Block Diagram

Rev. F | Page 6 of 64 SPECIFICATIONS AVDD ≥ 10 V; AVSS ≤ −5 V; |AV DD − AVSS| ≥ 20 V and ≤ 33 V; DVCC = 2.3 V to 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND = 0 V; gain (M), offset (C), and DAC offset registers at default values; TJ = 25°C to 90°C, unless otherwise noted. (FV = force voltage, FI = force current, MV = measure voltage, MI = measure current, FS = full scale, FSR = full-scale range, FSVR = full-scale voltage range, FSCR = full-scale current range.) Table 1. Parameter Min Typ1 Max Unit Test Conditions/Comments FORCE VOLTAGE FOHx Output Voltage Range2 AVSS + 4 AVDD − 4 V All current ranges from FOHx at full-scale current, includes ±1 V dropped across sense resistor EXTFOHx Output Voltage Range2 AVSS + 3 AVDD − 3 V External high current range at full-scale current, does not include ±1 V dropped across sense resistor Output Voltage Span 22.5 V Offset Error −50 +50 mV Measured at midscale code; prior to calibration Offset Error Tempco2 −10 µV/°C Standard deviation = 20 μV/°C Gain Error −0.5 +0.5 % FSR Prior to calibration Gain Error Tempco2 0.5 ppm/°C Standard deviation = 0.5 ppm/°C Linearity Error −0.01 +0.01 % FSR FSR = full-scale range (±10 V), gain and offset errors calibrated out Short-Circuit Current Limit2 −150 +150 mA ±80 mA range −10 +10 mA All other ranges Noise Spectral Density (NSD)2 320 nV/√Hz 1 kHz, at FOHx in FV mode MEASURE CURRENT Measure current = (IDUT × RSENSE × gain), amplifier gain = 5 or 10, unless otherwise noted Differential Input Voltage Range2 −1.125 +1.125 V Voltage across RSENSE; gain = 5 or 10 Output Voltage Span 22.5 V Measure current block with VREF = 5 V, MEASOUT scaling happens after Offset Error −0.5 +0.5 % FSCR V(RSENSE) = ±1 V, measured with zero current flowing Offset Error Tempco2 1 µV/°C Referred to MI input; standard deviation = 4 µV/°C Gain Error −1 +1 % FSCR Using internal current ranges −0.5 +0.5 % FSCR Measure current amplifier alone Gain Error Tempco2 −2 ppm/°C Standard deviation = 2 ppm/°C, measure current amplifier alone; internal sense resistor 25 ppm/°C Linearity Error (MEASOUTx Gain = 1) −0.015 +0.015 % FSR MI gain = 10 −0.01 +0.01 % FSR MI gain = 5 Linearity Error (MEASOUTx Gain = 0.2) −0.06 +0.06 % FSR MI gain = 10, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.11 +0.11 % FSR MI gain = 10, AVDD = 10 V, AVSS = −23 V, offset DAC = 0x0EDB7 −0.015 +0.015 % FSR MI gain = 10, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 −0.06 +0.06 % FSR MI gain = 5, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.01 +0.01 % FSR MI gain = 5, AVDD = 10 V, AVSS = −23 V, offset DAC = 0xEDB7 −0.01 +0.01 % FSR MI gain = 5, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 Common-Mode Voltage Range2 AVSS + 4 AVDD − 4 V Common-Mode Error (Gain = 5) −0.01 +0.01 % FSCR/V % of full-scale change at force output per V change in DUT voltage Common-Mode Error (Gain = 10) −0.005 +0.005 % FSCR/V % of full-scale change at force output per V change in DUT voltage Sense Resistors Sense resistors are trimmed to within 1% 200 kΩ ±5 µA range 50 kΩ ±20 µA range 5 kΩ ±200 µA range 0.5 kΩ ±2 mA range

Rev. F | Page 7 of 64 Parameter Min Typ1 Max Unit Test Conditions/Comments Measure Current Ranges2 Specified current ranges are achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 ±5 µA Set using internal sense resistor ±20 µA Set using internal sense resistor ±200 µA Set using internal sense resistor ±2 mA Set using internal sense resistor ±80 mA Set using external sense resistor; internal amplifier can drive up to ±80 mA Noise Spectral Density (NSD)2 400 nV/√Hz 1 kHz, MI amplifier only, inputs grounded FORCE CURRENT Voltage Compliance, FOHx2 AVSS + 4 AVDD − 4 V Voltage Compliance, EXTFOHx2 AVSS + 3 AVDD − 3 V Supports 64 mA sink current and 80 mA source current AVSS + 6 AVDD − 3 V Supports 80 mA sink and source current Offset Error −0.5 +0.5 % FSCR Measured at midscale code, 0 V, prior to calibration Offset Error Tempco2 5 ppm FS/°C Standard deviation = 5 ppm/°C Gain Error −1.5 +1.5 % FSCR Prior to calibration Gain Error Tempco2 −6 ppm/°C Standard deviation = 5 ppm/°C Linearity Error −0.02 +0.02 % FSCR Common-Mode Error (Gain = 5) −0.01 +0.01 % FSCR/V % of full-scale change per V change in DUT voltage Common-Mode Error (Gain = 10) −0.006 +0.006 % FSCR/V % of full-scale change per V change in DUT voltage Force Current Ranges Specified current ranges achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 V ±5 µA Set using internal sense resistor, 200 kΩ ±20 µA Set using internal sense resistor, 50 kΩ ±200 µA Set using internal sense resistor, 5 kΩ ±2 mA Set using internal sense resistor, 500 Ω ±64 ±80 mA Set using external sense resistor, internal amplifier can drive up to ±80 mA with increased compliance MEASURE VOLTAGE Measure Voltage Range2 AVSS + 4 AVDD − 4 V Offset Error −10 +10 mV Gain = 1, measured at 0 V −25 +25 mV Gain = 0.2, measured at 0 V Offset Error Tempco2 −1 µV/°C Standard deviation = 6 µV/°C Gain Error −0.25 +0.25 % FSR MEASOUTx gain = 1 −0.5 +0.5 % FSR MEASOUTx gain = 0.2 Gain Error Tempco2 1 ppm/°C Standard deviation = 4 ppm/°C Linearity Error (MEASOUTx Gain = 1) −0.01 +0.01 % FSR −0.06 +0.06 % FSR AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.1 +0.1 % FSR AVDD = −10 V, AVSS = −23 V, offset DAC = 0x3640 Noise Spectral Density (NSD)2 100 nV/√Hz 1 kHz; measure voltage amplifier only, inputs grounded OFFSET DAC Span Error ±30 mV COMPARATOR Comparator Span 22.5 V Offset Error −2 +1 +2 mV Measured directly at comparator; does not include measure block errors Offset Error Tempco2 1 µV/°C Standard deviation = 2 µV/°C Propagation Delay2 0.25 μs VOLTAGE CLAMPS Clamp Span 22.5 V Positive Clamp Accuracy 155 mV Negative Clamp Accuracy −155 mV CLL to CLH2 500 mV CLL < CLH and minimum voltage apart Recovery Time2 0.5 1.5 μs Activation Time2 1.5 3 μs

Rev. F | Page 8 of 64 Parameter Min Typ1 Max Unit Test Conditions/Comments CURRENT CLAMPS Clamp Accuracy Programmed clamp value Programmed clamp value ± 10 % FSC MI gain = 10, clamp current scales with selected range Programmed clamp value Programmed clamp value ± 20 % FSC MI gain = 5, clamp current scales with selected range CLL to CLH2 5 % of IRANGE CLL < CLH and minimum setting apart, MI gain = 10 10 % of IRANGE CLL < CLH and minimum setting apart, MI gain = 5 Recovery Time2 0.5 1.5 μs Activation Time2 1.5 3 μs FOHx, EXTFOHx, EXTMEASILx, EXTMEASIHx, CFFx PINS Pin Capacitance2 10 pF Leakage Current −3 +3 nA Individual pin on or off switch leakage, measured with ±11 V stress applied to pin, channel enabled, but tristate Leakage Current Tempco2 ±0.01 nA/°C MEASVHx PIN Pin Capacitance2 3 pF Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, channel enabled, but tristate Leakage Current Tempco2 ±0.01 nA/°C SYS_SENSE PIN SYS_SENSE connected, force amplifier inhibited Pin Capacitance2 3 pF Switch Impedance 1 1.3 kΩ Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, switch off Leakage Current Tempco2 ±0.01 nA/°C SYS_FORCE PIN SYS_FORCE connected, force amplifier inhibited Pin Capacitance2 6 pF Switch Impedance 60 80 Ω Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, switch off Leakage Current Tempco2 ±0.01 nA/°C COMBINED LEAKAGE AT DUT Includes FOHx, MEASVHx, SYS_SENSE, SYS_FORCE, EXTMEASILx, EXTMEASIHx, EXTFOHx, and CFFx, calculation of all the individual leakage contributors Leakage Current −15 +15 nA TJ = 25°C to 70°C −25 +25 nA TJ = 25°C to 90°C Leakage Current Tempco2 ±0.1 nA/°C DUTGNDx PIN Voltage Range −500 +500 mV Leakage Current −30 +30 nA MEASOUTx PIN With respect to AGND Output Voltage Span 22.5 V Software programmable output range Output Impedance 60 80 Ω Output Leakage Current −3 +3 nA With SW12 off Output Capacitance2 15 pF Maximum Load Capacitance2 0.5 μF Output Current Drive2 2 mA Short-Circuit Current −10 +10 mA Slew Rate2 2 V/μs Enable Time2 150 320 ns Closing SW12, measured from BUSY rising edge Disable Time2 400 1100 ns Opening SW12, measured from BUSY rising edge MI to MV Switching Time2 200 ns Measured from BUSY rising edge, does not include slewing or settling

Rev. F | Page 9 of 64 Parameter Min Typ1 Max Unit Test Conditions/Comments GUARDx PIN Output Voltage Span 22.5 V Output Offset −10 +10 mV Short-Circuit Current −15 +15 mA Maximum Load Capacitance2 100 nF Output Impedance 85 Ω Tristate Leakage Current2 −30 +30 nA When guard amplifier is disabled Slew Rate2 5 V/μs CLOAD = 10 pF Alarm Activation Time2 200 μs Alarm delayed to eliminate false alarms FORCE AMPLIFIER2 Slew Rate 0.4 V/μs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Gain Bandwidth 1.3 MHz CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Max Stable Load Capacitance 10,000 pF CCOMPx = 100 pF, larger CLOAD requires larger CCOMP capacitor 100 nF CCOMPx = 1 nF, larger CLOAD requires larger CCOMP capacitor FV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 40 80 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 300 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1400 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF MI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 60 100 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 462 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1902 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF FI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF MV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF DAC SPECIFICATIONS Resolution 16 Bits Output Voltage Span2 22.5 V VREF = 5 V, within a range of −16.25 V to +22.5 V Differential Nonlinearity2 −1 +1 LSB Guaranteed monotonic by design over temperature COMPARATOR DAC DYNAMIC SPECIFICATIONS2 Output Voltage Settling Time 1 µs 500 mV change to ±½ LSB Slew Rate 5.5 V/µs Digital-to-Analog Glitch Energy 20 nV-sec Glitch Impulse Peak Amplitude 10 mV REFERENCE INPUT VREF DC Input Impedance 1 100 MΩ VREF Input Current −10 +0.03 +10 µA VREF Range2 2 5 V

Rev. F | Page 10 of 64 Parameter Min Typ1 Max Unit Test Conditions/Comments DIE TEMPERATURE SENSOR Accuracy2 ±7 °C Output Voltage at 25°C 1.5 V Output Scale Factor2 4.6 mV/°C Output Voltage Range2 0 3 V INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, FV and FI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, MV and MI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk Within a Channel 0.05 mV All channels in FVMI mode, one channel at midscale, measure the current for one channel in the lowest current range for a change in comparator or clamp DAC levels for that PMU SPI INTERFACE LOGIC INPUTS input levels input levels Input Current, IINH, IINL −1 +1 µA Input Capacitance, CIN2 10 pF CMOS LOGIC OUTPUTS SDO, CPOx Output High Voltage, VOH DVCC − 0.4 V Output Low Voltage, VOL 0.4 V IOL = 500 µA Tristate Leakage Current −2 +2 µA SDO, CPOH1/SDO −1 +1 µA All other output pins Output Capacitance2 10 pF OPEN-DRAIN LOGIC OUTPUTS BUSY, TMPALM, CGALM Output Low Voltage, VOL 0.4 V IOL = 500 µA, CLOAD = 50 pF, RPULLUP = 1 kΩ Output Capacitance2 10 pF LVDS INTERFACE LOGIC INPUTS REDUCED RANGE LINK2 Input Voltage Range 875 1575 mV Input Differential Threshold −100 +100 mV External Termination Resistance 80 100 120 Ω Differential Input Voltage 100 mV LVDS INTERFACE LOGIC OUTPUTS REDUCED RANGE LINK Output Offset Voltage 1200 mV Output Differential Voltage 400 mV POWER SUPPLIES AVDD 10 28 V |AVDD − AVSS| ≤ 33 V AVSS −23 −5 V DVCC 2.3 5.25 V AIDD 26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AISS −26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AIDD 28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AISS −28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AIDD 36 mA External range, excluding load conditions AISS −36 mA External range, excluding load conditions DICC 1.5 mA Maximum Power Dissipation2 7 W Maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design

1 Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted. 2 Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted. Table 2. SPI Interface

1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 5 and Figure 6. should either be timed or should wait until BUSY returns high (see Figure 56). This is required to ensure that data is not lost or overwritten. 5 t19 is measured with the load circuit shown in Figure 4. 6 SDO output slows with lower DVCC supply and may require use of a slower SCLK. Table 3. LVDS Interface 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 4 SDO output slows with lower DVCC supply and may require use of slower SCLK.

Table 5. Thermal Resistance1 (JEDEC 4-Layer (1S2P) Board) 1 The information in this section is based on simulated thermal information. between the cooling plate and the exposed paddle.

61 EXTFOH1

62 AVSS

63 MEASOUT3

64 MEASOUT2

65 MEASOUT1

66 MEASOUT0

67 AVSS

68 SYS_FORCE

69 AGND

70 SYS_SENSE

71 REFGND

72 VREF

73 DUTGND

74 AVDD

75 SPI/LVDS

76 CGALM

77 TMPALM

78 RESET

79 AVSS

80 EXTFOH0

41 AVDD

42 CFF3

43 CCOMP3

44 EXTMEASIH3

45 EXTMEASIL3

46 FOH3

47 GUARD3

48 GUARDIN3/DUTGND3

49 MEASVH3

50 AGND

51 AGND

52 MEASVH1

53 GUARDIN1/DUTGND1

54 GUARD1

55 FOH1

56 EXTMEASIL1

57 EXTMEASIH1

58 CCOMP1

59 CFF1

60 AVDD06197-008

1. THE EXPOSED PAD IS INTERNALLY ELECTRICALLY CONNECTED TO AVSS. FOR ENHANCED THERMAL, ELECTRICAL,

TO A CORRESPONDING THERMAL LAND PADDLE ON THE PCB. Figure 8. Pin Configuration, Exposed Pad on Bottom Table 6. Pin Function Descriptions thermal land paddle on the PCB. AVDD Positive Analog Supply Voltage. amplifier when in force voltage mode. See the Compensation Capacitors section. 3 CCOMP0 Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. 4 EXTMEASIH0 Sense Input (High Sense) for High Current Range (Channel 0). 5 EXTMEASIL0 Sense Input (Low Sense) for High Current Range (Channel 0). 6 FOH0 Force Output for Internal Current Ranges (Channel 0). 7 GUARD0 Guard Output Drive for Channel 0.

8 GUARDIN0/

the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 9 MEASVH0 DUT Voltage Sense Input (High Sense) for Channel 0. AGND Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. 12 MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2.

Rev. F | Page 17 of 64 Pin No. Mnemonic Description

13 GUARDIN2/

Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 14 GUARD2 Guard Output Drive for Channel 2. 15 FOH2 Force Output for Internal Current Ranges (Channel 2). 16 EXTMEASIL2 Sense Input (Low Sense) for High Current Range (Channel 2). 17 EXTMEASIH2 Sense Input (High Sense) for High Current Range (Channel 2). 18 CCOMP2 Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. 19 CFF2 External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 21 EXTFOH2 Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 22, 39, 62, 67, 79 AVSS Negative Analog Supply Voltage. 23 BUSY Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. 24 SCLK Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 25 CPOL0/SCLK Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. 26 CPOH0/SDI Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. 27 SDI Serial Data Input for SPI or LVDS Interface. 28 SYNC Active Low Frame Synchronization Input for SPI or LVDS Interface. 29 CPOL1/SYNC Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. 30 DGND Digital Ground Reference Point. 31 CPOH1/SDO Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. 32 SDO Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. 33 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. 34 DVCC Digital Supply Voltage. 35 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 36 CPOH2/CPO1 Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface. 37 CPOL3/CPO2 Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. 38 CPOH3/CPO3 Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. 40 EXTFOH3 Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 42 CFF3 External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 43 CCOMP3 Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. 44 EXTMEASIH3 Sense Input (High Sense) for High Current Range (Channel 3). 45 EXTMEASIL3 Sense Input (Low Sense) for High Current Range (Channel 3). 46 FOH3 Force Output for Internal Current Ranges (Channel 3). 47 GUARD3 Guard Output Drive for Channel 3.

48 GUARDIN3/

Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.

Rev. F | Page 18 of 64 Pin No. Mnemonic Description 49 MEASVH3 DUT Voltage Sense Input (High Sense) for Channel 3. 52 MEASVH1 DUT Voltage Sense Input (High Sense) for Channel 1.

53 GUARDIN1/

Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 54 GUARD1 Guard Output Drive for Channel 1. 55 FOH1 Force Output for Internal Current Ranges (Channel 1). 56 EXTMEASIL1 Sense Input (Low Sense) for High Current Range (Channel 1). 57 EXTMEASIH1 Sense Input (High Sense) for High Current Range (Channel 1). 58 CCOMP1 Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. 59 CFF1 External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 61 EXTFOH1 Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 63 MEASOUT3 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. 64 MEASOUT2 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. 65 MEASOUT1 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. 66 MEASOUT0 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. 68 SYS_FORCE External Force Signal Input. This pin enables the connection of the system PMU. 70 SYS_SENSE External Sense Signal Output. This pin enables the connection of the system PMU. 71 REFGND Accurate Analog Reference Input Ground. 72 VREF Reference Input for DAC Channels (5 V for specified performance). 73 DUTGND DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. 75 SPI/LVDS Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. 76 CGALM Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control register allows the user to enable this function and to set the open-drain output as a latched output. The user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the alarm is still present. 77 TMPALM Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers. 78 RESET Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their power- on reset values. 80 EXTFOH0 Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section.

1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO AVSS.

Figure 9. Pin Configuration, Exposed Pad on Top Table 7. Pin Function Descriptions Exposed pad The exposed pad is electrically connected to AVSS. ±80 mA. For more information, see the Current Range Selection section. AVSS Negative Analog Supply Voltage. to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers.

Rev. F | Page 20 of 64 Pin No. Mnemonic Description 6 SPI/LVDS Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. 7, 21, 40, 61, 80 AVDD Positive Analog Supply Voltage. 8 DUTGND DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. 9 VREF Reference Input for DAC Channels. 5 V for specified performance. 10 REFGND Accurate Analog Reference Input Ground. 11 SYS_SENSE External Sense Signal Output. This pin enables the connection of the system PMU. 12, 30, 31, 70, 71 AGND Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. 13 SYS_FORCE External Force Signal Input. This pin enables the connection of the system PMU. 15 MEASOUT0 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. 16 MEASOUT1 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. 17 MEASOUT2 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. 18 MEASOUT3 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. 20 EXTFOH1 Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 22 CFF1 External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 23 CCOMP1 Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. 24 EXTMEASIH1 Sense Input (High Sense) for High Current Range (Channel 1). 25 EXTMEASIL1 Sense Input (Low Sense) for High Current Range (Channel 1). 26 FOH1 Force Output for Internal Current Ranges (Channel 1). 27 GUARD1 Guard Output Drive for Channel 1.

28 GUARDIN1/

Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 29 MEASVH1 DUT Voltage Sense Input (High Sense) for Channel 1. 32 MEASVH3 DUT Voltage Sense Input (High Sense) for Channel 3.

33 GUARDIN3/

Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 34 GUARD3 Guard Output Drive for Channel 3. 35 FOH3 Force Output for Internal Current Ranges (Channel 3). 36 EXTMEASIL3 Sense Input (Low Sense) for High Current Range (Channel 3). 37 EXTMEASIH3 Sense Input (High Sense) for High Current Range (Channel 3). 38 CCOMP3 Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. 39 CFF3 External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 41 EXTFOH3 Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 43 CPOH3/CPO3 Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. 44 CPOL3/CPO2 Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. 45 CPOH2/CPO1 Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface.

Rev. F | Page 21 of 64 Pin No. Mnemonic Description 46 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 47 DVCC Digital Supply Voltage. 48 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. 49 SDO Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. 50 CPOH1/SDO Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. 51 DGND Digital Ground Reference Point. 52 CPOL1/SYNC Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. 53 SYNC Active Low Frame Synchronization Input for SPI or LVDS Interface. 54 SDI Serial Data Input for SPI or LVDS Interface. 55 CPOH0/SDI Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. 56 CPOL0/SCLK Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. 57 SCLK Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 58 BUSY Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. 60 EXTFOH2 Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 62 CFF2 External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 63 CCOMP2 Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. 64 EXTMEASIH2 Sense Input (High Sense) for High Current Range (Channel 2). 65 EXTMEASIL2 Sense Input (Low Sense) for High Current Range (Channel 2). 66 FOH2 Force Output for Internal Current Ranges (Channel 2). 67 GUARD2 Guard Output Drive for Channel 2.

68 GUARDIN2/

Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 69 MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2. 72 MEASVH0 DUT Voltage Sense Input (High Sense) for Channel 0.

73 GUARDIN0/

Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 74 GUARD0 Guard Output Drive for Channel 0. 75 FOH0 Force Output for Internal Current Ranges (Channel 0). 76 EXTMEASIL0 Sense Input (Low Sense) for High Current Range (Channel 0). 77 EXTMEASIH0 Sense Input (High Sense) for High Current Range (Channel 0). 78 CCOMP0 Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. 79 CFF0 External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section.

Figure 34. Shorted DUT AC Crosstalk, Victim PMU in FVMI Mode

5 DIFFERENT DEVICES

Figure 35. Temperature Sensor Voltage on MEASOUTx Figure 36. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 1 nF, Figure 37. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 1 nF, Figure 38. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 100 nF, Figure 39. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 100 nF,

Figure 46. FV Settling, 0 V to 5 V, ±200 μA Range, CLOAD = 220 pF,

Rev. F | Page 29 of 64 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in mV or % FSR. Gain Error Gain error is the difference between full-scale error and zero- scale error. It is expressed in % FSR. Gain Error = Full-Scale Error − Zero-Scale Error where: Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale. Zero-Scale Error is the difference between the actual voltage and the ideal voltage at zero scale. Linearity Error Linearity error, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. It is measured after adjusting for gain error and offset error and is expressed in % FSR. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Common-Mode (CM) Error Common-mode (CM) error is the error at the output of the amplifier due to the common-mode input voltage. It is expressed in % of FSVR / V. Leakage Current Leakage current is the current measured at an output pin when that function is off or high impedance. Pin Capacitance Pin capacitance is the capacitance measured at a pin when that function is off or high impedance. Slew Rate The slew rate is the rate of change of the output voltage expressed in V/μs. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-sec. It is measured by toggling the DAC register data between 0x7FFF and 0x8000. Digital Crosstalk Digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter. It is specified in nV-sec. AC Crosstalk AC crosstalk is defined as the glitch impulse transferred to the output of one PMU due to a change in any of the DAC registers in the package. ACPSRR ACPSRR is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.2 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR.

capacitive loads require larger compensation capacitances. Table 8. Comparator Output Function Using SPI Interface large pin count requirement of the LVDS interface. low is available via the serial interface (comparator status register). Table 9. Comparator Output Function Using LVDS Interface using the serial interface (system control register or PMU register). both are off. Similarly, set current clamps ±250 mV away from 0 A. See the DAC Levels section for more information. RSENSE is the sense resistor of the selected current range. instrumentation amplifier, either 5 or 10. disabled during a force operation.

that an external amplifier be used. RSENSE is the selected sense resistor. gain of 10, the maximum current range possible is ±225 μA. 12.5% to allow for error correction. irrespective of the voltage span used. electronics driver to provide high current ranges. times. See Table 26 for more information. Figure 47. Addition of High Current Amplifier for Wider Current Range (>±80 mA)

The measure current amplifier has two gain settings, 5 and 10. these examples, the offset DAC is at its default value of 0xA492. overrange of ±12.5% to allow for error correction). (including overrange of ±12.5% to allow for error correction). overrange of ±12.5% to allow for error correction). Table 13). See the block diagram in Figure 48. Figure 48. Measure Block and VMID Influence

DAC centers that range about some chosen point. VDUTGND is the voltage range anticipated at DUTGND. RCABLE is the cable/path resistance. ILOAD is the maximum load current. and includes some overrange to allow for offset correction. channel can be made high impedance via the serial interface. VREF and offset DAC setting). a DUTGND input for each channel. is SW13b (GUARDIN) and SW14b (shared DUTGND). Table 10. MEASOUTx Output Ranges for GAIN1 = 0, MEASOUT Gain = 1 1 VREF = 5 V unless otherwise noted. 2 VMID = 3.5 × VREF × ((42,130 − OFFSET_DAC_CODE)/216), see VMID Voltage section for more information.

Table 11. MEASOUTx Output Ranges for GAIN1 = 1, MEASOUT Gain = 0.2 1 VREF = 5 V unless otherwise noted. 2 The offset DAC setting has no effect on the output voltage range. 3 VMIN = 3.5 × VREF × (OFFSET_DAC_CODE/216), see VMID Voltage section for more information. pin is no longer connected to the input of the guard amplifier. connected internally to MEASVHx (SW13a). Figure 49. Using the DUTGND per Channel Feature amplifiers decreases power consumption by 400 μA per channel. requirements of the end application (see Figure 49). interface (system control register). switch connecting the CFF capacitor is automatically closed. CCOMPx should typically be <50 Ω. have on resistances of less than 50 Ω. or ADG1209 family of multiplexers meet these requirements. of capacitor must take this into account. Table 12. Suggested Compensation Capacitor Selection

connections be made individually to each PMU channel. Figure 50. SYS_FORCE and SYS_SENSE Connections to FOHx and MEASVHx Pins

and one each for the comparator high and comparator low levels. being fed into the output amplifier. VREF is the reference voltage and is in the range of 2 V to 5 V . channels) that allows for adjustment of the voltage range. the offset DAC on the other DACs in the device. Table 13. Relationship of Offset DAC to Other DACs foot room and sense resistor voltage drop (±4 V). within a voltage span of 22.5 V. code, regardless of the offset DAC setting. required for a given reference and output voltage range. brated DAC data is then stored in the X2 register. X2 is the data-word loaded to the resistor-string DAC. X1 is the 16-bit data-word written to the DAC input register. register is 15 bits (D15 to D1, the LSB is a don’t care). C is the code in the offset register (default code = 215). n is the DAC resolution (n = 16).

Table 14. References Suggested For Use with AD55221 1 Subset of the possible references suitable for use with the AD5522. Visit www.analog.com for more options.

1. Identify the nominal range required.
2. Identify the maximum offset span and the maximum gain

required on the full output signal range.

1. Calculate the new maximum output range, including the

expected maximum gain and offset errors.

1. Choose the new required VOUTMAX and VOUTMIN, keeping

AVDD and AVSS must provide sufficient headroom.

1. Calculate the value of VREF as follows:

• Use a resistor divider to divide down a convenient, higher reference level to the required level.
• Select a convenient reference level above VREF and modify the gain and offset registers to digitally downsize the reference. In this way, the user can use almost any convenient refer- ence level.
• Use a combination of these two approaches. In this case, the optimum reference is a 2.5 V reference; the user can use the M and C registers and the offset DAC to achieve the required −2 V to +8 V range. Change the I SENSE amplifier gain to 5 to ensure a full-scale current range of the specified values (see the Current Range Selection section). This gain also allows opti- mization of power supplies and minimizes power consumption within the device. It is important to bear in mind when choosing a reference value that values other than 5 V (MI gain = 10) and 2.5 V (MI gain = 5) result in current ranges other than those specified. See the Measure Current Gains section for more details. CALIBRATION Calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the M and C registers of the individual DACs. In some cases (for example, FI mode), the calibration constants, particularly those for gains, may be range dependent. Reducing Zero-Scale Error Zero-scale error can be reduced as follows: 1. Set the output to the lowest possible value. 2. Measure the actual output voltage and compare it to the required value. This gives the zero-scale error. 3. Calculate the number of LSBs equivalent to the zero-scale error and add/subtract this number to the default value of the C register. Reducing Gain Error Gain error can be reduced as follows: 1. Measure the zero-scale error. 2. Set the output to the highest possible value. 3. Measure the actual output voltage and compare it to the required value. This is the gain error. 4. Calculate the number of LSBs equivalent to the gain error and subtract this number from the default value of the M register. Note that only positive gain error can be reduced.

Rev. F | Page 39 of 64 Calibration Example Nominal offset coefficient = 32,768 Nominal gain coefficient = 65,535 For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration: 65,535 × 0.995 = 65,207 Therefore, load Code 1111 1110 1011 0111 to the M register. Offset error (100 mV) calibration: LSB size = 10.25/65,535 = 156 µV Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs Therefore, load Code 0111 1101 0111 1111 to the C register. ADDITIONAL CALIBRATION The techniques described in the Calibration section are usually sufficient to reduce the zero-scale and gain errors. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (C) register can only be used to reduce the offset caused by negative zero-scale error. A positive offset cannot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a negative gain error, the gain (M) register cannot be used to increase the gain to compensate for the error. These limitations can be overcome by increasing the reference value. SYSTEM LEVEL CALIBRATION There are many ways to calibrate the device on power-on. Following is an example of how to calibrate the FIN DAC of the device without a DUT or DUT board connected. The calibration procedure for the force and measure circuitry is as follows: 1. Calibrate the force voltage (2 points). In FV mode, write zero scale to the FIN DAC. Connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and close the internal force/sense switch (SW7). Using the system PMU, measure the error between the voltage at FOHx/MEASVHx and the desired value. Similarly, load full scale to the FIN DAC and measure the error between the voltage at FOHx/MEASVHx and the desired value. Calculate the M and C values. Load these values to the appropriate M and C registers of the FIN DAC. 2. Calibrate the measure voltage (2 points). Connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and close the internal force/sense switch (SW7). Force voltage on FOHx via SYS_FORCE and measure the voltage at MEASOUTx. The difference is the error between the actual forced voltage and the voltage at MEASOUTx. 3. Calibrate the force current (2 points). In FI mode, write zero scale to the FIN DAC. Connect SYS_FORCE to an external ammeter and to the FOHx pin. Measure the error between the ammeter reading and the MEASOUTx reading. Repeat this step with full scale loaded to the FIN DAC. Calculate the M and C values. 4. Calibrate the measure current (2 points). In FI mode, write zero scale to the FIN DAC. Connect SYS_FORCE to an external ammeter and to the FOHx pin. Measure the error between the ammeter reading and the MEASOUTx reading. Repeat this step with full scale loaded to the FIN DAC. 5. Repeat this procedure for all four channels. Similarly, calibrate the comparator and clamp DACs, and load the appropriate gain and offset registers. Calibrating these DACs requires some successive approximation to find where the comparator trips or the clamps engage.

negative feedback to the forcing amplifier (see Figure 54). Figure 54. Forcing Voltage, Measuring Current

voltage measured across the DUT (see Figure 55). RSENSE is the selected sense resistor. gain of 10, the maximum current range possible is ±225 μA. 12.5% to allow for error correction. Figure 55. Forcing Current, Measuring Voltage

is being written to, that is, on the falling edge of SYNC. held low. It is controlled by four pins, as described in Table 15. Table 15. Pins That Control the SPI Interface ential operation, as described in Table 16. Table 16. Pins That Control the LVDS Interface all registers except the DAC registers. clock in 29 bits of data before SYNC is taken high again. RESET is brought high again and the initialization is complete. on reset functions the same way as RESET. goes low and stays low until the command completes. that the user writes new data to the corresponding X1 register. or PMU modes are updated immediately after BUSY goes high. low, thus delaying the effect of LOAD going low.

calculation, data may be lost. Table 17. BUSY Pulse Widths 1 BUSY pulse width = ((number of channels + 1) × 650 ns) + 350 ns. 2 Refer to Table 18 for details of PMU register effect on BUSY pulse width. edge is detected on the RESET pin. Figure 56. Multiple Writes to DAC X1 Registers Table 18. BUSY Pulse Widths for PMU Register Updates

21 CH EN 270 ns

12 FIN 270 ns

11 SFO 270 ns

10 SS0 270 ns

9 CL 270 ns

8 CPOLH 270 ns

6 Clear 270 ns

completion of the first write operation. Figure 57. Multiple Single-Channel Writes Engaging the Calibration Engine of DAC registers and the PMU register. Table 19. Mode Bits control, or DAC register, as determined by the address bits. registers, in addition to reading from all the registers (see Table 20). device, do not use reserved commands.

All codes not explicitly referenced in this table are reserved and should not be used (see Table 29). Table 20. Read and Write Functions of the AD5522

Table 21. System Control Register Bits—Bit B28 to Bit B15 Table 22. System Control Register Bits—Bit B14 to Bit B0 1 Bit B1 and Bit B0 are unused data bits. Table 23. System Control Register Functions 27 PMU3 Set Bit PMU3 to Bit PMU0 to 0 to address the system control register.

26 PMU2

25 PMU1

24 PMU0

23 MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register.

22 MODE0

register is available in the readback word from either the PMU register or the system control register.

20 CL2

19 CL1

18 CL0

status register is available in the readback word from either the PMU register or the system control register.

16 CPOLH2

15 CPOLH1

14 CPOLH0

output individually, enabling busing of comparator outputs. disconnected from this pin and instead are connected directly to the MEASVHx line by an internal connection. The default power-on condition is GUARDINx.

10 CLAMP ALM

closes SW15, allowing the user to connect another 10 kΩ resistor between DUTGNDx and AGND. guard function is not in use, disabling it saves power (typically 400 μA per channel).

Rev. F | Page 47 of 64 Bit Bit Name Description 7 GAIN1 MEASOUTx output range. The MEASOUTx range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is ±11.25 V with the default offset DAC setting, but changes for other offset DAC settings when GAIN1 = 0. Therefore, the MEASOUTx range can be an asymmetrical bipolar voltage range. GAIN1 = 1 enables a unipolar output voltage range, which allows the use of asymmetrical supplies or a smaller input range ADC. See Table 10 and Table 11 for more details.

6 GAIN0

Output Voltage Range for VREF = 5 V, Offset DAC = 0xA492 GAIN1 = 0, MEASOUT Gain = 1 GAIN1 = 1, MEASOUT Gain = 0.2 MV 5 or 10 ±VDUT (up to ±11.25 V) 0 V to 4.5 V MI (GAIN0 = 0) 10 ±IDUT × RRSENSE × 10 + VMID (up to ±11.25 V) 0 V to 4.5 V MI (GAIN0 = 1) 5 ±IDUT × RRSENSE × 5 + VMID (up to ±5.625 V) 0 V to 2.25 V 5 TMP ENABLE Thermal shutdown feature. To disable the thermal shutdown feature, set the TMP ENABLE bit to 0 (thermal shutdown is enabled by default). 4 TMP1 The TMP1 and TMP0 bits allow the user to program the temperature that triggers thermal shutdown.

3 TMP0

TMP ENABLE TMP1 TMP0 Action 0 X X Thermal shutdown disabled. 1 X X Thermal shutdown enabled. 1 0 0 Shutdown at junction temperature of 130°C (power-on default). 1 0 1 Shutdown at junction temperature of 120°C. 1 1 0 Shutdown at junction temperature of 110°C. 1 1 1 Shutdown at junction temperature of 100°C. 2 Latched Configure the open-drain pin (CGALM) as a latched or unlatched output pin. When high, this bit configures the CGALM alarm output as a latched output, allowing it to drive a controller I/O without needing to poll the line constantly. The power-on default for this pin is unlatched. 1 0 Unused bits. Set to 0. 0 (LSB) 0

Table 24. PMU Register Bits—Bit B28 to Bit B15 Table 25. PMU Register Bits—Bit B14 to Bit B0 1 Bit B5 to Bit B0 are unused data bits. Table 26. PMU Register Functions of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. and the comparators are not affected by this bit. 20 FORCE1 The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits). are calibrated, stored in the X2 register, and loaded directly to the DAC outputs.

19 FORCE0

0 0 FV and current clamp (if clamp is enabled). 0 1 FI and voltage clamp (if clamp is enabled). 1 0 High-Z FOHx voltage (preload FIN DAC and clamp DAC). 1 1 High-Z FOHx current (preload FIN DAC and clamp DAC).

18 Reserved 0

15 C0 C2 C1 C0 Selected Current Range

0 1 0 ±200 µA current range. 0 1 1 ±2 mA current range (default). 1 0 0 ±external current range. 1 0 1 Disable the always on mode for the external current range buffer1. 1 1 0 Enable the always on mode for the external current range buffer2.

Rev. F | Page 49 of 64 Bit Bit Name Description 14 MEAS1 The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled, connected to the temperature sensor, or enabled for measurement of current or voltage. 13 MEAS0 MEAS1 MEAS0 Action 0 0 MEASOUTx is connected to ISENSE 0 1 MEASOUTx is connected to VSENSE 1 0 MEASOUTx is connected to the temperature sensor 1 1 MEASOUTx is high-Z (SW12 open) 12 FIN This bit sets the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. 11 SF0 The SF0 and SS0 bits specify the switching of system force and sense lines to the force and sense paths at the DUT. The channel to which the system force and system sense lines are connected is set by the PMU3 to PMU0 bits. For correct operation, only one PMU channel should be connected to the SYS_FORCE and SYS_SENSE paths at any one time.

10 SS0

0 0 SYS_FORCE and SYS_SENSE are high-Z for the selected channel 0 1 SYS_FORCE is high-Z and SYS_SENSE is connected to MEASVHx for the selected channels 1 0 SYS_FORCE is connected to FOHx and SYS_SENSE is high-Z for the selected channel 1 1 SYS_FORCE is connected to FOHx and SYS_SENSE is connected to MEASVHx for the selected channel 9 CL Per-PMU current or voltage clamp enable bit. A logic high enables the clamp function for the selected PMU. The clamp enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the clamp enable function on a per-channel basis, the data that was most recently written to the clamp register is available in the readback word from either the PMU register or the system control register. 8 CPOLH Comparator output enable bit. By default, the comparator outputs are high-Z on power-on. A logic high enables the comparator output for the selected PMU. The comparator function CPBIASEN (Bit 13 in the system control register), must be enabled. The comparator output enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the PMU register or the system control register.

7 Compare

A logic high selects the compare voltage function; a logic low selects the compare current function. 6 Clear To clear or reset a latched alarm bit and pin (temperature, guard, or clamp), write a 1 to this bit. This bit applies to latched alarm conditions (clamp and guard) on all four PMU channels. 5 Unused Unused bits. Set to 0. 0 (LSB) 1 Writing 101 in Bit 17 to Bit 15 disables the always on mode for the external current range buffer. Use with FV mode (FORCE1 = FORCE0 = 0) only. To complete the disabling of the always on mode, the PMU channel is placed into high-Z mode and the external current range buffer is returned to its default operation (off). 2 Writing 110 in Bit 17 to Bit 15 places the external current range buffer into always on mode. In this mode, the buffer is always active with no regard to the selected current range. The always on mode is intended for use where an external high current stage is being used for a current drive in excess of ±80 mA; having the internal stage always on should help to eliminate timing concerns when transitioning between this current range and other ranges. When first enabling the always on mode, use it in conjunction with FV mode (FORCE1 = FORCE0 = 0); the device now enables the external current range buffer. The 110 code also places the device into high-Z mode (necessary to complete the enabling function). To return to an FV or FI operating mode, select the appropriate mode and current range. The external range sense resistor is connected to an MI circuit only when the external current range address is selected (C2 to C0 are set to 100). The default operation at power-on is disabled (or off).

particular DAC for any combination of PMU channels. Table 27. DAC Register Bits Table 28. DAC Register Functions 23 MODE1 The MODE1 and MODE0 bits allow addressing of the DAC gain (M), offset (C), or input (X1) register.

22 MODE0 MODE1 MODE0 Action

21 A5 DAC address bits. The A5 to A3 bits select the register set that is addressed. See the DAC Addressing section. 18 A2 DAC address bits. The A2 to A0 bits select the DAC that is addressed. See the DAC Addressing section. 16 DAC data bits for X1 and C registers. M register is 15 bits wide, D15 to D1.

there are only two sets of X1, M, and C registers. (no internal calculation occurs on M or C updates). Note that CLL is clamp level low and CLH is clamp level high.

• When forcing a voltage, the current clamps are engaged; therefore, both the CLL current ranges register set and the CLH current ranges register set are loaded to the clamp DACs.
• When forcing a current, the voltage clamps are engaged; therefore, both the CLL voltage range register set and the CLH voltage range register set are loaded to the clamp DACs. All codes not explicitly referenced Table 29 are reserved and should not be used.

Table 29. DAC Register Addressing

Rev. F | Page 52 of 64 A5 A4 A3 A2 A1 A0 MODE1 MODE0 Register Set Addressed Register 1 0 0 0 0 1 0 1 ±20 µA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 0 1 0 0 1 ±200 µA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 0 1 1 0 1 ±2 mA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 1 0 0 0 1 ±external current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 1 0 1 0 1 Voltage range CPL M 1 0 CPL C 1 1 CPL X1 1 0 1 0 0 0 0 1 ±5 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 0 1 0 1 ±20 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 1 0 0 1 ±200 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 1 1 0 1 ±2 mA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 1 0 0 0 1 ±external current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 1 0 1 0 1 Voltage range CPH M 1 0 CPH C 1 1 CPH X1 1 CLL should be within the range of 0x0000 to 0x7FFF. 2 CLH should be within the range of 0x8000 to 0xFFFF.

0xFFFFFF; thus, no change is made to any register in the device. back data is MSB data available on SDO, followed by 00000. Table 30. Read Functions of the AD5522

The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31. Table 31. System Control Register Readback 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 21 CL3 Read back the status of the individual current clamp enable bits. is available in the readback word. 17 CPOLH3 Read back information about the status of the comparator output enable bits. 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. or the PMU register is available in the readback word. 13 CPBIASEN This readback bit indicates the status of the comparator enable function. 1 = comparator function is enabled. 0 = comparator function is disabled. 12 DUTGND/CH DUTGND per channel enable. 1 = DUTGND per channel is enabled. 0 = individual guard inputs are available per channel. 11 GUARD ALM These bits provide information about which of these alarm bits trigger the CGALM pin. 1 = guard/clamp alarm is enabled. 0 = guard/clamp alarm is disabled. between DUTGND and AGND. If this bit is low, SW7 is open. 8 Guard EN Read back the status of the guard amplifiers. If this bit is high, the amplifiers are enabled. 7 GAIN1 Status of the selected MEASOUTx output range. See Table 10 and Table 11. 5 TMP ENABLE Read back the status of the thermal shutdown function.

4 TMP1 Bits[5:3] Action

3 TMP0 0XX Thermal shutdown disabled. 100 Thermal shutdown enabled at junction temperature of 130°C (power-on default). 101 Thermal shutdown enabled at junction temperature of 120°C. 110 Thermal shutdown enabled at junction temperature of 110°C. 111 Thermal shutdown enabled at junction temperature of 100°C. 1XX Thermal shutdown enabled. 2 Latched This bit indicates the status of the open-drain alarm outputs, TMPALM and CGALM. 1 = open-drain alarm outputs are latched. 0 = open-drain alarm outputs are unlatched.

1 Unused

Table 32. PMU Register Readback 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to access the selected PMU register. 21 CH EN Channel enable. If this bit is high, the selected channel is enabled; if this bit is low, the channel is disabled. 20 FORCE1 These bits indicate which force mode the selected channel is in. 00 = FV and current clamp (if clamp is enabled). 01 = FI and voltage clamp (if clamp is enabled). 14 MEAS1 These bits indicate which measure mode is selected: voltage, current, temperature sensor, or high-Z. 00 = MEASOUTx is connected to ISENSE. 01 = MEASOUTx is connected to VSENSE. 10 = MEASOUTx is connected to the temperature sensor. 11 = MEASOUTx is high-Z (SW12 open).

13 MEAS0

12 FIN This bit shows the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. 9 CL Read back the status of the individual current clamp enable bits. 1 = clamp is enabled on this channel. 0 = clamp is disabled on this channel. PMU register is available in the readback word. 8 CPOLH Read back the status of the comparator output enable bit. 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. PMU register is available in the readback word. 7 Compare V/I 1 = compare voltage function is enabled on the selected channel. 0 = compare current function is enabled on the selected channel. level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register.

5 TMPALM

of the four PMU readback registers. Table 33. Comparator Status Register (Read-Only)

22 MODE0 1

21 CPOL0 Comparator output conditions per channe l corresponding to the comparator output pins. 20 CPOH0 1 = PMU comparator output is high. 19 CPOL1 0 = PMU comparator output is low.

18 CPOH1

17 CPOL2

16 CPOH2

15 CPOL3

14 CPOH3

Table 34. Alarm Status Register Readback 1 to the clear bit (Bit 6) in the PMU register.

20 TMPALM

17 LG1

15 LG2

13 LG3

9 LC1

7 LC2

5 LC3

The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits. Table 35. DAC Register Readback 23 (MSB) MODE1 The MODE1 and MODE0 bits indicate the type of DAC register (X1, M, or C) that is read. 10 = DAC offset (C) register. 11 = DAC input data (X1) register. 21 to 16 A5 to A0 Address bits indicating the DAC register that is read (see Table 29). 15 to 0 (LSB) D15 to D0 Contents of the addressed DAC register (X1, M, or C).

the DAC X1 registers at power-on are listed in Table 36. the system control register are shown in Table 37 and Table 38.

1. Configure the device by writing to the system control

register to set up different functions as required.

1. Calibrate the device to trim out errors, and load the

registers. Load codes to each DAC input (X1) register. stores it, ready for the PMU address to call it.

1. Load the required PMU channel with the required force

with the appropriate stored X2 value.

1. Because the voltage and current ranges have individual

correct X2 register, but this value is not loaded to the DAC. Table 36. Default Contents of DAC Registers at Power-On Table 37. Power-On Default for System Control Register

20 CL2 0

19 CL1 0

18 CL0 0

17 CPOLH3 0

16 CPOLH2 0

15 CPOLH1 0

14 CPOLH0 0

13 CPBIASEN 0

12 DUTGND/CH 0

11 Guard ALM 0

10 Clamp ALM 0

9 INT10K 0

8 Guard EN 0

7 GAIN1 0

6 GAIN0 0

5 TMP enable 1

4 TMP1 0

3 TMP0 0

2 Latched 0

1 Unused data bit 0

Table 38. Power-On Default for PMU Register

20 FORCE1 0

19 FORCE0 0

17 C2 0

16 C1 1

15 C0 1

14 MEAS1 1

13 MEAS0 1

12 FIN 0

11 SF0 0

10 SS0 0

9 CL 0

8 CPOLH 0

7 Compare V/I 0

6 LTMPALM 1

5 TMPALM 1

4 Unused data bit 0

3 Unused data bit 0

2 Unused data bit 0

There are different ways of handling a mode change.

1. Load any DAC X1 values that require changes. Remember
2. Change to the new PMU mode (FI or FV). This action

loads the DAC register with the stored X2 data.

1. In the PMU register (Bit 20 and Bit 19), enable the high-Z
2. Load any DAC X1 values that require changes. Remember
3. When the high-Z (voltage or current) mode is used, the
4. Change to the new PMU mode (FI or FV). This action

loads the new switch conditions to the PMU circuitry. minimized when changing current or voltage mode. Figure 58. External Components Required for Use with the AD5522

Table 39. ADCs and ADC Drivers Suggested For Use with AD55221

5 V, Unipolar 10 V,

1 Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options. 3 Do not allow the MEASOUTx output range to exceed the analog input (AIN) range of the ADC. connection, the connection should be made at one point only. Establish the star ground point as close as possible to the device. supply be decoupled only once. ence inputs. It is essential to minimize noise on all VREF lines. package during the assembly process. to the negative supply, AVSS. ground planes before the positive or negative supplies are applied. This is the only power sequencing requirement for this device. integrated solution for a number of these levels.

Figure 59. Typical Applications Circuit Using the AD5522 as a Per-Pin Parametric Unit

0.50 BSC

0.08 MAX

Figure 60. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Figure 61. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. F | Page 63 of 64 ORDERING GUIDE Model1 Temperature Range (TJ) Package Description Package Option AD5522JSVDZ 25°C to 90°C 80-Lead TQFP_EP with Exposed Pad on Bottom SV-80-3 AD5522JSVUZ 25°C to 90°C 80-Lead TQFP_EP with Exposed Pad on Top SV-80-2 AD5522JSVUZ-RL 0°C to 70°C 80-Lead TQFP_EP with Exposed Pad on Top SV-80-2 EVAL-AD5522EBDZ Evaluation Board with Exposed Pad on Bottom EVAL-AD5522EBUZ Evaluation Board with Exposed Pad on Top 1 Z = RoHS Compliant Part.

Rev. F | Page 64 of 64 NOTES ©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06197-0-6/18(F)