AD5520JSTZ AD | Alldatasheet
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Measurement Unit/Source Measure Unit AD5520 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
FIMV, FVMI, FVMV, FIMI, FNMV Force/measure voltage range ±11 V 4 user programmable force/measure current ranges ±4 μA, ±40 μA, ±400 μA, ±4 mA (external resistors) 2 user programmable extended current ranges Up to 6 mA without external driver Higher currents with external driver Clamp circuitry and window comparators on board Guard amplifier 64-lead LQFP package
APPLICATIONS
Per pin PMU, shared pin PMU, device power supply instrumentation Source measure, parametric measurement, precision measurement GENERAL DESCRIPTION The AD5520 is a single-channel, per pin parametric measure- ment unit (PPMU) for use in semiconductor automatic test equipment. The part is also suited for use as a source measurement unit for instrumentation applications. It contains programmable modes to force a pin voltage and measure the corresponding current, or force a current and measure the voltage. The AD5520 can force/measure over a ±11 V range or user-programmable currents up to ±4 mA with its on-board force amplifier. An external amplifier is required for wider current ranges. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 is available in a 64-lead LQFP package. FUNCTIONAL BLOCK DIAGRAM CLLDETECT MEASI4H FIN BW SELECT COMPOUT2 FOH1 FOH2 FOH3 FOH0 AVEE AVCC CLH CLL REFGND MEASIOUT MEASOUT MEASVOUT G = 16 G = 1 CPH CPOH CPOL CPL MEASI5H MEASIL GUARDIN GUARD MEASVH MEASVL AGND QM5 QM4 DGND DVDD CS STANDBY COMPOUT1 COMPOUT0 COMPIN2 COMPIN1 COMPIN0 CLAMP DETECT ISENSE INST AMP VSENSE INST AMP LOGICS AC0 AC1 CLHDETECT MOE AM0 AM1 AM2 MSEL FSEL CPSEL STBCPCK AD5520 COMPARATOR G = 1 FOH MEASI3H MEASI2H MEASI1H MEASI0H 03701-001 Figure 1.
Rev. B | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
9/05—Rev. A to Rev. B 10/03—Rev. 0 to Rev. A 9/03—Revision 0: Initial Version
Rev. B | Page 3 of 24 SPECIFICATIONS AVCC = +15 V ± 5%, AVEE = −15 V ± 5%, DVDD = 5 V ± 10%, AGND = 0 V , REFGND = 0 V , DGND = 0 V . All specifications 0°C to 70°C, unless otherwise noted. Table 1. Parameter Min Typ1 Max Unit Test Conditions/Comments VOLTAGE FORCE MODE Force Control Output Voltage Range ±11 V RLOAD = 10 kΩ, CLOAD = 50 pF FOH Output Impedance 70 Ω FOH0 2.5 kΩ FOH1 3 kΩ FOH2 500 Ω FOH3 60 Ω Input Offset Error ±1 ±5 mV Input Offset Error Temperature Coefficient ±10 μV/°C Gain Error 1 % Clamp Current Error2 ±1 % FS of FIN CURRENT MEASURE/FORCE Suggested values; set with external sense resistors FOH0 ±4 μA MODE0, RS = 125 kΩ FOH1 ±40 μA MODE1, RS = 12.5 kΩ FOH2 ±400 μA MODE2, RS = 12.5 kΩ FOH3 ±4 mA MODE3, RS = 125 Ω CURRENT MEASURE MODE High Sense Input Range, VMEASIxH ±11 V Linearity3 ±0.01 % FSR +11 V > VFOL > −11 V Input Bias Current ±1 ±3 nA Input Bias Current Drift1 50 pA/°C Output Offset Error ±100 mV MODE0 (±4 μA) ±100 mV MODE1 (±40 μA) ±100 mV MODE2 (±400 μA) ±100 mV MODE3 (±4 mA) Output Offset Error Temperature Coefficient ±10 μV/°C Gain Error ±0.1 ±0.35 % Gain of 16 Gain Error Temperature Coefficient4 30 ppm/°C MEASIOUT Output Load Current ±4 mA CMRR 95 dB @ DC CURRENT FORCE MODE Input Offset Error ±10 mV with MODE0, MODE1, MODE2, MODE3 Gain Error 1 % Clamp Voltage Error2 ±1 % FS of FIN VOLTAGE MEASURE MODE Differential Input Range ±11 V Low Sense Input Voltage Range ±100 mV MEASVL Linearity3 +0.005 % FSR +11 V > VMEASVH to VMEASVL > −11 V Input Offset Error ±5 ±10 mV FIN = 0 V, measured @ MEASVOUT Input Offset Error Temperature Coefficient1 ±15 μV/°C Gain Error ±0.03 ±0.15 % Gain of 1 Gain Error Temperature Coefficient4 2 ppm/°C Input Bias Current ±1 ±3 nA Input Bias Current Drift4 50 pA/°C MEASVOUT Output Load Current ±4 mA CMRR4 73 dB @ DC
Rev. B | Page 4 of 24 Parameter Min Typ1 Max Unit Test Conditions/Comments AMPLIFIER SETTLING TIME4, 5 VSENSE Amp 20 μs to 0.2% ISENSE Amp 12 μs to 0.2% LOOP SETTLING4, 5 Settling to within 0.024% of 8 V step COMPIN2 = 100 pF 450 600 μs MODE0 285 390 μs MODE1 170 240 μs MODE2, MODE3 COMPIN1 = 1000 pF 2 2.5 ms MODE0 1.8 2.4 ms MODE1, MODE2, MODE3 COMPIN0 = 3000 pF 5.75 8.7 ms MODE0, MODE1, MODE2, MODE3 SLEW RATE4, 5 50 mV/μs COMPIN2 = 100 pF 4.3 mV/μs COMPIN1 = 1000 pF 1.28 mV/μs COMPIN0 = 3000 pF COMPARATOR CPH, CPL Input Range ±11 V VCPH > VCPL Input Offset ±7 mV GUARD DRIVER Output Voltage ±11 V Output Impedance 130 Ω Capacitive load only Output Offset Voltage 400 mV Load Current4 ±4 mA Output Settling Time4 0.5 2 μs 100 pF capacitive load ANALOG REFERENCE INPUTS Force Control Input Range ±11 V Force Control Input Impedance 1 MΩ Clamp Control Input Range ±11 V VCLH > VCLL Clamp Control Input Impedance 1 MΩ Comparator Threshold Input Range ±11 V Comparator Threshold Input Impedance 1 MΩ Input Capacitance4 3 pF LEAKAGE CURRENT MEASIxx, MEASVx, MEASOUT Leakage ±3 ±20 nA ANALOG MEASUREMENT OUTPUTS Voltage Measure Output Impedance 2 Ω Current Measure Output Impedance 3 Ω Multiplexed Sense Output Impedance 1 kΩ Input Capacitance MEASIxH, MEASVH, FOHx 8 pF LOGIC INPUTS Input Current ±1 μA All digital inputs together Input Low Voltage, VINL 0.8 V Input High Voltage, VIHL 2.0 V Input Capacitance4 3 pF LOGIC OUTPUTS Output Low Voltage, VOL4 0.4 V ISINK = 2 mA Output High Voltage, VOH4 2.4 V ISOURCE = 2 mA
Rev. B | Page 5 of 24 Parameter Min Typ1 Max Unit Test Conditions/Comments POWER REQUIREMENTS AVCC 14.25 15 15.75 V for specific performance6 AVEE −14.25 −15 +15.75 V Power Supply Rejection Ratio, PSRR1 FOH −25 dB 100 kHz −16 dB 500 kHz −15 dB 1 MHz MEASOUT −55 dB 100 kHz −10 dB 500 kHz DC PSR 90 dB DVDD 5 V IAVCC 12 mA IAVEE 12 mA IDVDD 0.5 mA Digital inputs at supply rails 1 Typical values are at 25°C and nominal supply, unless otherwise noted. 2 Full-scale = 11 V. 3 Full-scale range = 22 V. 4 Guaranteed by design and characterization, but not subject to production test. 5 Force control amplifier dominates slew rate and settling time. 6 Operational with ±12 V supplies, force/measure range is reduced to ±8.5 V.
Rev. B | Page 7 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVCC to AVEE 34 V AVCC to AGND −0.3 V, +17 V AVEE to AGND +0.3 V, −17 V DVDD −0.3 V to +6 V Digital Inputs to DGND −0.3 V to DVDD + 0.3 V Analog Inputs to AGND AVCC + 0.3 V to AVEE – 0.3 V CLH to CLL −0.3 V to +34 V CPH to CPL −0.3 V to +34 V REFGND, DGND AVCC + 0.3 V to AVEE – 0.3 V Operating Temperature Range Commercial (J Version) 0°C to 70°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, (TJ max) 150°C Package Power Dissipation (TJ max – TA)/θJA Thermal Impedance θJA 47.8°C /W Lead Temperature (Soldering 10 sec) 300°C IR Reflow, Peak Temperature 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
47 MEASI5H
46 MEASI4H
45 FOH3
42 MEASI2H
43 FOH2
44 MEASI3H
48 AVEE_B
41 FOH1
40 MEASI1H
39 FOH0
37 MEASIL
36 MEASVH
35 GUARD(NC)
34 MEASVL
33 AVCC_G
38 MEASI0H
Figure 4. Pin Configuration Table 4. Pin Function Descriptions 1 CPH Upper Comparator Threshold Voltage Input, CPH > CPL. 2 CPL Lower Comparator Threshold Voltage Input, CPL < CPH. 3, 18 DVDD Digital Supply Voltage. 4 CPOH Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH. 5 CPOL Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL. 6 CPCK Logic Input. Used to initiate comparator sampling and update CPOH and CPOL. 8 CLHDETECT Logic Output. When high, indicates upper clamp active. See the Clamp Function section. 9 CLLDETECT Logic Output. When high, indicates lower clamp active. See the Clamp Function section. switch. See the High Current Ranges section. switch. See the High Current Ranges section. 12 MOE Active Low MEASOUT Enable. 13 CS Active Low Logic Input. The device is selected when this pin is low. See the Interface section. configurations. Rising edge of STB triggers sequence inputs. See the Interface section. 15 AC0 Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors. See the Force Control Amplifier section. 16 AC1 Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors. See the Force Control Amplifier section. mode. See the Current Ranges section. mode. See the Current Ranges section. 22 STANDBY Logic Input. When high, device is in standby mode of operation. See the Standby Mode section.
Rev. B | Page 9 of 24 Pin No. Mnemonic Description 23 FSEL Logic Input. Force mode select. Used to select between current or voltage force operation. See the Force Voltage or Force Current section. 24 MSEL Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT when low. 25 CPSEL Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when high. See the Comparator Function and Strobing section. 26 AVEE Most Negative Supply Voltage. 27 AVCC Most Positive Supply Voltage. 28 AGND MEASx Input Ground. 29 AVEE_G Most Negative Supply Voltage. 30 GUARD Guard Output. 31 NC No Connect. 32 GUARDIN Guard Input. 33 AVCC_G Most Positive Supply Voltage. 34 MEASVL DUT Voltage Sense Inputs (Low Sense). 35 GUARD(NC) No Connect. 36 MEASVH DUT Voltage Sense Inputs (High Sense). 37 MEASIL DUT Current Sense Inputs (Low Sense). 38 MEASI0H DUT Current Sense Inputs (High Sense). 39 FOH0 Force Control Voltage Output. 40 MEASI1H DUT Current Sense Inputs (High Sense). 41 FOH1 Force Control Voltage Output. 42 MEASI2H DUT Current Sense Inputs (High Sense). 43 FOH2 Force Control Voltage Output. 44 MEASI3H DUT Current Sense Inputs (High Sense). 45 FOH3 Force Control Voltage Output. 46 MEASI4H DUT Current Sense Inputs (High Sense). 47 MEASI5H DUT Current Sense Inputs (High Sense). 48 AVEE_B Most Negative Supply Voltage. 49 FOH External Force Driver Control Voltage Output. 50 AVCC_B Most Positive Supply Voltage. 51 COMPOUT0 Compensation Capacitor 0 Output. 52 COMPOUT1 Compensation Capacitor 1 Output. 53 COMPOUT2 Compensation Capacitor 2 Output. 54 COMPIN0 Compensation Capacitor 0 Input. 55 COMPIN1 Compensation Capacitor 1 Input. 56 COMPIN2 Compensation Capacitor 2 Input. 57, 59 REFGND Analog Input/Output Reference Ground. 58 MEASOUT Multiplexed DUT Voltage/Current Sense Output. See the Measured Parameter section. 60 MEASIOUT DUT Current Sense Output. 61 MEASVOUT DUT Voltage Sense Output. 62 FIN Force Control Voltage Input. 63 CLH Upper Clamp Voltage Input CLH > CLL. 64 CLL Lower Clamp Voltage CLL < CLH.
Rev. B | Page 13 of 24 THEORY OF OPERATION The AD5520 is a single-channel per pin parametric measure- ment unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), force voltage measure voltage (FVMV), and force nothing measure voltage (FNMV). The PPMU can force or measure a voltage from −11 V to +11 V . It can force or measure currents up to 6 mA using the internal amplifier, while the addition of an external amplifier enables higher current ranges. External resistors allow users to choose the optimum ranges for their needs. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. Also provided on the chip is clamp circuitry that flags via CLHDETECT and CLLDETECT if the voltage applied to FIN or across the DUT exceeds the voltage applied to CLL and CLH. On-chip is clamp circuitry that clamps the output of the force amplifier if the voltage at MEASIOUT and MEASVOUT exceeds CLL or CLH.
connected between the COMPOUTx and COMPINx pins. compensation capacitor is used. Table 10. AC0, AC1 Compensation Capacitor Selection voltage sense or the current sense amplifier. Table 11. Comparator Function Select required to clock the CPOH and CPOL data out. Table 12. CPCK Synchronous Logic Outputs and a short circuit occurs, the current clamps protect the DUT. Table 13. Clamp Detect Outputs Table 14. High Current Range Logic Outputs
Rev. B | Page 18 of 24 SETTLING TIME CONSIDERATIONS Fast throughput is a key requirement in automatic test equipment because it relates directly to the cost of manufac- turing the DUT; thus reducing the time required to make a measurement is of greatest importance. When taking measurements using a PMU, the limiting factor is usually the time it takes the output to settle to the required accuracy so a measurement can be taken. DUT capacitance, measurement accuracy, and the design of the PMU are the major contributors to this time. Figure 26 shows a simplified block diagram of the AD5520 PMU. In brief, the device consists of a force control amplifier, access to a number of selectable sense resistors, a voltage measure instrumentation amplifier, and a current measure instrumentation amplifier. To optimize the performance of the device, there are also nodes provided where external compensa- tion capacitors are added. As mentioned, making an accurate measurement in the fastest time while avoiding overshoots and ringing is the key requirement in any automatic test equipment (ATE) system. Doing so provides challenges, however. The external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and while one compensation capacitor value may suit one range, it may not suit other ranges. To optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account. When selecting a faster settling time, there is a trade-off. A small compensation value results in faster settling, but may incur penalties in overshoots or ringing at the DUT . Compensation capacitor selection should be optimized to ensure minimum overshoots while still giving decent settling time performance. While careful selection of the compensation capacitor is required to minimize the settling time, another factor can greatly contribute to the overall settling of the loop if the feedback loop is broken in some manner, and the force control amplifier goes to either the positive or negative rails. There is a finite amount of time required for the amplifier to recover from this condition, typically 85 μs, which adds to the settling of the loop. Ensuring that the force control amplifier never goes into saturation is the best solution. This solution can be helped by putting the device into standby mode any time the operating mode or range selection is changed. In addition, ensure that the selected output range can supply the required current needed by the DUT .
Rev. B | Page 19 of 24 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion to the power supply and the ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5520 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the PMU is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. This PMU should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply and should be located as close as possible to the package, ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR (1 μF to 10 μF) tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. It is good practice to use compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance.
Rev. B | Page 22 of 24 EVALUATION BOARD FOR THE AD5520 A full-featured evaluation kit is available for the AD5520. It includes an evaluation board with direct hookup via a 36-way Centronics connector to a PC. PC-based software to control the AD5520 is also part of the evaluation kit. The evaluation board schematic is shown in Figure 28. Note that VDD and VSS must provide sufficient headroom for the force and measure voltage range. In addition to the supply voltages for the evaluation board, it is necessary to provide the voltage levels for the clamp, comparator, and the force input pins (CLL, CLH, CPL, CPH, and FIN). SMB connections are provided for these voltage inputs. To use the evaluation board, it is also necessary to provide a DUT connected via the gold pins. Both AGND and DGND inputs are provided on the board. The AGND and DGND planes are connected at one location close to the AD5520. It is recommended not to connect AGND and DGND elsewhere in the system to avoid ground loop problems. REFGND is routed back to AGND at the power block to maintain a clean ground reference for accurate measurements. Each supply is decoupled to the relevant ground plane with 10 μF and 0.1 μF capacitors. The device supply pin is again decoupled with a 10 μF and 0.1 μF capacitor pair to the relevant ground plane. Care should be taken when replacing devices to ensure that the pins line up correctly with the PCB pads.
Figure 28. Evaluation Board Schematic
0.08 MAX
Figure 29. 64-Lead Low Profile Quad Flat Package [LQFP] registered trademarks are the property of their respective owners.