AD5516ABC-2

AD5516 AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5516* Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode FUNCTIONAL BLOCK DIAGRAM RFB0 RESET BUSY DACGND AGND DGND DCEN AD5516 DVCC AVCC VDD VSS VOUT0 RFB1 VOUT1 RFB14 VOUT14 RFB15 VOUT15 ROFFS RFB DAC VBIAS ROFFS RFB DAC ROFFS RFB DAC ROFFS RFB DAC REF_IN PD POWER-DOWN LOGIC SCLK D IN DOUT SYNC INTERFACE CONTROL LOGIC 7-BIT BUS ANALOG CALIBRATION LOOP 12-BIT BUS MODE1 MODE2

FEATURES

High Integration: 16-Channel DAC in 12 mm /H11547 12 mm LFBGA 14-Bit Resolution via Increment/Decrement Mode Guaranteed Monotonic Low Power, SPI TM, QSPITM, MICROWIRETM, and DSP- Compatible 3-Wire Serial Interface Output Impedance 0.5 /H9024 Output Voltage Range /H115502.5 V (AD5516-1) /H115505 V (AD5516-2) /H1155010 V (AD5516-3) Asynchronous Reset-Facility (via RESET Pin) Asynchronous Power-Down Facility (via PD Pin) Daisy-Chain Mode Temperature Range: –40 /H11543C to +85/H11543C

APPLICATIONS

Industrial Control Systems Data Acquisition Low Cost I/O GENERAL DESCRIPTION The AD5516 is a 16-channel, 12-bit voltage-output DAC. The selected DAC register is written to via the 3-wire serial interface. DAC selection is accomplished via address bits A3–A0. 14-bit resolution can be achieved by fine adjustment in Increment/ Decrement Mode (Mode 2). The serial interface operates at clock rates up to 20 MHz and is compatible with standard SPI, MICROWIRE, and DSP interface standards. The output volt- age range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2), and ±10 V (AD5516-3). Access to the feedback resistor in each channel is provided via R FB0 to RFB15 pins. The device is operated with AV CC = 5 V ± 5%, DVCC = 2.7 V to 5.25 V, VSS = –4.75 V to –12 V, and V DD = +4.75 V to +12 V and requires a stable 3 V reference on REF_IN. PRODUCT HIGHLIGHTS 1. Sixteen 12-bit DACs in one package, guaranteed monotonic 2. Available in a 74-lead LFBGA package with a body size of 12 mm /H11547 12 mm *Protected by U.S. Patent No. 5,969,657; other patents pending SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0–2– AD5516 Parameter1 A Version2 Unit Conditions/Comments DAC DC PERFORMANCE Resolution 12 Bits Integral Nonlinearity (INL) ±2 LSB max Mode 1 Differential Nonlinearity (DNL) –1/+1.3 LSB max ±0.5 LSB typ, Monotonic; Mode 1 Increment/Decrement Step-Size ±0.25 LSB typ Monotonic; Mode 2 Only Bipolar Zero Error ±7 LSB max Positive Full-Scale Error ±10 LSB max Negative Full-Scale Error ±10 LSB max VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3 V Input Voltage Range 3 2.875/3.125 V min/max Input Current ±1 µA max < 1 nA typ ANALOG OUTPUTS (V OUT 0–15) Output Temperature Coefficient 3, 4 10 ppm/ °C typ of FSR DC Output Impedance 3 0.5 Ω typ Output Range5 AD5516-1 ±2.5 V typ AD5516-2 ±5 V typ AD5516-3 ±10 V typ Resistive Load3, 6 5k Ω min Capacitive Load3, 6 200 pF Short-Circuit Current 3 7 mA typ DC Power-Supply Rejection Ratio 3 –85 dB typ V DD = +12 V ± 5%, VSS = –12 V ± 5% DC Crosstalk3 120 µV max DIGITAL INPUTS3 Input Current ±10 µA max ±5 µA typ Input Low Voltage 0.8 V max DV CC = 5 V ± 5%

0.4 V max DV CC = 3 V ± 10%

Input High Voltage 2.4 V min DV CC = 5 V ± 5%

2 V min DV CC = 3 V ± 10%

Input Hysteresis (SCLK and SYNC) 150 mV typ Input Capacitance 10 pF max 5 pF typ DIGITAL OUTPUTS ( BUSY, DOUT)3 Output Low Voltage, DV CC = 5 V 0.4 V max Sinking 200 µA Output High Voltage, DV CC = 5 V 4 V min Sourcing 200 µA Output Low Voltage, DV CC = 3 V 0.4 V max Sinking 200 µA Output High Voltage, DV CC = 3 V 2.4 V min Sourcing 200 µA High Impedance Leakage Current (D OUT only) ±1 µA max DCEN = 0 High Impedance Output Capacitance (D OUT only) 5 pF typ DCEN = 0 POWER REQUIREMENTS Power Supply Voltages VDD +4.75/+15.75 V min/max VSS –4.75/–15.75 V min/max AVCC 4.75/5.25 V min/max DVCC 2.7/5.25 V min/max Power Supply Currents 7 IDD 5 mA max 3.5 mA typ. All Channels Full-Scale ISS 5 mA max 3.5 mA typ. All Channels Full-Scale AICC 17 mA max 13 mA typ DICC 1.5 mA max 1 mA typ Power-Down Currents 7 IDD 2 µA max 200 nA typ ISS 3 µA max 200 nA typ AICC 2 µA max 200 nA typ DICC 2 µA max 200 nA typ Power Dissipation 7 105 mW typ V DD = +5 V, VSS = –5 V NOTES 1See Terminology section. 2A Version: Industrial temperature range –40 °C to +85 °C; typical at +25 °C. 3Guaranteed by design and characterization; not production tested. 4AD780 as reference for the AD5516. 5Output range is restricted from V SS + 2 V to V DD – 2 V. Output span varies with reference voltage and is functional down to 2 V. 6Ensure that you do not exceed T J (MAX). See Absolute Maximum Ratings section. 7Outputs unloaded. Specifications subject to change without notice. –SPECIFICATIONS 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)

–3– AC CHARACTERISTICS AD5516 = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.) Parameter1, 2 A Version3 Unit Conditions/Comments Output Voltage Settling Time (Mode 1) 4 32 /H9262s max 100 pF, 5 k Ω Load Full-Scale Change Output Voltage Settling Time (Mode 2) 4 2.5 /H9262s max 100 pF, 5 k Ω Load, 1 Code Increment Slew Rate 0.85 V/ /H9262s typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry Digital Crosstalk 5 nV-s typ Analog Crosstalk AD5516-1 10 nV-s typ Digital Feedthrough 1 nV-s typ Output Noise Spectral Density @ 1 kHz 150 nV/(Hz) 1/2 typ AD5516-1 NOTES 1See Terminology section. 2Guaranteed by design and characterization; not production tested. 3A version: Industrial temperature range –40 °C to +85 °C. 4 Timed from the end of a write sequence. Specifications subject to change without notice. Limit at TMIN, TMAX Parameter1, 2, 3 (A Version) Unit Conditions/Comments fUPDATE1 32 kHz max DAC Update Rate (Mode 1) fUPDATE2 750 kHz max DAC Update Rate (Mode 2) fCLKIN 20 MHz max SCLK Frequency t1 20 ns min SCLK High Pulsewidth t2 20 ns min SCLK Low Pulsewidth t3 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t4 5 ns min D IN Setup Time t5 5 ns min D IN Hold Time t6 0 ns min SCLK Falling Edge to SYNC Rising Edge t7 10 ns min Minimum SYNC High Time (Standalone Mode) t7MODE2 400 ns min Minimum SYNC High Time (Daisy-Chain Mode) t8MODE1 10 ns min BUSY Rising Edge to SYNC Falling Edge t9MODE2 200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode) t10 10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode) t11 4 20 ns max SCLK Rising Edge to D OUT Valid (Daisy-Chain Mode) t12 20 ns min RESET Pulsewidth NOTES 1See Timing Diagrams in Figures 1 and 2. 2Guaranteed by design and characterization; not production tested. 3All input signals are specified with tr = tf = 5 ns (10% to 90% of DV CC) and timed from a voltage level of (V IL + VIH)/2. 4This is measured with the load circuit of Figure 3. Specifications subject to change without notice. TIMING CHARACTERISTICS AGND = DGND = DACGND = 0 V. All specifications T MIN to TMAX unless otherwise noted.)

REV. 0 AD5516 –5– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C unless otherwise noted.) R 74-Lead LFBGA Package, /H9258JA Thermal Impedance . . 41 °C/W Reflow Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model Function Output Voltage Span Package Option AD5516ABC-1 16 DACs ±2.5 V 74-Lead LFBGA AD5516ABC-2 16 DACs ±5 V 74-Lead LFBGA AD5516ABC-3 16 DACs ±10 V 74-Lead LFBGA

REV. 0 AD5516 –6– PIN CONFIGURATION A B C D E F G H J K 1110987654321 TOP VIEW A B C D E F G H J K 1110987654321 LL PIN FUNCTION DESCRIPTIONS Mnemonic Function AGND (1–2) Analog GND pins AVCC (1–2) Analog supply pins. Voltage range from +4.75 V to +5.25 V. VDD (1–2) V DD supply pins. Voltage range from +4.75 V to +15.75 V. VSS (1–2) V SS supply pins. Voltage range from –4.75 V to –15.75 V. DGND Digital GND pins DVCC Digital supply pin. Voltage range from 2.7 V to 5.25 V. DACGND Reference GND supply for all 16 DACs. REF_IN Reference input voltage for all 16 DACs. The recommended value of REF_IN is 3 V. V OUT (0–15) Analog output voltages from the 16 DAC channels. RFB (0–15) Feedback resistors. For nominal output voltage range connect each R FB to its corresponding V OUT. SYNC Active low input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. SCLK Serial clock input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 20 MHz. DIN Serial data input. Data must be valid on the falling edge of SCLK. 74-LEAD LFBGA BALL CONFIGURATION LFBGA Ball LFBGA Ball LFBGA Ball LFBGA Ball LFBGA Ball Number Name Number Name Number Name Number Name Number Name NC = Not Internally Connected A1 NC A2 NC A3 RESET A4 BUSY A5 DGND A6 DV CC A7 D OUT A8 D IN A9 SYNC A10 NC A11 NC B1 NC B2 NC B3 NC B4 DCEN B5 DGND B6 DGND B7 NC B8 NC B9 SCLK B10 NC B11 REF_IN C1 V OUT0 C2 DACGND C6 NC C10 AV CC1 C11 NC D1 R FB0 D2 DACGND D10 AV CC2 D11 NC E1 V OUT1 E2 NC E10 AGND1 E11 PD F1 V OUT2 F2 R FB1 F10 AGND2 F11 R FB14 G1 R FB2 G2 R FB15 G10 V OUT14 G11 R FB13 H1 V OUT3 H2 V OUT15 H10 V OUT13 H11 V OUT12 J1 R FB3 J2 V OUT14 J6 NC J10 R FB12 J11 R FB11 K1 R FB4 K2 V OUT5 K3 R FB5 K4 NC K5 V SS2 K6 V SS1 K7 V OUT10 K8 V OUT9 K9 R FB10 K10 R FB9 K11 V OUT11 L1 NC L2 V OUT6 L3 R FB6 L4 V OUT7 L5 NC L6 V DD2 L7 V DD1 L8 R FB7 L9 V OUT8 L10 R FB8 L11 NC

REV. 0 AD5516 –7– TERMINOLOGY Integral Nonlinearity (INL) This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of –1 LSB maximum ensures monotonicity. Bipolar Zero Error Bipolar zero error is the deviation of the DAC output from the ideal It is expressed in LSBs. Positive Full-Scale Error This is the error in the DAC output voltage with all 1s loaded to the DAC. Ideally the DAC output voltage, with all 1s loaded to the DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB (AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs. Negative Full-Scale Error This is the error in the DAC output voltage with all 0s loaded to the DAC. Ideally the DAC output voltage, with all 0s loaded to the DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2), and –10 V (AD5516-3). It is expressed in LSBs. Output Temperature Coefficient This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/ °C of FSR. DC Power Supply Rejection Ratio DC power supply rejection ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (V DD and VSS). It is expressed in dBs. V DD and VSS are varied ±5%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in mV. Output Settling Time This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within ±0.5 LSB of its final value (see TPC 7). Digital-to-Analog Glitch Impulse This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs. Analog Crosstalk This is the area of the glitch transferred to the output (V OUT) of one DAC due to a full-scale change in the output (V OUT) of another DAC. The area of the glitch is expressed in nV-secs. Digital Feedthrough This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., SYNC is high. It is specified in nV-secs and measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured in nV/(Hz) 1/2. PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Function DOUT Serial data output. D OUT can be used for daisy-chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes. Data is clocked out on D OUT on the rising edge of SCLK and is valid on the falling edge of SCLK. DCEN1 Active high control input. This pin is tied high to enable daisy-chain mode. RESET2 Active low control input. This resets all DAC registers to power-on value. PD1 Active high control input. All DACs go into power-down mode when this pin is high. The DAC outputs go into a high-impedance state. BUSY Active low output. This signal tells the user that the analog calibration loop is active. It goes low during conversion. The duration of the pulse on BUSY determines the maximum DAC update rate, f UPDATE. Further writes to the AD5516 are ignored while BUSY is active. NOTES 1Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition. 2Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.

REV. 0–8– DAC CODE DNL ERROR – LSB 1.0 0.6 0.2 –0.2 –0.4 –0.6 0.8 0.4 –0.8 –1.0 1000 2000 3000 40000 REF_IN = 3V TA = 25/H11543C TPC 1. Typical DNL Plot TEMPERA TURE – /H11543C ERROR – LSB –40 –20 0 20 40 80 REF_IN = 3V BIPOLAR ZERO ERROR POSITIVE FS ERROR NEGA TIVE FS ERROR TPC 4. Bipolar Zero Error and Full-Scale Error vs. Temperature VOUT – V 3.0 1.0 –1.0 –2.0 2.0 –3.0 TIME BASE = 2.5/H9262s/DIV TA = 25/H11543C REF_IN = 3V TPC 7. Full-Scale Settling Time DAC CODE INL ERROR – LSB 1.0 0.6 0.2 –0.2 –0.4 –0.6 0.8 0.4 –0.8 –1.0 1000 2000 3000 4000 REF_IN = 3V TA = 25/H11543C TPC 2. Typical INL Plot TEMPERA TURE – /H11543C VOUT – V 0.003 –40 0.002 0.001 –0.001 –0.002 –0.003 –20 0 20 40 80 AVDD = +12V AVSS = –12V REF_IN = 3V MIDSCALE LOADED TPC 5. VOUT vs. Temperature VOUT PD TA = 25/H11543C REF_IN = 3V 5V/DIV 2V/DIV 2/H9262s/DIV TPC 8. Exiting Power-Down to Full Scale TEMPERA TURE – /H11543C ERROR – LSB 2.0 –40 1.0 –1.0 –0.5 –1.5 –2.0 –20 0 20 40 80 1.5 0.5 INL +VE DNL –VE DNL REF_IN = 3V TPC 3. Typical INL Error and DNL Error vs. Temperature CURRENT – mA VOUT – V 0.002 –4 –202 6 4 MIDSCALE REF_IN = 3V TA = 25/H11543C 0.0 –0.002 –0.004 –0.006 –0.008 –0.01 0.004 0.006 0.008 0.01 8–8 TPC 6. VOUT Source and Sink Capability BUSY –0.029 –0.031 –0.032 –0.030 –0.033 TA = 25/H11543C REF_IN = 3V CALIBRA TION TIME NEW VALUE 2.5/H9262s/DIV OLD VALUE TPC 9. Major Code Transition Glitch Impulse –Typical Performance CharacteristicsAD5516

REV. 0 –9– AD5516 VOUT – V FREQUENCY 450 350 250 150 200 100 400 300 2.48992.48962.4893 TPC 10. VOUT Repeatability; Program- ming the Same Code Multiple Times FREQUENCY – % –10 0 10 REF_IN = 3V TA = 25/H11543C LSBs TPC 12. Positive Full-Scale Error Distribution FREQUENCY – % –10 0 10 REF_IN = 3V TA = 25/H11543C LSBs TPC 13. Negative Full-Scale Error Distribution STEP SIZE ERROR – LSB 2.5 2.0 1.5 1.0 0.5 0 20 40 60 80 100 120 130 REF_IN = 3V TA = 25/H11543C TPC 14. Increment Step vs. Accuracy FREQUENCY – % –10 0 10 REF_IN = 3V TA = 25/H11543C LSBs TPC 11. Bipolar Error Distribution

Table I illustrates ideal analog output versus DAC code. The AD5516 has two modes of operation. not pulsed while BUSY is low. Mode 1 conversion takes 25 µs typ. racy varies with increment/decrement step as shown in TPC 14. The AD5516 consists of sixteen 12-bit DACs in a single package. the required DAC is addressed via the 3-wire serial interface. appropriate voltage level on an internal 14-bit resolution DAC. normal selected voltage. See TPC 10. reference to drive the AD5516. Figure 4. Mode 1 Data Format

7 INCREMENT

7 DECREMENT

Figure 5. Mode 2 Data Format

REV. 0 AD5516 –11– Daisy-Chain Mode (DCEN = 1) In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 18 clock pulses are applied, the data ripples out of the shift register and appears on the DOUT line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the D IN input on the next device in the chain, a multidevice interface is constructed. Eighteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 18N where N is the total number of devices in the chain. See the timing diagram in Figure 2. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device’s input shift register to the addressed DAC. RESET Function The RESET function on the AD5516 can be used to reset all nodes on this device to their power-on reset condition. This is implemented by applying a low-going pulse of minimum 20 ns to the RESET Pin on the device. Table III. Typical Power-ON Values Device Output Voltage AD5516-1 –0.073 V AD5516-2 –0.183 V AD5516-3 –0.391 V BUSY Output During conversion, the BUSY output is low and all SCLK pulses are ignored. At the end of a conversion, BUSY goes high indicating that the update of the addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. MICROPROCESSOR INTERFACING The AD5516 is controlled via a versatile 3-wire serial interface that is compatible with a number of microprocessors and DSPs. AD5516 to ADSP-2106x SHARC DSP Interface The ADSP-2106x SHARC DSPs are easily interfaced to the AD5516 without the need for extra logic. The AD5516 expects a t 3 (SYNC falling edge to SCLK falling edge setup time) of 15 ns min. Consult the ADSP-2106x User Manual for information on clock and frame sync frequencies for the SPORT register and contents of the TDIV, RDIV registers. The user must allow 200 ns (min) between two consecutive Mode 2 writes in standalone mode and 400 ns (min) between two consecutive Mode 2 writes in daisy-chain mode. See Figures 4 and 5 for Mode 1 and Mode 2 data formats. When MODE bits = 11, the device is in No Operation mode. This may be useful in daisy-chain applications where the user does not wish to change the settings of the DACs. Simply write 11 to the MODE bits and the following address and data bits will be ignored. SERIAL INTERFACE The AD5516 has a 3-wire interface that is compatible with SPI/ QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 18-bit words. This 18-bit word consists of two mode bits, four address bits, and 12 data bits as shown in Figure 4. The serial interface works with both a continuous and burst clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. A3–A0 Four address bits (A3 = MSB Address, A0 = LSB). These are used to address one of 16 DACs. Table II. Selected DAC A3 A2 A1 A0 Selected DAC 0 0 0 0 DAC 0 0 0 0 1 DAC 1 : ::: 1 1 1 1 DAC 15 DB11–DB0 These are used to write a 12-bit word into the addressed DAC register. Figures 1 and 2 show the timing diagram for a write cycle to the AD5516. SYNC FUNCTION In both standalone and daisy-chain modes, SYNC is an edge- triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t Standalone Mode (DCEN = 0) After SYNC goes low, serial data will be shifted into the device’s input shift register on the falling edges of SCLK for 18 clock pulses. After the falling edge of the 18th SCLK pulse, data will automatically be transferred from the input shift register to the addressed DAC. SYNC must be taken high and low again for further serial data transfer. SYNC may be taken high after the falling edge of the 18th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t 6. If SYNC is taken high before the 18th falling edge of SCLK, the data transfer will be aborted and the addressed DAC will not be updated. See the timing diagram in Figure 1.

REV. 0 AD5516 –14– OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 74-Lead LFBGA (BC-74) A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 1.00 (0.0394) BSC 1.00 (0.0394) BSC BOTTOM VIEW 10.00 (0.3937) BSC 10.00 (0.3937) BSC A1 CORNER INDEX CORNER TOP VIEW 12.00 (0.4724) BSC 12.00 (0.4724) BSC DETAIL A SEATING PLANE DETAIL A 0.63 (0.0248) BSC BALL DIAMETER 0.50 (0.0197) MIN A1 CORNER INDEX CORNER 1.70 (0.0669) MAX CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-192

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–16– C02792–0–5/02(0) PRINTED IN U.S.A.