AD5501

AD5501 (Rev. C) - OBSOLETE

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

12-Bit, High Voltage DAC with SPI Interface Data Sheet AD5501 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2009-2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Single-channel high voltage DAC 12-bit resolution Pin-selectable 30 V or 60 V output range Integrated precision reference Low power serial interface with readback capability Integrated temperature sensor alarm function Power-on reset Wide operating temperature range: −40°C to +105°C

APPLICATIONS

Programmable voltage sources High voltage LED drivers Receiver bias in optical communications GENERAL DESCRIPTION The AD5501 is a single-channel, 12-bit, serial input, digital-to- analog converter (DAC) with an on-chip high voltage output amplifier and an integrated precision reference. The DAC output voltage range is programmable via the range select pin (R_SEL). If R_SEL is held high, the DAC output range is 0 V to 30 V . If R_SEL is held low, the DAC output range is 0 V to 60 V . The on chip output amplifier allows an output swing within the range of AGND + 0.5 V to VDD − 0.5 V . The AD5501 has a high speed serial interface, which is compatible with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface standards and can handle clock speeds of up to 16.667 MHz. FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC SYNC CLR R_SEL DGND VLOGIC VDD AGND SCLK SDI SDO VOUT VFB LDAC ALARM POWER-DOWN CONTROL LOGIC PRECISION REFERENCE TEMPERATURE SENSOR 12-BIT DAC REF(+) OUTPUT BUFFER 122.36kΩ 1713kΩ RESISTOR NETWORK AD5501 07992-001 Figure 1. OBSOLETE

Rev. C | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

12/12—Rev. B to Rev. C Changes to Pin 2 Description, Table 7 and Pin 3 Description, 4/12—Rev. A to Rev. B 10/10—Rev. 0 to Rev. A 7/09—Revision 0: Initial Version OBSOLETE

to, and reading from, most internal registers. value while typically consuming only 30 μA of supply current. loads while in the power-down mode. Table 1. Related Device

Rev. C | Page 4 of 20 SPECIFICATIONS VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted. Table 2. Parameter Symbol Min Typ1 Max Unit Test Conditions/Comments ACCURACY2 Resolution 12 Bits Differential Nonlinearity DNL −1 +1 LSB Integral Nonlinearity INL

60 V Mode −1 +1 LSB VDD = 62 V

30 V Mode −2 +2 LSB VDD = 62 V

VOUT Temperature Coefficient3, 4 50 ppm/°C DAC code = half scale Offset Error VOE −65 +100 mV Offset Error Drift4 60 µV/°C Zero-Scale Error VZSE 80 mV Zero-Scale Error Drift4 50 µV/°C 60 V mode Full-Scale Error VFSE −325 +275 mV Full-Scale Error Drift4 1 mV/°C −40°C to +25°C; 60 V mode 350 µV/°C +25°C to +105°C; 60 V mode Gain Error −0.6 +0.6 % of FSR Gain Temperature Coefficient4 10 ppm of FSR/°C OUTPUT CHARACTERISTICS Output Voltage Range5 AGND + 0.5 VDD − 0.5 V Short-Circuit Current4, 6 2 mA Capacitive Load Stability4 1 V to 4 V step RL = 60 kΩ to ∞ 1 nF Load Current4 −1 +1 mA Feedback Resistance7 100 Ω DC Output Impedance4 3 Ω DC Output Leakage4 10 µA DIGITAL INPUTS Input Logic High VIH 2.0 V VLOGIC = 4.5 V to 5.5 V 1.8 V VLOGIC = 2.3 V to 3.6 V Input Logic Low VIL 0.8 V VLOGIC = 2.3 V to 5.5 V Input Current IIL ±1 µA Input Capacitance4 IIC 5 pF DIGITAL OUTPUTS Output High Voltage VOH VLOGIC − 0.4 V V ISOURCE = 200 µA Output Low Voltage VOL DGND + 0.4 V V ISINK = 200 µA Three-State Leakage Current SDI, SDO, SCLK, LDAC, CLR, R_SEL Pins −1 +1 µA ALARM Pin −10 +10 µA Output Capacitance4 5 pF OBSOLETE

Rev. C | Page 5 of 20 Parameter Symbol Min Typ1 Max Unit Test Conditions/Comments POWER SUPPLIES VDD 10 62 V VLOGIC 2.3 5.5 V Quiescent Supply Current IQUIESCENT 0.6 0.75 mA Static conditions; DAC output = midscale Logic Supply Current ILOGIC 0.4 2 µA VIH = VLOGIC; VIL = DGND DC PSRR4

30 V mode 76 dB DAC output = full scale

60 V mode 68 dB DAC output = full scale

Supply Current IDD_PWD Software Power-Down Mode 30 50 µA Junction Temperature6 TJ 130 °C TJ = TA + PTOTAL × θJA 1 Typical specifications represent average readings at 25°C, VDD = 62 V, and VLOGIC = 5 V. 2 Valid in the output voltage range of (AGND + 0.5 V) to (VDD − 0.5 V). Output is unloaded. 3 Includes linearity, offset, and gain drift. 4 Guaranteed by design and characterization. Not production tested. 5 The DAC architecture gives a fixed linear voltage output range of 0 V to 30 V if R_SEL is held high and 0 V to 60 V if R_SEL is held low. As the output voltage range is limited by output amplifier compliance, VDD should be set to at least 0.5 V higher than the maximum output voltage to ensure compliance. 6 If the die temperature exceeds 110°C, the AD5501 enters a temperature power-down mode putting the DAC output into a high impedance state thereby removing the short-circuit condition. Overheating caused by long term short-circuit condition(s) is detected by an integrated thermal sensor. After power-down, the AD5501 remains powered down until a software power-up command is executed. 7 Maximum resistance between VOUT and VFB pins. AC CHARACTERISTICS VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted. Ta ble 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 AC CHARACTERISTICS Output Voltage Settling Time ¼ to ¾ scale settling to ±1 LSB, RL = 60 kΩ

60 V Mode 45 55 µs

30 V Mode 25 35 µs

Slew Rate 0.65 V/µs Digital-to-Analog Glitch Energy 300 nV-s 1 LSB change around major carry in 60 V mode Glitch Impulse Peak Amplitude 170 mV 60 V mode Digital Feedthrough 5 nV-s Peak-to-Peak Noise 140 μV p-p 0.1 Hz to 10 Hz; DAC code = 0x800 4 mV p-p 0.1 Hz to 10 kHz; DAC code = 0x800 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to + 105°C, typical at 25°C. OBSOLETE

VDD = 30 V , VLOGIC = 2.3 V to 5.5 V, and −40°C < TA < +105°C, all specifications TMIN to TMAX, unless otherwise noted. 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 16.667 MHz. 3 Under the load conditions that are outlined in Figure 2. 4 Time from when VDD or VLOGIC supplies are powered-up to when a digital interface command can be executed. 5 Time required from execution of power-on software command to when the DAC output has settled to 1 V. Figure 2. Load Circuit for SDO Timing Diagram

100 mA do not cause SCR latch-up. soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance

Figure 5. Pin Configuration Table 7. Pin Function Descriptions 1 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are set to 0x000 and the output to zero scale. edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. DAC output is updated automatically when data is written to the input register. 9, 10 NC Not Connected. These pins remain unconnected. 11 VFB Voltage Feedback Pin. Feedback node for the output amplifier. 12 VOUT Buffered Analog Output Voltage from the DAC. selects a DAC output range of 0 V to 30 V. capacitors and 10 µF capacitors. 15 ALARM Active Low CMOS Output Pin. Flags an alarm if the temperature on the die exceeds 110°C.

Rev. C | Page 12 of 20 TERMINOLOGY Relative Accuracy (Integral Nonlinearity) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x000) is loaded into the DAC register. Ideally, the output should be 0 V . The zero-code error is always positive in the AD5501 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in millivolts. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature expressed in μV/°C. Offset Error A measure of the difference between V OUT (actual) and VOUT (ideal) expressed in millivolts in the linear region of the transfer function. Offset error is measured on the AD5501 with Code 32 loaded in the DAC registers for 60 V mode and with Code 64 loaded in the DAC registers for 30 V mode. Offset error is expressed in millivolts. Offset Error Drift Offset error drift is a measure of the change in offset error with a change in temperature. It is expressed in μV/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFF) is loaded into the DAC register expressed in millivolts. Full-Scale Error Drift Full-scale error drift is a measure of the change in full-scale error with a change in temperature. It is expressed in μV/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Gain Temperature Coefficient The gain temperature coefficient is a measure of the change in gain with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V OUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VDD is dc varied ±10%. AC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V OUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VDD is ac varied ±10%. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to SYNC held high). It is specified in nV-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Capacitive Load Stability Capacitive load stability refers to the ability of the amplifier to drive a capacitive load. An amplifier output is considered stable if any overshoot or ringing has stopped before approximately 1.5 times the settling time of the DAC has elapsed. OBSOLETE

Rev. C | Page 14 of 20 SELECTING THE OUTPUT RANGE The output range of the DAC is selected by the R_SEL pin. When the R_SEL pin is connected to a Logic 1, the DAC output voltage can be set between 0 V and 30 V. When the R_SEL pin is connected to a Logic 0, the DAC output voltage can be set between 0 V and 60 V. The state of R_SEL can be changed any time when the serial interface is not being used, that is, not during a read or write operation. When the R_SEL pin is changed, the voltage on the output pin remains the same until the next write to the DAC register (and LDAC is brought low). For example, if the user writes 0x800 to the DAC register when in 30 V mode (R_SEL = 1), the output voltage is 15 V (assuming LDAC is low or has been pulsed low). When the user switches to 60 V mode (R_SEL = 0), the output stays at 15 V until the user writes a new value to the DAC register. LDAC must be low or be pulsed low for the output to change. CLR FUNCTION The AD5501 has a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to 0x000. The CLR pulse activation time, that is, the falling edge of CLR to when the output starts to change, is typically 100 ns. LDAC FUNCTION The DAC output can be updated using the hardware LDAC pin. LDAC is normally high. On the falling edge of LDAC, data is copied from the input register to the DAC register and the DAC output is updated (asynchronous update mode, see Figure 3). If the LDAC is kept low or is low on the falling edge of the 16th SCLK, the DAC register and DAC output are updated automatically when new data is received in the input register (synchronous update mode, see Figure 3). TEMPERATURE SENSOR The AD5501 has an integrated temperature sensor, which causes the part to enter thermal shutdown mode when the temperature on the die exceeds 110°C. In thermal shutdown mode, the analog section of the device powers down and the DAC output is disconnected but the digital section remains operational, which is equivalent to setting the power-down bit in the control register. To indicate that the AD5501 has entered temperature shutdown mode, Bit 0 of the control register is set to 1 and the ALARM pin goes low. The AD5501 remains in temperature shutdown mode with Bit 0 set to 1 and the ALARM pin low, even if the die temperature falls, until Bit 0 in the control register is cleared to 0. POWER DISSIPATION Drawing current from the VOUT pin causes a temperature rise in the die and package of the AD5501. The package junction temperature (TJ) should not exceed 130°C for normal operation. If the die temperature exceeds 110°C, the AD5501 enters thermal shutdown mode as described in the previous section. The amount of heat generated can be calculated using the formula TJ = TA + (PTOTAL × θJA) where: TJ is the package junction temperature. TA is the ambient temperature. PTOTAL is the total power being consumed by the AD5501. θJA is the thermal impedance of the AD5501 package (see the Absolute Maximum Ratings section for this value). POWER SUPPLY SEQUENCING The power supplies for the AD5501 can be applied in any order without affecting the device. However, before the power supplies are applied, connect the AGND and DGND pins to the relevant ground plane. Do not allow any of the digital input pins (SCLK, SDI, SYNC, R_SEL, and CLR) to float during power up. The digital input pins can be connected to pull-up (to VLOGIC) or pull-down (to DGND) resistors as required. OBSOLETE

not directly writeable or readable. three address bits and 12 DAC data bits. Data is loaded MSB first. rails to minimize power consumption in the digital input buffers. the SDO pin on the next 12 clocks of the same frame. operation should not exceed 9 MHz. Table 8. Input Register Bit Map Table 9. Input Register Bit Functions R/W Indicates a read from or a write to the addressed register. A2, A1, A0 These bits determine if the input register or the control register is to be accessed.

1 No operation command

Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. C | Page 18 of 20 NOTES OBSOLETE

Rev. C | Page 19 of 20 NOTES OBSOLETE

Rev. C | Page 20 of 20 NOTES ©2009-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07992-0-12/12(C) OBSOLETE