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Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface Data Sheet AD5428/AD5440/AD5447 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
10 MHz multiplying bandwidth
INL of ±0.25 LSB at 8 bits 20-lead and 24-lead TSSOP packages 2.5 V to 5.5 V supply operation ±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C 4-quadrant multiplication Power-on reset 0.5 µA typical current consumption Guaranteed monotonic Readback function AD7528 upgrade (AD5428) AD7547 upgrade (AD5447)
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit, dual-channel, current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered and other applications. As a result of being manufactured on a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The DACs use data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s, and the DAC outputs are at zero scale. ㈀he applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. The AD5428 is available in a small 20-lead TSSOP package, and the AD5440/AD5447 DACs are available in small 24-lead TSSOP packages. FUNCTIONAL BLOCK DIAGRAM 04462-001 CONTROL LOGIC INPUT BUFFER DATA INPUTS IOUT ADB0 DAC A/B CS R/W DGND DB7 DB9 DB11 I OUT B AGND AD5428/AD5440/AD5447 LATCH LATCH 8-/10-/12-BIT R-2R DAC A 8-/10-/12-BIT R-2R DAC B POWER-ON RESET VDD VREF A VREF B R FB A R FB B R R Figure 1. 1 U.S. Patent Number 5,689,257.
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 2 of 32 TABLE OF CONTENTS
REVISION HISTORY
1/16—Rev. C. to Rev. D 8/11—Rev. B to Rev. C Changes to CS 3/11—Rev. A to Rev. B 7/05—Rev. 0 to Rev. A Changed Pin DAC A/B to DAC A Changes to Divider or Programmable Gain Element Section .... 20 Added 8xC51-to-AD5428/AD5440/AD5447 Added ADSP-BF5xx-to-AD5428/AD5440/AD5447 Changes to Power Supplies for the Evaluation Board Section .... 23 7/04—Revision 0: Initial Version
Data Sheet AD5428/AD5440/AD5447 Rev. D | Page 3 of 32 SPECIFICATIONS1 VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V . Temperature range for Y version: −40°C to +125°C. All speciications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5428 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5440 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5447 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±5 nA Data = 0x0000, T A = 25°C ±15 nA Data = 0x0000 REFERENCE INPUT Reference Input Range ±10 V VREFA, VREFB Input Resistance 8 10 13 kΩ Input resistance TC = –50 ppm/°C VREFA-to-VREFB Input Resistance Mismatch 1.6 2.5 % Typ = 25°C, max = 125°C Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, VIH 1.7 V V DD = 3.6 V to 5.5 V 1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V V DD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH V DD − 1 V V DD = 4.5 V to 5.5 V, ISOURCE = 200 μA V DD − 0.5 V V DD = 2.5 V to 3.6 V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V V DD = 4.5 V to 5.5 V, ISINK = 200 μA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 μA Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying BW 10 MHz V REF = ±3.5 V p-p, DAC loaded all 1s Output Voltage Settling Time R LOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall times, V REF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, VREF = 0 V
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 4 of 32 Parameter Min Typ Max Unit Conditions Multiplying Feedthrough Error DAC latches loaded with all 0s, V REF = ±3.5 V 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Digital Feedthrough 1 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V REF = 3.5 V p-p, all 1s loaded, f = 100 kHz Digital THD Clock = 10 MHz, V REF = 3.5 V 100 kHz fOUT 61 dB 50 kHz fOUT 66 dB SFDR Performance (Wide Band) AD5447, 65k codes, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 55 dB 100 kHz fOUT 63 dB 50 kHz fOUT 65 dB Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz fOUT 60 dB 50 kHz fOUT 62 dB SFDR Performance (Narrow Band) AD5447, 65k codes, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50k Hz fOUT 87 dB Clock = 25 MHz 500 kHz fOUT 70 dB 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion AD5447, 65k codes, VREF = 3.5 V f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 10 MHz f1 = 40 kHz, f2 = 50 kHz 65 dB Clock = 25 MHz POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.7 μA TA = 25°C, logic inputs = 0 V or VDD 0.5 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD Power Supply Sensitivity 0.001 %/% ∆V DD = ±5% 1 Guaranteed by design, not subject to production test.
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 6 of 32 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND –0.3 V to +7 V VREFA, VREFB, RFBA, RFBB to DGND –12 V to +12 V IOUT1, IOUT2 to DGND –0.3 V to +7 V Logic Inputs and Output1 –0.3 V to V DD + 0.3 V Operating Temperature Range Automotive (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 20-lead TSSOP θJA Thermal Impedance 143°C/W 24-lead TSSOP θJA Thermal Impedance 128°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at DBx, CS, and R/W are clamped by internal diodes. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20) achieve single-supply operation. 2, 20 I OUTA, IOUTB DAC Current Outputs. 4, 18 V REFA, VREFB DAC Reference Voltage Input Terminals. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to14 DB7 to DB0 Parallel Data Bits 7 Through 0. CS to read back contents of the DAC register. 17 V DD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24) achieve single-supply operation. 2, 24 I OUTA, IOUTB DAC Current Outputs. 3, 23 R FBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier output. 4, 22 V REFA, VREFB DAC Reference Voltage Input Terminals. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to16 DB9 to DB0 Parallel Data Bits 9 Through 0. CS to read back contents of the DAC register. 21 V DD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24) achieve single-supply operation. 2, 24 I OUTA, IOUTB DAC Current Outputs. 4, 22 V REFA, VREFB DAC Reference Voltage Input Terminals. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to 18 DB11 to DB0 Parallel Data Bits 11 Through 0. CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent. Any changes on the data lines are reflected in the relevant DAC output. 21 V DD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Figure 25. Power Supply Rejection Ratio vs. Frequency Figure 26. THD + Noise vs. Frequency Figure 27. Wideband SFDR vs. fOUT Frequency Figure 28. Wideband SFDR vs. fOUT Frequency
0 TA = 25C
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Data Sheet AD5428/AD5440/AD5447 Rev. D | Page 15 of 32 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is typically expressed in LSBs or as a percentage of the full-scale reading. Differential Nonlinearity The difference in the measured change and the ideal 1 LSB change between two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error (Full-Scale Error) A measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF – 1 LSB. The gain error of the DACs is adjustable to zero with an external resistance. Output Leakage Current The current that flows into the DAC ladder switches when they are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows into the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time The amount of time for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs is capacitively coupled through the device and produces noise on the IOUT pins and, subsequently, on the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics are included, such as second to fifth harmonics. 5432 V VVVVTHD 2222 log20 Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones digitally generated by the DAC and the second-order products at 2fa − b and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonic or nonharmonic spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fs/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50%, of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.
flows into each ladder leg, regardless of digital input code. the amplifier’s inverting input node. Figure 37. Simplified Ladder switch is used in series with the internal RFBA feedback resistor. n is the resolution of the DAC. the on and off states of the DAC switches. input signals in the range of –10 V to +10 V . signal, the circuit performs 2-quadrant multiplication. Table 7. Unipolar Code
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION. Figure 38. Unipolar Operation
−VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). Table 8. Bipolar Code there is excessive parasitic capacitance at the inverting node. 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V OUT A = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR V OUT B = 0V WITH CODE 10000000 IN DAC B LATCH. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER. Figure 39. Bipolar Operation (4-Quadrant Multiplication)
Table 9. Suitable ADI Precision References Table 10. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Table 11. Suitable ADI High Speed Op Amps
Data Sheet AD5428/AD5440/AD5447 Rev. D | Page 23 of 32 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5428/AD5440/AD5447 is mounted should be designed so that the analog and digital sections are separate and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close as possible to the package, ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), like the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best method, but its use is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. It is good practice to use compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close as possible to the device. EVALUATION BOARD FOR THE AD5447 The evaluation board consists of an AD5447 DAC and a current-to-voltage amplifier, the AD8065. Included on the evaluation board is a 10 V reference, the ADR01. An external reference may also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software simply allows the user to write a code to the device. POWER SUPPLIES FOR THE EVALUATION BOARD The board requires ±12 V and +5 V supplies. The +12 V VDD and −12 V VSS are used to power the output amplifier; the +5 V is used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10 μF tantalum and 0.1 μF ceramic capacitors.
Figure 46. Schematic of AD5447 Evaluation Board
Figure 49. Solder-Side Artwork
Table 12. Bill of Materials
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 28 of 32 OVERVIEW OF MULTIPLYING DAC DEVICES Table 13. Part No. Resolution No. DACs INL (LSB) Interface Package 1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
6.40 BSC
Figure 50. 20-Lead Thin Shrink Outline Package [TSSOP]
0.10 COPLANARITY
Figure 51. 24-Lead Thin Shrink Small Outline Package [TSSOP]
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 30 of 32 ORDERING GUIDE Model1 Resolution INL (LSB) Temperature Rang e Package Description Package Option AD5428YRU 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRU-REEL7 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL7 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5440YRU 10 ±0.5 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ 10 ±0.5 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL7 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRU 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL7 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 EVAL-AD5447EBZ Evaluation Kit 1 Z = RoHS Compliant Part.
Data Sheet AD5428/AD5440/AD5447 Rev. D | Page 31 of 32 NOTES
AD5428/AD5440/AD5447 Data Sheet Rev. D | Page 32 of 32 NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04462-0-1/16(D)