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8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5426/AD5432/AD5443 Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
2.5 V to 5.5 V supply operation
50 MHz serial interface
10 MHz multiplying bandwidth
2.5 MSPS update rate
INL of ±1 LSB for 12-bit DAC ±10 V reference input Low glitch energy < 2 nV-s Extended temperature range −40°C to +125°C 10-lead MSOP package Pin-compatible 8-, 10-, and 12-bit current output DACs Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Daisy-chain mode Readback function 0.4 µA typical power consumption
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD5426/AD5432/AD54431 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs use a double buffered, 3-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing on a CMOS submicron process, the parts offer excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 MHz. The applied external reference input voltage, VREF, determines the full-scale output current. An integrated feedback resistor, RFB, provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. The AD5426/AD5432/AD5443 DACs are available in small, 10-lead MSOP packages. The EV-AD5443/46/53SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM SCLK SYNC AD5426/ AD5432/ AD5443 VREF IOUT2 IOUT1 RFB R 8-/10-/12-BIT R-2R DAC DAC REGISTER SDIN VDD GND POWER-ON RESET CONTROL LOGIC AND INPUT SHIFT REGISTER INPUT LATCH SDO 03162-001 Figure 1. 1 U.S. Patent No. 5,689,257.
AD5426/AD5432/AD5443 Data Sheet Rev. G | Page 2 of 24 TABLE OF CONTENTS DACs Used as a Divider or Programmable Gain Element ... 18
REVISION HISTORY
6/13—Rev. F to Rev. G 7/12—Rev. E to Rev. F No Change to Content, Changed VDD Values in 7/12 Revision 7/12—Rev. D to Rev. E Changed V 4/12—Rev. C to Rev. D Deleted Microprocessor Interface Section, ADSP-21xx to AD5426/AD5432/AD5443 Interface Section, Figure 51, Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443 Interface Section, Figure 53 and Figure 54; Renumbered Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/ AD5443 Interface Section, Figure 56, MICROWIRE to AD5426/AD5432/AD5443 Interface Section, Figure 57, PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22 Deleted Evaluation Board for the AD5426/AD5432/AD5443 Series of DACs Section, Operating the Evaluation Board 2/09—Rev. B to Rev. C Changes to Low Power Serial Interface Section and Daisy- 11/08—Rev. A to Rev. B 5/05—Rev. 0 to Rev. A 2/04—Revision 0: Initial Version
Data Sheet AD5426/AD5432/AD5443 Rev. G | Page 3 of 24 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted; dc performance measured with OP177; ac performance with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5426 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic AD5432 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5443 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temperature Coefficient1 ±5 ppm FSR/°C Output Leakage Current ±10 nA Data = 0x0000, TA = 25°C, IOUT1 ±20 nA Data = 0x0000, T = −40°C to 125°C, IOUT1 REFERENCE INPUT1 Reference Input Range ±10 V VREF Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C RFB Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF DIGITAL INPUT/OUTPUT1 Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.6 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 µA Input Leakage Current, IIL 1 µA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s Output Voltage Settling Time VREF = 10 V; RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±16 mV of FS 50 100 ns Measured to ±4 mV of FS 55 110 ns Measured to ±1 mV of FS 90 160 ns Digital Delay 40 75 ns Interface delay time 10% to 90% Rise/Fall Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V Multiplying Feedthrough Error DAC latch loaded with all 0s, VREF = ±3.5 70 dB 1 MHz 48 dB 10 MHz
AD5426/AD5432/AD5443 Data Sheet Rev. G | Page 4 of 24 Parameter Min Typ Max Unit Test Conditions/Comments Output Capacitance IOUT1 12 17 pF All 0s loaded 10 12 pF All 1s loaded IOUT2 22 25 pF All 0s loaded 10 12 pF All 1s loaded Digital Feedthrough 0.1 nV-s Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Digital THD Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF 50 kHz fOUT 73 dB 20 kHz fOUT 74 dB Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 75 dB 20 kHz fOUT 76 dB SFDR Performance (Narrow Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 87 dB 20 kHz fOUT 87 dB Intermodulation Distortion 78 dB Clock = 1 MHz, f1 = 20 kHz, f2 = 25 kHz, VREF = 3.5 V POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 µA T = −40°C to +125°C , logic inputs = 0 V or VDD Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization, not subject to production testing.
Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. 1 Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes. Figure 4. Load Circuit for SDO Timing Specifications
Figure 5. Pin Configuration Table 4. Pin Function Descriptions 2 IOUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz. user to change the active edge to rising edge. interface counts clocks, and data is latched to the shift register on the 16th active clock edge. 8 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 9 VREF DAC Reference Voltage Input. 10 RFB DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
AD5426/AD5432/AD5443 Data Sheet Rev. G | Page 14 of 24 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for 0 and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is V REF − 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the I OUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the I OUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from SYNC rising edge to the full-scale output charge. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled to show up as noise on the I OUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. ( ) log20 V VVVV THD +++ Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the mea- sure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or f S/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.
4-quadrant multiplying operation or a bipolar output swing. amplifier and some external resistors, as shown in Figure 42. In this circuit, the second amplifier, A2, provides a gain of 2. (VOUT = 0 V) to full scale (VOUT = +VREF). loaded to the DAC and n is the resolution of the DAC. Table 6. Bipolar Code Table and there is excessive parasitic capacitance at the inverting node.
- R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR
VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
- MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
- C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH
Figure 42. Bipolar Operation
when stepping through codes. enough to prevent any significant errors in 12-bit applications. common-mode rejection at an 8-, 10-, or 12-bit resolution. IN and AGND), they settle quickly. DAC circuit is determined largely by the output op amp. single-supply amplifiers available from Analog Devices. Table 7. Suitable ADI Precision References Table 8. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Table 9. Suitable ADI High Speed Op Amps
Data Sheet AD5426/AD5432/AD5443 Rev. G | Page 21 of 24 Standalone Mode After power-on, write 1001 to the control word to disable daisy- chain mode. The first falling edge of SYNC resets a counter that counts the number of serial clocks, ensuring the correct number of bits are shifted in and out of the serial shift registers. A rising edge on SYNC during a write causes the write cycle to be aborted. After the falling edge of the 16th SCLK pulse, data is auto- matically transferred from the input shift register to the DAC. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC.
AD5426/AD5432/AD5443 Data Sheet Rev. G | Page 22 of 24 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5426/AD5432/AD5443 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close to the device as possible. The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A micro- strip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between V REF and RFB should also be matched to minimize gain error. T o maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible.
Data Sheet AD5426/AD5432/AD5443 Rev. G | Page 23 of 24 OVERVIEW OF AD54xx AND AD55xx DEVICES Table 11. Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width
0.50 BSC
1.10 MAX
Figure 51. 10-Lead Mini Small Outline Package [MSOP] 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. registered trademarks are the property of their respective owners.