AD5425YRMZ-REEL

AD5425YRMZ AD | Alldatasheet

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8-Bit, High Bandwidth Multiplying DAC with Serial Interface Data Sheet AD5425 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.

FEATURES

2.5 V to 5.5 V supply operation

50 MHz serial interface

2.47 MSPS update rate

INL of ±0.25 LSB

10 MHz multiplying bandwidth

±10 V reference input Low glitch energy: <2 nV-s Extended temperature range: −40°C to +125°C 10-lead MSOP package Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection LDAC function 0.4 µA typical power consumption

APPLICATIONS

Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD54251 is a CMOS, 8-bit, current output digital-to-analog converter that operates from a 2.5 V to 5.5 V power supply, making it suitable for battery-powered applications and many other applications. This DAC utilizes a double buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. An LDAC pin is also provided, which allows simultaneous updates in a multi-DAC configuration. On power-up, the internal shift register and latches are filled with 0s and the DAC outputs are 0 V . As a result of manufacturing on a CMOS submicron process, this DAC offers excellent 4-quadrant multiplication charac- teristics with large signal multiplying bandwidths of 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor, RFB, provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. The AD5425 is available in a small, 10-lead MSOP package. FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 U.S. Patent No. 5,969,657. SCLK SYNC AD5425 VREF IOUT2 IOUT1 RFB R 8-BIT R-2R DAC DAC REGISTER SDIN VDD GND POWER-ON RESET LDAC CONTROL LOGIC AND INPUT SHIFT REGISTER INPUT LATCH 03161-001

IMPORTANT LINKS for the AD5425* Last content update 10/02/2013 05:42 pm PARAMETRIC SELECTION TABLES Data Converters: Overview of AD54xx Devices Find Similar Products By Operating Parameters AD5450 8-Bit High Bandwidth Multiplying DACs with Serial Interface AD5432 High Bandwidth CMOS 10-Bit Serial Interface Multiplying D/A Converter AD5443 High Bandwidth CMOS 12-Bit Serial Interface Multiplying D/A Converter AD5453 14-Bit High Bandwidth Multiplying DACs with Serial Interface DOCUMENTATION AN-912: Driving a Center-Tapped Transformer with a Balanced Current-Output DAC AN-320A: CMOS Multiplying DACs and Op Amps Combine to Build Programmable Gain Amplifier, Part 1 AN-349: Keys to Longer Life for CMOS AN-137: A Digitally Programmable Gain and Attenuation Amplifier Design Digital to Analog Converters ICs Solutions Bulletin 4-Quadrant Multiplying D/A Converters DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE BeMicro FPGA Project for AD5425 with Nios driver AD5425 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for documentation and purchasing Symbols and Footprints DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: 1-800-262-5643 Europe: 00800-266-822-82 China: 4006-100-006 India: 1800-419-0108 Russia: 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD5425 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. Powered by TCPDF (www.tcpdf.org)

Rev. C | Page 2 of 24 TABLE OF CONTENTS DACs Used as a Divider or Programmable Gain Element ... 17

REVISION HISTORY

9/12—Rev. B to Rev. C 6/12—Rev. A to Rev. B Deleted ADSP-2103 and changed ADSP-2191 to Deleted Evaluation Board Section and Operating the Evaluation Board Section, deleted Figure 46 to Figure 49, and deleted 3/05—Rev. 0 to Rev. A 2/04—Revision 0: Initial Version

Rev. C | Page 3 of 24 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±10 nA Data = 0x0000, TA = 25°C, IOUT1 ±20 nA Data = 0x0000, T = −40°C to +125°C, IOUT 1 REFERENCE INPUT1 Reference Input Range ±10 V VREF Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C RFB Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF DIGITAL INPUT/OUTPUT1 Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.6 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 µA Input Leakage Current, IIL 1 µA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V, DAC loaded all 1s Output Voltage Settling Time VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±1 mV 90 160 ns Measured to ±4 mV 55 110 ns Measured to ±16 mV 50 100 ns Digital Delay 40 75 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry VREF = 0 V Multiplying Feedthrough Error DAC latch loaded with all 0s. VREF = ±3.5 V 70 dB 1 MHz 48 dB 10 MHz Output Capacitance IOUT1 12 17 pF All 0s loaded 25 30 pF All 1s loaded IOUT2 22 25 pF All 0s loaded 10 12 pF All 1s loaded Digital Feedthrough 0.1 nV-s Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p; all 1s loaded, f = 1 kHz

Rev. C | Page 4 of 24 Parameter Min Typ Max Unit Conditions/Comments Digital THD Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF 50 kHz fOUT 70 dB 20 kHz fOUT 73 dB Output Noise Spectral Density 25 nV√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 2 MHz , VREF = 3.5 V 50 kHz fOUT 67 dB 20 kHz fOUT 68 dB SFDR Performance (Narrow Band) Clock = 2 MHz, VREF = 3.5 V 50 kHz fOUT 73 dB 20 kHz fOUT 75 dB Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, clock = 2 MHz, VREF = 3.5 V POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 µA Logic inputs = 0 V or VDD, T = −40°C to +125°C Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 1 Guaranteed by design and characterization, not subject to production test.

VREF = 10 V , IOUT2 = 0 V , temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by control bits of serial word. Figure 2. Timing Diagram 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE.

Rev. C | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND −0.3 V to +7 V VREF, RFB to GND −12 V to +12 V IOUT1, IOUT2 to GND −0.3 V to VDD + 0.3 V Logic Input and Output1 −0.3 V to VDD + 0.3 V Operating Temperature Range Extended Industrial (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 10-lead MSOP θJA Thermal Impedance 206°C/W Lead Temperature, Soldering (10 secs) 300°C IR Reflow, Peak Temperature (<20 secs) 235°C 1 Overvoltages at SCLK, SYNC, DIN, and LDAC are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. Pin Configuration Table 4. Pin Function Descriptions 2 IOUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. 4 SCLK Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input. This device can accommodate clock rates of up to 50 MHz. 5 SDIN Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input. 8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. 9 VREF DAC Reference Voltage Input Terminal. 10 RFB DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output.

Figure 28. Narrowband IMD (±50%) Clock = 2 MHz,

Rev. C | Page 13 of 24 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is V REF − 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from SYNC rising edge to the full-scale output charge. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs can be capacitively coupled to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC I OUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. ( ) log20 V VVVVTHD +++= Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the mea- sure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or f S/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.

low enough to prevent any significant errors. common-mode rejection for use at an 8-bit resolution. inputs capacitance buffer amplifiers and careful board design. amplifiers available from Analog Devices. Table 7. Suitable ADI Precision References Table 8. Suitable Precision ADI Op Amps

0.1 Hz to 10 Hz

Table 9. Suitable High Speed ADI Op Amps

Rev. C | Page 22 of 24 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5425 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have an ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply and located as close to the package as possible—ideally up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as found in the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and to filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between V REF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible.

Figure 46. 10-Lead Mini Small Outline Package [MSOP]

0.50 BSC

1.10 MAX

Rev. C | Page 24 of 24 NOTES ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03161-0-9/12(C)