AD5424YCP

AD5424_1 AD | Alldatasheet

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8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface AD5424/AD5433/AD5445 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.

FEATURES

2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of ±1 LSB for 12-bit DAC

10 MHz multiplying bandwidth

±10 V reference input Extended temperature range: –40°C to +125°C 20-lead TSSOP and chip scale (4 mm × 4 mm) packages 8-, 10-, and 12-bit current output DACs Upgrades to AD7524/AD7533/AD7545 Pin-compatible 8-, 10-, and 12-bit DACs in chip scale Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Readback function 0.4 μA typical power consumption

APPLICATIONS

Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD5424/AD5433/AD54451 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respect- ively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing with a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (V REF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of the AD7524/AD7533/ AD7545 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. The AD5424 is available in small, 20-lead LFCSP and 16-lead TSSOP packages, while the AD5433/AD5445 DACs are available in small, 20-lead LFCSP and TSSOP packages. 1 U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM 03160-001 AD5424/ AD5433/ AD5445 VDD CS R/W GND DB0 DATA INPUTS DB7/DB9/DB11 VREF RFB IOUT1 IOUT2 POWER-ON RESET DAC REGISTER INPUT LATCH 8-/10-/12-BIT R-2R DAC R Figure 1.

Rev. B | Page 2 of 32 TABLE OF CONTENTS DACs Used as a Divider or Programmable Gain Element ... 20

REVISION HISTORY

8/09—Rev. A to Rev. B 3/05—Rev. 0 to Rev. A 10/03—Initial Version: Revision 0

Rev. B | Page 3 of 32 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V . Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5424 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic AD5433 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5445 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temperature Coefficient1 ±5 ppm FSR/°C Output Leakage Current1 ±10 nA Data = 0×0000, TA = 25°C, IOUT1 ±20 nA Data = 0×0000, T = −40°C to +125°C, IOUT1 REFERENCE INPUT1 Reference Input Range ±10 V VREF Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C RFB Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.6 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 μA V DD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 μA Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s Output Voltage Settling Time VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±16 mV of full scale 30 60 ns Measured to ±4 mV of full scale 35 70 ns Measured to ±1 mV of full scale 80 120 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V Multiplying Feedthrough Error DAC latch loaded with all 0s, VREF = ±3.5 V 70 dB Reference = 1 MHz 48 dB Reference = 10 MHz

Rev. B | Page 4 of 32 Parameter Min Typ Max Unit Conditions Output Capacitance IOUT1 12 17 pF All 0s loaded 25 30 pF All 1s loaded IOUT2 22 25 pF All 0s loaded 10 12 pF All 1s loaded Digital Feedthrough 1 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Digital THD Clock = 10 MHz, VREF = 3.5 V 50 kHz fOUT 65 dB Output Noise Spectral Density 25 nV√Hz @ 1 kHz SFDR Performance (Wide Band) AD5445, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 55 dB 100 kHz fOUT 63 dB 50 kHz fOUT 65 dB Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz fOUT 60 dB 50 kHz fOUT 62 dB SFDR Performance (Narrow Band) AD5445, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50 kHz fOUT 82 dB Clock = 25 MHz 500 kHz fOUT 70 dB 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion AD5445, VREF = 3.5 V Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz 65 dB f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz 51 dB f1 = 40 kHz, f2 = 50 kHz 65 dB POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 μA Logic inputs = 0 V or VDD, T= −40°C to +125°C Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 1 Guaranteed by design, not subject to production test.

VREF = 10 V , IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. 1 Guaranteed by design, not subject to production test. Figure 2. Timing Diagram

Rev. B | Page 6 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND –0.3 V to +7 V VREF, RFB to GND –12 V to +12 V IOUT1, IOUT2 to GND –0.3 V to +7 V Logic Inputs and Output1 –0.3 V to VDD + 0.3 V Operating Temperature Range Extended Industrial (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP θJA Thermal Impedance 150°C/W 20-Lead TSSOP θJA Thermal Impedance 143°C/W 20-Lead LFCSP θJA Thermal Impedance 135°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Overvoltages at DBx, CS, and R/W, are clamped by internal diodes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrosta tic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge with out detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 16 of 32 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of –1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is V REF – 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the I OUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1, or IOUT2, to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from the CS rising edge to the full-scale output change. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA seconds or nV seconds, depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled through the device to show up as noise on the I OUT pins and subsequently in the following circuitry. This noise is called digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC I OUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. ( ) log 20 V V V V V THD + + + Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is mea- sured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or f S/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case, 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.

by the DAC on the amplifiers inverting input node. Figure 48. Simplified Ladder cation in bipolar mode or in single-supply modes of operation. must be applied to VDD to achieve continuity. voltage swing, as shown in Figure 49. loaded to the DAC and n is the resolution of the DAC. polarity for dc reference voltages. input signals in the range of –10 V to +10 V . signal, the circuit performs 2-quadrant multiplication. Table 7. Unipolar Code Table

0 TO –VREF

R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. IF A1 IS A HIGH SPEED AMPLIFIER. Figure 49. Unipolar Operation

Table 9. Suitable ADI Precision References Table 10. Suitable ADI Precision Op Amps

0.1 Hz to 10 Hz

Table 11. Suitable ADI High Speed Op Amps reference’s output voltage temperature coefficient specification. drift with temperature should be less than 78 ppm/°C. temperature coefficient this error source can be minimized. that are suitable for use with this range of current output DACs.

Rev. B | Page 23 of 32 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5424/AD5433/AD5445 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply, located as close to the package as possible and ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A micro-strip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between V REF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. EVALUATION BOARD FOR THE AD5424/AD5433/AD5445 The board consists of a 12-bit AD5445 and a current-to-voltage amplifier, the AD8065. Included on the evaluation board is a 10 V reference, the ADR01. An external reference may also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software allows the user to simply write a code to the device. POWER SUPPLIES FOR EVALUATION BOARD The board requires ±12 V and 5 V supplies. The 12 V VDD and VSS are used to power the output amplifier, while the +5 V VDD and VSS are used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10 μF tantalum and 0.1 μF ceramic capacitors. Link1 (LK1) is provided to allow selection between the on- board reference (ADR01) and an external reference applied through J2.

Figure 59. Evaluation Board Schematic

Figure 62. Solder-Side Artwork Table 12. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board

Table 13. Overview of AD54xx and AD55xx Devices

Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]

6.40 BSC

Figure 64. 20-Lead Thin Shrink Small Outline Package [TSSOP]

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.60 MAX

0.25 MIN

Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. B | Page 29 of 32 ORDERING GUIDE Model Resolution (Bits) INL (LSB) Temperature Range Package Description Package Option AD5424YRU 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRU-REEL 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRU-REEL7 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ1 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ-REEL1 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ-REEL71 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YCP 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5424YCP-REEL 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5424YCP-REEL7 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5424YCPZ-REEL1 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5424YCPZ-REEL71 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5433YRU 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRU-REEL 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRU-REEL7 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ1 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ-REEL1 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ-REEL71 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YCP 10 ±0.5 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5433YCP-REEL 10 ±0.5 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5433YCP-REEL7 10 ±0.5 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5433YCPZ1 10 ±0.5 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5445YRU 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRU-REEL 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRU-REEL7 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ1 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ-REEL1 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ-REEL71 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YCP 12 ±1 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5445YCP-REEL 12 ±1 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5445YCP-REEL7 12 ±1 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5445YCPZ1 12 ±1 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 EVAL-AD5424EBZ1 Evaluation Kit EVAL-AD5433EBZ1 Evaluation Kit EVAL-AD5445EBZ1 Evaluation Kit 1 Z = RoHS Compliant Part.

Rev. B | Page 30 of 32 NOTES

Rev. B | Page 31 of 32 NOTES

Rev. B | Page 32 of 32 NOTES ©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D03160-0-8/09(B)