AD5424/AD5433/AD5445 (Rev. E)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 28
Technical content
8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface Data Sheet AD5424/AD5433/AD5445 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of ±1 LSB for 12-bit DAC
10 MHz multiplying bandwidth
±10 V reference input Extended temperature range: –40°C to +125°C 20-lead TSSOP and chip scale (4 mm × 4 mm) packages 8-, 10-, and 12-bit current output DACs Upgrades to AD7524/AD7533/AD7545 Pin-compatible 8-, 10-, and 12-bit DACs in chip scale Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Readback function 0.4 µA typical power consumption
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD5424/AD5433/AD54451 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing with a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of the AD5424/AD5433/ AD5445 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. The AD5424 is available in a small, 20-lead LFCSP and a small, 16-lead TSSOP, while the AD5433 and AD5445 DACs are available in a small, 20-lead LFCSP and a small, 20-lead TSSOP . The E VA L-AD5445SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-333 evaluation board user guide. 1 U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM 03160-001 AD5424/ AD5433/ AD5445 VDD CS R/W GND DB0 DATA INPUTS DB7/DB9/DB11 VREF RFB IOUT1 IOUT2 POWER-ON RESET DAC REGISTER INPUT LATCH 8-/10-/12-BIT R-2R DAC R Figure 1.
AD5424/AD5433/AD5445 Data Sheet Rev. E | Page 2 of 28 TABLE OF CONTENTS DACs Used as a Divider or Programmable Gain Element ... 21
REVISION HISTORY
1/16—Rev. D to Rev. E Deleted Positive Output Voltage Section and Figure 53; Changed ADSP-21xx-to-AD5424/AD5433/AD5445 Interface Section to ADSP-2191M-to-AD5424/AD5433/AD5445 Interface Section and ADSP-BF5xx-to-AD5424/AD5433/ AD5445 Interface Section to Blackfin Processor-to-AD5424/ 4/13—Rev. C to Rev. D 12/12—Rev. B to Rev. C Deleted the Evaluation Board for AD5424/AD5433/AD5445 8/09—Rev. A to Rev. B 3/05—Rev. 0 to Rev. A 10/03—Initial Version: Revision 0
Data Sheet AD5424/AD5433/AD5445 Rev. E | Page 3 of 28 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V . Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5424 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic AD5433 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5445 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temperature Coefficient1 ±5 ppm FSR/°C Output Leakage Current1 ±10 nA Data = 0×0000, TA = 25°C, IOUT1 ±20 nA Data = 0×0000, T = −40°C to +125°C, IOUT1 REFERENCE INPUT1 Reference Input Range ±10 V VREF Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C RFB Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.6 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 µA Input Leakage Current, IIL 1 µA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s Output Voltage Settling Time VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±16 mV of full scale 30 60 ns Measured to ±4 mV of full scale 35 70 ns Measured to ±1 mV of full scale 80 120 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V Multiplying Feedthrough Error DAC latch loaded with all 0s, VREF = ±3.5 V 70 dB Reference = 1 MHz 48 dB Reference = 10 MHz
AD5424/AD5433/AD5445 Data Sheet Rev. E | Page 4 of 28 Parameter Min Typ Max Unit Test Conditions/Comments Output Capacitance IOUT1 12 17 pF All 0s loaded 25 30 pF All 1s loaded IOUT2 22 25 pF All 0s loaded 10 12 pF All 1s loaded Digital Feedthrough 1 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Digital THD Clock = 10 MHz, VREF = 3.5 V 50 kHz fOUT 65 dB Output Noise Spectral Density2 25 nV√Hz At 1 kHz SFDR Performance (Wide Band) AD5445, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 55 dB 100 kHz fOUT 63 dB 50 kHz fOUT 65 dB Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz fOUT 60 dB 50 kHz fOUT 62 dB SFDR Performance (Narrow Band) AD5445, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50 kHz fOUT 82 dB Clock = 25 MHz 500 kHz fOUT 70 dB 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion AD5445, VREF = 3.5 V Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz 65 dB f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz 51 dB f1 = 40 kHz, f2 = 50 kHz 65 dB POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 µA Logic inputs = 0 V or VDD, T= −40°C to +125°C Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 1 Guaranteed by design, not subject to production test. 2 Specification measured with OP27.
VREF = 10 V , IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. 1 Guaranteed by design, not subject to production test. Figure 2. Timing Diagram
AD5424/AD5433/AD5445 Data Sheet Rev. E | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND –0.3 V to +7 V VREF, RFB to GND –12 V to +12 V IOUT1, IOUT2 to GND –0.3 V to +7 V Logic Inputs and Output1 –0.3 V to VDD + 0.3 V Operating Temperature Range Extended Industrial (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP θJA Thermal Impedance 150°C/W 20-Lead TSSOP θJA Thermal Impedance 143°C/W 20-Lead LFCSP θJA Thermal Impedance 135°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at DBx, CS, and R/W, are clamped by internal diodes. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 3. AD5424 Pin Configuration (TSSOP)
15 R/W
- THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 4. AD5424 Pin Configuration (LFCSP) Table 4. AD5424 Pin Function Descriptions 1 19 IOUT1 DAC Current Output. 2 20 IOUT2 DAC Analog Ground. This pin must normally be tied to the analog ground of the system. 4 to 11 2 to 9 DB7 to DB0 Parallel Data Bits 7 to 0. 10 to 13 NC No Internal Connection. latch or to read data from the DAC register. Rising edge of CS loads data. to read back contents of DAC register. 14 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 15 17 VREF DAC Reference Voltage Input Terminal. Not applicable EPAD Exposed Pad. The exposed pad must be connected to AGND.
Figure 5. AD5433 Pin Configuration (TSSOP)
11 DB0
- THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 6. AD5433 Pin Configuration (LFCSP) Table 5. AD5433 Pin Function Descriptions 1 19 IOUT1 DAC Current Output. 2 20 IOUT2 DAC Analog Ground. This pin must normally be tied to the analog ground of the system. 4 to 13 2 to 11 DB9 to DB0 Parallel Data Bits 9 to 0. 14, 15 12, 13 NC Not Internally Connected. latch or to read data from the DAC register. Rising edge of CS loads data. to read back contents of DAC register. 18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 19 17 VREF DAC Reference Voltage Input Terminal. Not applicable EPAD Exposed Pad. The exposed pad must be connected to AGND.
Figure 7. AD5445 Pin Configuration (TSSOP)
11 DB2
- THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 8. AD5445 Pin Configuration (LFCSP) Table 6. AD5445 Pin Function Descriptions 1 19 IOUT1 DAC Current Output. 2 20 IOUT2 DAC Analog Ground. This pin must normally be tied to the analog ground of the system. 4 to 15 2 to 13 DB11 to DB0 Parallel Data Bits 11 to 0. latch or to read data from the DAC register. Rising edge of CS loads data. CS to read back contents of DAC register. 18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 19 17 VREF DAC Reference Voltage Input Terminal. Not applicable EPAD Exposed Pad. The exposed pad must be connected to AGND.
Data Sheet AD5424/AD5433/AD5445 Rev. E | Page 17 of 28 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of –1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is V REF – 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the I OUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1, or IOUT2, to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from the CS rising edge to the full-scale output change. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA seconds or nV seconds, depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs can be capacitively coupled through the device to show up as noise on the I OUT pins and subsequently in the following circuitry. This noise is called digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. ( ) log20 V VVVV THD +++ Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is measured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or f S/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case, 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.
at VREF is always constant and nominally of resistance value R. DAC on the amplifiers inverting input node. Figure 48. Simplified Ladder voltage swing, as shown in Figure 49. to the DAC and n is the resolution of the DAC. polarity for dc reference voltages. digital logic to drive the DAC switches’ on and off states. input signals in the range of –10 V to +10 V . signal, the circuit performs 2-quadrant multiplication. output voltage for unipolar operation (AD5424, 8-bit device). Table 7. Unipolar Code Table
0 TO –VREF
R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. IF A1 IS A HIGH SPEED AMPLIFIER. Figure 49. Unipolar Operation
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. Figure 50. Bipolar Operation (4-Quadrant Multiplication) 4-quadrant multiplying operation or a bipolar output swing. amplifier and some external resistors, as shown in Figure 50. In this circuit, the second amplifier, A2, provides a gain of 2. (VOUT = 0 V) to full scale (VOUT = +VREF). loaded to the DAC and n is the resolution of the DAC. Table 8. Bipolar Code Table ringing or instability in closed-loop applications.
recommended in circuits where gains greater than 1 are required. percentage of 100 × (R2||R3)/RFB. REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 53. Increasing the Gain of the Current Output DAC inversely proportional to the digital input fraction, D. and that the required accuracy is met.
16.5 VIN—an error of 3% even though the DAC itself has a
Figure 54. Current-Steering DAC Used as a Divider or opposite current supplied from the op amp through the DAC. where R is the DAC resistance at the VREF terminal. (that is, 1/D) of 16, the error voltage is 1.6 mV .
Table 9. Suitable ADI Precision References Table 10. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Table 11. Suitable ADI High Speed Op Amps but can also affect the linearity (INL and DNL) performance. system drift with temperature must be less than 78 ppm/°C. temperature coefficient this error source can be minimized. that are suitable for use with this range of current output DACs. LSB to ensure monotonic behavior when stepping through codes. low enough to prevent significant errors in 12-bit applications. common mode rejection for use at 8-, 10-, and 12-bit resolution.
never be run near the reference inputs. are placed on the solder side. possible to minimize IR drops and stray inductance. I-to-V amplifier as close to the device as possible. Table 12. Overview of the AD5424/AD5433/AD5445 and Related Multiplying DACs
Figure 58. 16-Lead Thin Shrink Small Outline Package [TSSOP]
6.40 BSC
Figure 59. 20-Lead Thin Shrink Small Outline Package [TSSOP]
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
0.02 NOM
0.20 REF
0.20 MIN
Figure 60. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Data Sheet AD5424/AD5433/AD5445 Rev. E | Page 27 of 28 NOTES
AD5424/AD5433/AD5445 Data Sheet Rev. E | Page 28 of 28 NOTES ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03160-0-1/16(E)