AD5421

AD5421 (Rev. I)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC Data Sheet AD5421 Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Suppor t www.analog.com

FEATURES

16-bit resolution and monotonicity Pin selectable NAMUR-compliant ranges 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA NAMUR-compliant alarm currents Downscale alarm current = 3.2 mA Upscale alarm current = 22.8 mA/24 mA Total unadjusted error (TUE): 0.05% maximum INL error: 0.0035% FSR maximum Output TC: 3 ppm/°C typical Quiescent current: 300 μA maximum Flexible SPI-compatible serial digital interface with Schmitt triggered inputs On-chip fault alerts via FAUL T pin or alarm current Automatic readback of fault register on each write cycle Slew rate control function Gain and offset adjust registers On-chip reference TC: 4 ppm/°C maximum Selectable regulated voltage output Loop voltage range: 5.5 V to 52 V Temperature range: −40°C to +105°C TSSOP and LFCSP packages

APPLICATIONS

Industrial process control 4 mA to 20 mA loop-powered transmitters Smart transmitters HART network connectivity GENERAL DESCRIPTION The AD5421 is a complete, loop-powered, 4 mA to 20 mA digital-to-analog converter (DAC) designed to meet the needs of smart transmitter manufacturers in the industrial control industry. The DAC provides a high precision, fully integrated, low cost solution in compact TSSOP and LFCSP packages. The AD5421 includes a regulated voltage output that is used to power itself and other devices in the transmitter. This regulator provides a regulated 1.8 V to 12 V output voltage. The AD5421 also contains 1.22 V and 2.5 V references, thus eliminating the need for a discrete regulator and voltage reference. The AD5421 can be used with standard Highway Addressable Remote Transducer (HART®) FSK protocol communication circuitry without any degradation in specified performance. The high speed serial interface is capable of operating at 30 MHz and allows for simple connection to commonly used microprocessors and microcontrollers via a SPI-compatible, 3-wire interface. The AD5421 is guaranteed monotonic to 16 bits. It provides 0.0015% integral nonlinearity, 0.0012% offset error, and 0.0006% gain error under typical conditions. The AD5421 is available in a 28-lead TSSOP and a 32-lead LFCSP specified over the extended industrial temperature range of −40°C to +105°C. COMPANION LOW POWER PRODUCTS HART Modem: AD5700, AD5700-1 Microcontroller: ADuCM360 FUNCTIONAL BLOCK DIAGRAM RSET 24kΩ SYNC SCLK SDIN SDO LDAC RANGE0 RANGE1 ALARM_CURRENT_DIRECTION FAULT RINT/REXT INPUT REGISTER CONTROL LOGIC GAIN/OFFSET ADJUSTMENT REGISTERS TEMPERATURE SENSOR REFOUT2 REFIN CIN REXT1 REXT2REFOUT1 VREF 16 16-BIT DAC LOOP VOLTAGE MONITOR VLOOPDVDDIODVDD AD5421 VOLTAGE REGULATOR REG_SEL0 REG_SEL1 REG_SEL2 REGOUT REGIN DRIVE LOOP– 11.5kΩ 52Ω 09128-001 COM Figure 1.

Rev. I | Page 2 of 36 TABLE OF CONTENTS

Rev. I | Page 3 of 36

REVISION HISTORY

11/2018—Rev. H to Rev. I 11/2014—Rev. G to Rev. H Changes to Offset Adjust Register Section and Gain Adjust 10/2013—Rev. F to Rev. G 1/2013—Rev. E to Rev. F Changes to Table 19 and On-Chip ADC Transfer Function 7/2012—Rev. D to Re v. E Changes to Applications Information Section and Figure 49 ... 31 5/2012—Rev. C to Rev. D Changes to Features Section and Applications Section; Added 12/2011—Rev. B to Rev. C Change to REFOUT1 Pin, Capacitive Load Parameter, Test Change to REGOUT Output, Capacitive Load Parameter, Test 12/2011—Rev. A to Rev. B 5/2011—Rev. 0 to Rev. A Changes to REGIN, REFOUT1, and REFOUT2 Pin Changes to Input Shift Register Section, Table 11, and Register 2/2011—Revision 0: Initial Version

Rev. I | Page 4 of 36 SPECIFICATIONS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments ACCURACY, INTERNAL RSET Resolution 16 Bits Total Unadjusted Error (TUE)2 −0.126 +0.126 % FSR C grade −0.041 ±0.0064 +0.041 % FSR C grade, TA = 25°C −0.18 +0.18 % FSR B grade −0.06 ±0.011 +0.06 % FSR B grade, TA = 25°C −0.27 +0.27 % FSR A grade −0.08 ±0.011 +0.08 A grade, TA = 25°C TUE Long-Term Stability 210 ppm FSR Drift after 1000 hours at TA = 125°C Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade −0.012 ±0.006 +0.012 % FSR B grade −0.024 ±0.01 +0.024 % FSR A grade Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.056 +0.056 % FSR B grade and C grade −0.008 ±0.0008 +0.008 % FSR B grade and C grade, TA = 25°C −0.11 ±0.0008 +0.11 % FSR A grade Offset Error TC3 1 ppm FSR/°C Gain Error −0.107 +0.107 % FSR B grade and C grade −0.035 ±0.0058 +0.035 % FSR B grade and C grade, TA = 25°C −0.2 ±0.0058 +0.2 % FSR A grade Gain Error TC3 4 ppm FSR/°C Full-Scale Error −0.126 +0.126 % FSR B grade and C grade −0.041 ±0.0065 +0.041 % FSR B grade and C grade, TA = 25°C −0.25 ±0.0065 +0.25 % FSR A grade Full-Scale Error TC3 5 ppm FSR/°C Downscale Alarm Current 3.19 3.21 mA Upscale Alarm Current 22.77 22.83 mA 4 mA to 20 mA and 3.8 mA to 21 mA ranges 23.97 24.03 mA 3.2 mA to 24 mA range ACCURACY, EXTERNAL RSET (24 kΩ) Assumes ideal resistor, B grade and C grade only; not specified for A grade Resolution 16 Bits Total Unadjusted Error (TUE)2 −0.048 +0.048 % FSR C grade −0.027 ±0.002 +0.027 % FSR C grade, TA = 25°C −0.08 +0.08 % FSR B grade −0.04 ±0.003 +0.04 % FSR B grade, TA = 25°C TUE Long-Term Stability 40 ppm FSR Drift after 1000 hours at TA = 125°C Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade −0.012 ±0.006 +0.012 % FSR B grade Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.021 +0.021 % FSR −0.007 ±0.0012 +0.007 % FSR TA = 25°C Offset Error TC3 0.5 ppm FSR/°C Gain Error −0.03 +0.03 % FSR −0.023 ±0.0006 +0.023 % FSR TA = 25°C

Rev. I | Page 5 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments Gain Error TC3 1 ppm FSR/°C Full-Scale Error −0.047 +0.047 % FSR −0.028 ±0.0017 +0.028 % FSR TA = 25°C Full-Scale Error TC3 1 ppm FSR/°C Downscale Alarm Current 3.08 3.21 mA Upscale Alarm Current 22.78 23 mA 4 mA to 20 mA and 3.8 mA to 21 mA ranges 23.99 24.01 mA 3.2 mA to 24 mA range OUTPUT CHARACTERISTICS3 Loop Compliance Voltage4 LOOP− + 5.5 V REGOUT < 5.5 V, loop current = 24 mA LOOP− + 12.5 V REGOUT = 12 V, loop current = 24 mA Loop Current Long-Term Stability 100 ppm FSR Drift after 1000 hours at TA = 125°C, loop current = 12 mA, internal RSET 15 ppm FSR Drift after 1000 hours at TA = 125°C, loop current = 12 mA, external RSET Loop Current Error vs. REGOUT Load Current 1.2 µA/mA Loop current = 12 mA, load current from REG OUT = 5 mA Resistive Load 0 2 kΩ See Figure 21 for a load line graph Inductive Load 50 mH Stable operation Power Supply Sensitivity 0.1 µA/V Loop current = 12 mA Output Impedance 12 400 MΩ Output TC 3 ppm FSR/°C Loop current = 12 mA, internal RSET 1 ppm FSR/°C Loop current = 12 mA, external RSET Output Noise

0.1 Hz to 10 Hz 50 nA p-p

500 Hz to 10 kHz 0.2 mV rms HART bandwidth; measured across 500 Ω load Noise Spectral Density 195 nA/√Hz At 1 kHz 256 nA/√Hz At 10 kHz REFERENCE INPUT (REFIN PIN)3 Reference Input Voltage5 2.5 V For specified performance DC Input Impedance 75 800 MΩ REFERENCE OUTPUTS REFOUT1 Pin Output Voltage 2.498 2.5 2.503 V TA = 25°C Temperature Coefficient 1.5 4 ppm/°C C grade 2 8 ppm/°C B grade 4 10 ppm/°C A grade Output Noise (0.1 Hz to 10 Hz)3 7.5 µV p-p Noise Spectral Density3 245 nV/√Hz At 1 kHz 70 nV/√Hz At 10 kHz Output Voltage Drift vs. Time3 200 ppm Drift after 1000 hours at TA = 125°C Capacitive Load3 10 nF Recommended operation Load Current3, 6 4 mA Short-Circuit Current3 6.5 mA Short circuit to COM Power Supply Sensitivity3 2 12 µV/V Thermal Hysteresis3 285 ppm First temperature cycle 5 ppm Second temperature cycle Load Regulation3 0.1 0.2 mV/mA Measured at 0 mA and 1 mA loads Output Impedance 0.1 Ω REFOUT2 Pin Output Voltage 1.18 1.227 1.28 V TA = 25°C Output Impedance 72 kΩ

Rev. I | Page 6 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments REGOUT OUTPUT Voltage regulator output Output Voltage 1.8 12 V See Table 10 Output Voltage TC3 110 ppm/°C Output Voltage Accuracy −4 ±2 +4 % Externally Available Current3, 6 3.15 mA Assuming 4 mA is flowing in the loop and during HART communications Short-Circuit Current 23 mA Line Regulation3 500 µV/V Internal NMOS 10 µV/V External NMOS Load Regulation3 8 mV/mA Inductive Load 50 mH Stable operation Capacitive Load 2 10 µF Recommended operation ADC ACCURACY Die Temperature ±5 °C VLOOP Input ±1 % DVDD OUTPUT Can be overdriven up to 5.5 V Output Voltage 3.17 3.3 3.48 V Externally Available Current3, 6 3.15 mA Assuming 4 mA is flowing in the loop and during HART communications Short-Circuit Current 7.7 mA Load Regulation 45 mV/mA Measured at 0 mA and 3 mA loads DIGITAL INPUTS3 SCLK, SYNC, SDIN, LDAC Input High Voltage, VIH 0.7 × IODVDD V Input Low Voltage, VIL 0.25 × IODVDD V Hysteresis 0.21 V IODVDD = 1.8 V 0.63 V IODVDD = 3.3 V 1.46 V IODVDD = 5.5 V Input Current −0.015 +0.015 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS3 SDO Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V High Impedance Leakage Current −0.01 +0.01 µA High Impedance Output Capacitance 5 pF FAULT Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V FAULT THRESHOLDS ILOOP Under ILOOP − 0.01% FSR mA ILOOP Over ILOOP + 0.01% FSR mA Temp 140°C 133 °C Fault removed when temperature is ≤ 125°C Temp 100°C 90 °C Fault removed when temperature is ≤ 85°C VLOOP 6V 0.3 V Fault removed when VLOOP ≥ 0.4 V VLOOP 12V 0.6 V Fault removed when VLOOP ≥ 0.7 V

Rev. I | Page 7 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS REGIN 5.5 52 V With respect to LOOP− pin IODVDD 1.71 5.5 V With respect to COM pin Quiescent Current 260 300 µA 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers. 3 Guaranteed by design and characterization; not production tested. 4 The voltage between LOOP− and REGIN must be 5.5 V or greater. 5 The AD5421 is factory calibrated with an external 2.5 V reference connected to REFIN. 6 This is the current that the output is capable of sourcing. The load current originates from the loop and, therefore, contributes to the total current consumption figure.

Rev. I | Page 8 of 36 Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1, 2 C Grade Unit Test Conditions/Comments Min Typ Max ACCURACY, INTERNAL RSET Total Unadjusted Error (TUE)3 −0.157 +0.157 % FSR −0.117 ±0.0172 +0.117 % FSR TA = 25°C Relative Accuracy (INL) −0.004 +0.004 % FSR −0.004 ±0.0015 +0.004 % FSR TA = 25°C Offset Error −0.04 +0.04 % FSR −0.025 ±0.0025 +0.025 % FSR TA = 25°C Offset Error TC 1 ppm FSR/°C Gain Error −0.128 +0.128 % FSR −0.093 ±0.0137 +0.093 % FSR TA = 25°C Gain Error TC 5 ppm FSR/°C Full-Scale Error −0.157 +0.157 % FSR −0.117 ±0.0172 +0.117 % FSR TA = 25°C Full-Scale Error TC 6 ppm FSR/°C ACCURACY, EXTERNAL RSET (24 kΩ) Assumes ideal resistor Total Unadjusted Error (TUE)3 −0.133 +0.133 % FSR −0.133 ±0.0252 +0.133 % FSR TA = 25°C Relative Accuracy (INL) −0.004 +0.004 % FSR −0.004 ±0.0015 +0.004 % FSR TA = 25°C Offset Error −0.029 +0.029 % FSR −0.029 ±0.0038 +0.029 % FSR TA = 25°C Offset Error TC 0.5 ppm FSR/°C Gain Error −0.11 +0.11 % FSR −0.106 ±0.0197 +0.106 % FSR TA = 25°C Gain Error TC 2 ppm FSR/°C Full-Scale Error −0.133 +0.133 % FSR −0.133 ±0.0252 +0.133 % FSR TA = 25°C Full-Scale Error TC 2 ppm FSR/°C 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Specifications guaranteed by design and characterization; not production tested. 3 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers.

Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX, unless otherwise noted. 1 Temperature range: −40°C to +105°C; typical at +25°C. Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX. 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 2 and Figure 3. Table 5. SPI Watchdog Timeout Periods 1 Specifications guaranteed by design and characterization; not production tested.

to 100 mA do not cause SCR latch-up. soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with thermal vias. See JEDEC JESD51.

Rev. I | Page 13 of 36 Pin No. Mnemonic Description TSSOP LFCSP 13, 14 4, 11, 12 COM Ground Reference Pin for the AD5421. It is recommended that a 4.7 V Zener diode be placed between the LOOP− and COM pins. See the Applications Information section for more information. 15, 16, 13, 14, 15 REG_SEL2, REG_SEL1, REG_SEL0 These three pins together select the regulator output (REG OUT) voltage (see the Voltage Regulator section). 18 17 REFIN Reference Voltage Input. VREFIN = 2.5 V for specified performance. 19 18 REFOUT2 Internal Reference Voltage Output (1.22 V). It is recommended to connect a 100 nF capacitor from this pin to COM. 20 19 REFOUT1 Internal Reference Voltage Output (2.5 V). It is recommended to connect a 100 nF capacitor from this pin to COM. 21 20 CIN External Capacitor Connection and HART FSK Input. An external capacitor connected from CIN to COM implements an output slew rate control function (see the Loop Current Slew Rate Control section). HART FSK signaling can also be coupled through a capacitor to this pin (see the HART Communications section). 22, 23 21, 22 REXT1, REXT2 Connection for External Current Setting Resistor. A precision 24 kΩ resistor can be connected between these pins for improved performance. 24 23 LOOP− Loop Current Return Pin. As shown in Figure 1 , the COM and LOOP− pins can be used to sense the loop current across the internal 52 Ω r esistor. Note that the voltage measured at LOOP− is be negative with respect to COM. 25 23 VLOOP Voltage Input Pin. Voltage input range is 0 V to 2.5 V. The voltage applied to this pin is digitized to eight bits, which are available in the fault register. This pin can be used for general-purpose voltage monitoring, but it is intended for monitoring of the loop supply voltage. Connecting the loop voltage to this pin via a 20:1 resistor divider allows the AD5421 to monitor and feedback the loop voltage. The AD5421 also generates an alert if the loop voltage is close to the minimum operating value (see the Loop Voltage Fault section). 26 26 DRIVE Gate Connection for External Depletion Mode MOSFET. For more information, see the Connection to Loop Power Supply section. 27 27 REGIN Voltage Regulator Input. The loop voltage can be connected directly to this pin. Or, to reduce on- chip power dissipation, an external pass transistor can be connected at this pin to stand off the loop voltage. For more information, see the Connection to Loop Power Supply section. 28 28 REGOUT Voltage Regulator Output. Pin selectable values are from 1.8 V to 12 V via the REG_SEL0, REG_SEL1, and REG_SEL2 pins (see the Voltage Regulator section). If REGOUT is driving a microconverter supply (see Figure 50), this pin should be decoupled to COM with a >1 µF capacitor. N/A1 9, 16, 25 NC No Connect. Do not connect to this pin. EPAD Exposed Paddle. The exposed paddle should be connected to the same potential as the COM pin and to a copper plane for optimum thermal performance. 1 N/A means not applicable.

60 DEVICES SHOWN

Figure 37. REFOUT1 Voltage vs. Temperature, 60 Devices Shown Figure 38. REFOUT1 Temperature Coefficient Histogram Figure 39. On-Chip ADC Code vs. Die Temperature Figure 40. On-Chip ADC Code vs. VLOOP Pin Input Voltage

Rev. I | Page 20 of 36 TERMINOLOGY Total Unadjusted Error Total unadjusted error (TUE) is a measure of the total output error. TUE consists of INL error, offset error, gain error, and output drift over temperature, in the case of maximum TUE. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) Error Relative accuracy, or integral nonlinearity (INL) error, is a measure of the maximum deviation in the output current from a straight line passing through the endpoints of the transfer function. INL error is expressed in % FSR. Differential Nonlinearity (DNL) Error Differential nonlinearity (DNL) error is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Offset Error Offset error is a measure of the output error when zero code is loaded to the DAC register and is expressed in % FSR. Offset Error T emperature Coefficient (TC) Offset error TC is a measure of the change in offset error with changes in temperature and is expressed in ppm FSR/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer function from the ideal and is expressed in % FSR. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature and is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register and is expressed in % FSR. Full-Scale Error Temperature Coefficient (TC) Full-scale error TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C. Loop Compliance Voltage Headroom Loop compliance voltage headroom is the minimum voltage between the LOOP− and REG IN pins for which the output current is equal to the programmed value. Output Temperature Coefficient (TC) Output TC is a measure of the change in the output current at 12 mA with changes in temperature and is expressed in ppm FSR/°C. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to −40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in mV . Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output voltage over a given temperature range. Voltage reference TC is expressed in ppm/°C as follows: 610× −= Temp_RangeV VV TC REF_NOM REF_MINREF_MAX where: VREF_MAX is the maximum reference output voltage measured over the total temperature range. VREF_MIN is the minimum reference output voltage measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V . Temp_Range is the specified temperature range (−40°C to +105°C).

any register of the AD5421 for more than a user-defined period. the AD5421, the loop current is also forced to the alarm value. selected via the ALARM_CURRENT_DIRECTION pin. downscale alarm current (3.2 mA). 32 data bits are sent to the AD5421 before SYNC is taken high. FAULT pin is asserted and the PEC bit of the fault register is set. Figure 41. PEC Timing pin is set to logic high in either case.

6 V loop supply value), the VLOOP 6V bit is set; this bit is cleared

the fault register, the FAULT pin is set to logic high. that are not equal to 6 V and 12 V . Figure 42. Resistor Divider Connection at VLOOP Pin temperature is dependent on the temperature coefficient of RSET. unadjusted error of better than 0.126% FSR can be expected. Determining the Expected T otal Error section. RANGE1 pins to the COM and DVDD pins, as shown in Table 9. Table 9. Selecting the Loop Current Range The AD5421 is powered from the 4 mA to 20 mA current loop. to a maximum of 52 V (see Figure 43). Figure 43. Direct Connection of the AD5421 to Loop Power Supply dissipation changes in proportion to the loop power supply voltage. Figure 44. MOSFET Connecting the AD5421 to Loop Power Supply

continuous or noncontinuous gated burst clock. output or mode of operation). as shown in Table 13 and Table 14. The address/command byte decoding is described in Table 12. Table 12. Address/Command Byte Functions

00000001 Write to DAC register

00000010 Write to control register

00000011 Write to offset adjust register

00000100 Write to gain adjust register

00000101 Load DAC

00000110 Force alarm current

00000111 Reset (it is recommended to wait

00001000 Initiate VLOOP/temperature

00001001 No operation

10000001 Read DAC register

10000010 Read control register

10000011 Read offset adjust register

10000100 Read gain adjust register

10000101 Read fault register

to Logic 1 to disable the automatic readback of the fault register. are don’t cares (see Table 13 and Table 14). of SDO on the subsequent write command (see Figure 3). Table 13. Input Shift Register Table 14. Input Shift Register with CRC

Transfer Function section and in Table 16. expressed by the following three equations.

16 D I LOOP +×

16 D ILOOP +×

where D is the decimal value of the DAC register. Table 15. DAC Register Bit Map Table 16. Relationship of DAC Register Code to Ideal Loop Current (Gain = 65,536; Offset = 0)

determines the mode of operation of the AD5421. Table 17. Control Register Bit Map Table 18. Control Register Bit Descriptions write to any AD5421 register occurs or when a NOP command is written. 0 = SPI watchdog timer is enabled (default). 1 = SPI watchdog timer is disabled. This bit specifies whether the fault register contents are automatically clocked out on the SDO pin on each write operation. 0 = fault register contents are clocked out on the SDO pin (default). 1 = fault register contents are not clocked out on the SDO pin. timer times out). When an SPI fault is detected, the SPI fault bit of the fault register and the FAULT pin are always set. 0 = loop current is forced to the alarm value when an SPI fault is detected (default). 1 = loop current is not forced to the alarm value when an SPI fault is detected. 0 = normal operation (default). current of the AD5421 and its associated circuitry. 0 = on-chip ADC measures the voltage between the VLOOP and COM pins (default). 1 = on-chip ADC measures the temperature of the AD5421 die. On-chip ADC 0 = on-chip ADC is disabled (default). 0 = internal voltage reference is powered up (default). 1 = internal voltage reference is powered down and an external voltage reference source is required. This bit specifies whether the FAULT pin is set when the voltage between the VLOOP and COM pins falls to approximately 0.3 V. 0 = FAULT pin is not set when the VLOOP − COM voltage falls to approximately 0.3 V. 1 = FAULT pin is set when the VLOOP − COM voltage falls to approximately 0.3 V.

The read-only fault register is addressed as described in Table 12. The bits in the fault register indicate a range of possible fault conditions. Table 19. Fault Register Bit Map Table 20. Fault Register Bit Descriptions Logic 0. The alarm current direction is determined by the state of the ALARM_CURRENT_DIRECTION pin. error detection. See the Packet Error Checking section for more information. ILOOP Over Yes This bit is set high when the actual loop current is greater than the programmed loop current. ILOOP Under Yes This bit is set high when the actual loop current is less than the programmed loop current. exceeds approximately 140°C. This bit is cleared when the temperature returns below approximately 125°C. AD5421 exceeds approximately 100°C. This bit is cleared when the temperature returns below approximately 85°C. where D is the 8-bit digital code returned by the on-chip ADC. where D is the 8-bit digital code returned by the on-chip ADC.

followed by a write to the data register for the contents of the offset register to take effect. Table 21. Offset Adjust Register Bit Map Table 22. Offset Adjust Register Adjustment Range followed by a write to the data register for the contents of the gain register to take effect. Table 23. Gain Adjust Register Bit Map Table 24. Gain Adjust Register Adjustment Range

Rev. I | Page 31 of 36 Transfer Function Equations with Offset and Gain Adjust Values When the offset adjust and gain adjust register values are taken into account, the transfer equations can be expressed as follows. For the 4 mA to 20 mA output range, the loop current can be expressed as follows: × = D Gain I LOOP 16 mA16 ( )  ++ 768,322 mA16mA4 16 Offset For the 3.8 mA to 21 mA output range, the loop current can be expressed as follows: × = D Gain I LOOP 16 mA2.17 ( )  ++ 768,322 mA2.17mA8.3 16 Offset For the 3.2 mA to 24 mA output range, the loop current can be expressed as follows: × = D Gain I LOOP 16 mA8.20 ( )  ++ 768,322 mA8.20mA2.3 16 Offset where: D is the decimal value of the DAC register. Gain is the decimal value of the gain adjust register. Offset is the decimal value of the offset adjust register. Note that the offset adjust register cannot adjust the zero-scale output value downward.

Figure 51. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]

1.20 MAX

0.15 MAX

0.05 MIN

Figure 55. 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

Rev. I | Page 36 of 36 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD5421ACPZ-REEL7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD5421BCPZ-REEL7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD5421BREZ −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 AD5421BREZ-REEL −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 AD5421BREZ-REEL7 −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 AD5421CREZ −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 AD5421CREZ-RL −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 AD5421CREZ-RL7 −40°C to +105°C 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] RE-28-2 EVAL-AD5421SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09128-0-11/18(I)