AD5415

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Rev. D | Page 2 of 20 TABLE OF CONTENTS PCB Layout, Power Supply Bypassing, and Ground

REVISION HISTORY

11/12—Rev. C to Rev. D 11/11—Rev. B to Rev. C 4/10—Rev. A to Rev. B Changes to Features Section and General Description Section . 1 Deleted Figure 17 and Figure 18; Renumbered Sequentially ... 10 Added Reference Selection Section, Amplifier Selection Section, 9/09—Rev. 0 to Rev. A Changes to Static Performance, Relative Accuracy, 1/04—Revision 0: Initial Version

Rev. D | Page 3 of 20 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V , IOUT = virtual GND, GND = 0 V , VREF = −10 V to +10 V , TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit STATIC PERFORMANCE1 Resolution N AD5547, 1 LSB = VREF/216 = 153 µV at VREF = 10 V 16 Bits AD5557, 1 LSB = VREF/214 = 610 µV at VREF = 10 V 14 Bits Relative Accuracy INL Grade: AD5557C ±1 LSB Grade: AD5547B ±2 LSB Grade: AD5547C ±1 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current IOUT Data = zero scale, TA = 25°C 10 nA Data = zero scale, TA = TA maximum 20 nA Full-Scale Gain Error GFSE Data = full scale ±1 ±4 mV Bipolar Mode Gain Error GE Data = full scale ±1 ±4 mV Bipolar Mode Zero-Scale Error GZSE Data = full scale ±1 ±3 mV Full-Scale Temperature Coefficient2 TCVFS 1 ppm/°C REFERENCE INPUT VREF Range VREF −18 +18 V REF Input Resistance REF 4 5 6 kΩ R1 and R2 Resistance R1 and R2 4 5 6 kΩ R1-to-R2 Mismatch Δ(R1 to R2) ±0.5 ±1.5 Ω Feedback and Offset Resistance RFB, ROFS 8 10 12 kΩ Input Capacitance2 CREF 5 pF ANALOG OUTPUT Output Current IOUT Data = full scale 2 mA Output Capacitance2 COUT Code dependent 200 pF LOGIC INPUT AND OUTPUT Logic Input Low Voltage VIL VDD = 5 V 0.8 V VDD = 3 V 0.4 V Logic Input High Voltage VIH VDD = 5 V 2.4 V VDD = 3 V 2.1 V Input Leakage Current IIL 10 µA Input Capacitance2 CIL 10 pF INTERFACE TIMING2, 3 See Figure 3 Data to WR Setup Time tDS VDD = 5 V 20 ns VDD = 3 V 35 ns Data to WR Hold Time tDH VDD = 5 V 0 ns VDD = 3 V 0 ns WR Pulse Width tWR VDD = 5 V 20 ns VDD = 3 V 35 ns LDAC Pulse Width tLDAC VDD = 5 V 20 ns VDD = 3 V 35 ns RS Pulse Width tRS VDD = 5 V 20 ns VDD = 3 V 35 ns WR to LDAC Delay Time tLWD VDD = 5 V 0 ns VDD = 3 V 0 ns

2 Guaranteed by design; not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used. Figure 3. AD5547/AD5557 Timing Diagram

Rev. D | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VDD to GND −0.3 V to +8 V RFB, ROFS, R1, RCOM, and VREF to GND −18 V to +18 V Logic Inputs to GND −0.3 V to +8 V V(IOUT) to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin except Supplies ±50 mA Thermal Resistance (θJA)1 Maximum Junction Temperature (TJ MAX) 150°C Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature Vapor Phase, 60 sec 215°C Infrared, 15 sec 220°C 1 Package power dissipation = (TJ MAX − TA)/θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 4. AD5547 Pin Configuration Table 3. AD5547 Pin Function Descriptions D0 to D15 Digital Input Data Bits D0 to D15. Signal level must be ≤ VDD + 0.3 V. ties to R1A and the external reference. 4 RFBA Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. not connect when operating in unipolar mode. 8 IOUTA DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output. 9 AGNDA DAC A Analog Ground. 11 AGNDB DAC B Analog Ground. 12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF. connect if operating in unipolar mode. 16 RFBB Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. ties to R1B and an external reference. 18 WR Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. Signal level must be ≤VDD + 0.3 V.

Rev. D | Page 7 of 20 Pin No. Mnemonic Function 19 A0 Address Pin 0. Signal level must be ≤VDD + 0.3 V. 20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V. 21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. 22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤VDD + 0.3 V. 23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. 29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Figure 5. AD5557 Pin Configuration Table 4. AD5557 Pin Function Descriptions 1, 2 NC No Connection. Do not connect anything other than the dummy pads to these pins. ties to R1A and the external reference. 4 RFBA Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. not connect when operating in unipolar mode. 9 AGNDA DAC A Analog Ground. 11 AGNDB DAC B Analog Ground. 12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF. not connect if operating in unipolar mode. 16 RFBB Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. ties to R1B and an external reference. 18 WR Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge. Signal level must be ≤VDD + 0.3 V. 19 A0 Address Pin 0. Signal level must be ≤VDD + 0.3 V. 20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V. 21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. signal level must be ≤VDD + 0.3 V.

23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. D13 to D0 Digital Input Data Bits D13 to D0. Signal level must be ≤VDD + 0.3 V. 29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Table 5. Address Decoder Pins Table 6. Control Inputs 0 X X Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1. 1 0 0 Load the input register with data bits. 1 1 1 Load the DAC register with the contents of the input register. 1 0 1 The input and DAC registers are transparent. on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse. 1 1 0 No register operation.

tional precision resistors for 4-quadrant bipolar applications. the 4 MSBs are decoded into 15 segments of resistor value 2R. adequate for the compensation. power supply rejection degrades at higher frequencies.

4 MSB

15 SEGMENTS

Figure 18. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown

where D is the decimal equivalent of the input code. polarity (see Figure 21). Table 7 shows the negative output vs. Table 7. AD5547 Unipolar Mode Negative Output vs. Code Figure 21. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to –VREF

resistors necessary for precision bipolar multiplying operation. the circuit yields a precision, bipolar –10 V to +10 V output. Table 9 shows some of the results for the 16-bit AD5547. Table 9. AD5547 Output vs. Code Figure 23. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF

with this range of current output DACs. amplifier with low input bias currents and low input offset voltage. which, if large enough, can cause the DAC to be nonmonotonic. at the voltage output of the circuit. IN and AGND), they settle quickly. amplifiers and careful board design. dc and ac applications, as listed in Table 11 and Table 12. Table 10. Suitable Analog Devices Precision References Table 11. Suitable Analog Devices Precision Op Amps

0.1 Hz to 10 Hz

Table 12. Suitable Analog Devices High Speed Op Amps Table 13 lists the latest DACS available from Analog Devices. Table 13. ADI Current Output DACs

6.40 BSC

Figure 26. 38-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the property of their respective owners.