AD5412

AD5412/AD5422 (Rev.P)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 41

Technical content

Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs, HART Connectivity Rev. P DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►12-/16-bit resolution and monotonicity ►Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ►±0.01% FSR typical total unadjusted error (TUE) ►±3 ppm FSR/°C output drift ►Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V ►10% overrange ►±0.01% FSR typical TUE ►±2 ppm FSR/°C output drift ►Flexible serial digital interface ►On-chip output fault detection ►On-chip reference: 10 ppm/°C maximum ►Optional regulated DVCC output ►Asynchronous clear function ►Power supply range ►AVDD: 10.8 V to 40 V ►AVSS: −26.4 V to −3 V/0 V ►Current loop compliance voltage: AVDD – 2.5 V ►Temperature range: −40°C to +105°C ►TSSOP and LFCSP packages

APPLICATIONS

►Process controls ►Actuator controls ►PLC ►HART network connectivity (LFCSP package only) GENERAL DESCRIPTION The AD5412/AD5422 are low cost, precision, fully integrated 12-/16-bit digital-to-analog converters (DAC) offering a programma- ble current source and programmable voltage output designed to meet the requirements of industrial process control applications. The output current range is programmable at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. The LFCSP version of this product has a CAP2 pin so that the HART signals can be coupled onto the current output of the AD5412/AD5422. Voltage output is provided from a separate pin that can be config- ured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V output ranges; an overrange of 10% is available on all ranges. Analog outputs are short and open-circuit protected and can drive capacitive loads of 1 µF. The device operates with an AVDD power supply range from 10.8 V to 40 V. Current loop compliance voltage is 0 V to AVDD − 2.5 V. The flexible serial interface is SPI- and MICROWIRE™-compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on-reset function, ensuring that the device powers up in a known state. The part also includes an asynchronous clear pin (CLEAR) that sets the outputs to zero- scale/midscale voltage output or the low end of the selected current range. The total output error is typically ±0.01% in current mode and ±0.01% in voltage mode. Table 1. Pin-Compatible Devices

analog.com Rev. P | 2 of 41 Voltage and Current Output Ranges on the Industrial HART Capable Analog Output

REVISION HISTORY

11/2023—Rev. O to Rev. P

analog.com Rev. P | 3 of 41 Figure 1.

analog.com Rev. P | 4 of 41 RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges 0 5 V 0 10 V −5 +5 V −10 +10 V Accuracy Output unloaded Resolution 16 Bits AD5422

12 Bits AD5412

Total Unadjusted Error (TUE) B Version −0.1 +0.1 % FSR A Version −0.3 +0.3 % FSR TA = −40°C to +85°C Relative Accuracy (INL)2 −0.008 +0.008 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1 LSB TA = −40°C to +85°C, guaranteed monotonic −1 +1.3 LSB Guaranteed monotonic Bipolar Zero Error −6 +6 mV TA = −40°C to +85°C, bipolar output range −9 +9 mV Bipolar output range −1.5 ±0.2 +1.5 mV TA = 25°C, bipolar output range Bipolar Zero Error Temperature Coefficient (TC)3 ±3 ppm FSR/°CBipolar output range Zero-Scale Error −5 +5 mV TA = −40°C to +85°C −8 +8 mV Zero-Scale Error TC3 ±2 ppm FSR/°C Offset Error −4 +4 mV TA = −40°C to +85°C, unipolar output range −6 +6 mV Unipolar output range −1.5 ±0.2 +1.5 mV TA = 25°C, unipolar output range Offset Error TC3 ±2 ppm FSR/°CUnipolar output range Gain Error −0.07 +0.07 % FSR Gain Error TC3 ±1 ppm FSR/°CTA = −40°C to +85°C ±3 ppm FSR/°C Full-Scale Error −0.07 +0.07 % FSR Full-Scale Error TC3 ±1 ppm FSR/°CTA = −40°C to +85°C ±2 ppm FSR/°C OUTPUT CHARACTERISTICS3 Headroom 0.5 0.8 V Output unloaded Output Voltage Drift vs. Time 90 ppm FSR Drift after 1000 hours, TA = 125°C Short-Circuit Current 20 mA Load 1 kΩ Capacitive Load Stability TA = 25°C RLOAD = ∞ 20 nF RLOAD = 1 kΩ 5 nF

Table 2. (Continued)

1 Temperature range: −40°C to +105°C; typical at +25°C. 3 Guaranteed by design and characterization; not production tested. 4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C. RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Voltage over range enabled.

Table 3. (Continued) 1 Temperature range: −40°C to +105°C; typical at +25°C. 3 Guaranteed by design and characterization; not production tested. RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. 1 Guaranteed by characterization, not production tested.

analog.com Rev. P | 9 of 41 TIMING CHARACTERISTICS RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description WRITE MODE t1 33 ns min SCLK cycle time t2 13 ns min SCLK low time t3 13 ns min SCLK high time t4 13 ns min LATCH delay time t5 5 µs min LATCH high time t6 5 ns min Data setup time t7 5 ns min Data hold time t8 40 ns min LATCH low time t9 20 ns min CLEAR pulse width t10 5 µs max CLEAR activation time READBACK MODE t11 90 ns min SCLK cycle time t12 40 ns min SCLK low time t13 40 ns min SCLK high time t14 13 ns min LATCH delay time t15 40 ns min LATCH high time t16 5 ns min Data setup time t17 5 ns min Data hold time t18 40 ns min LATCH low time t19 35 ns max Serial output delay time (CL SDO4 = 15 pF) t20 35 ns max LATCH rising edge to SDO tristate (CL SDO4 = 15 pF) DAISY-CHAIN MODE t21 90 ns min SCLK cycle time t22 40 ns min SCLK low time t23 40 ns min SCLK high time t24 13 ns min LATCH delay time t25 40 ns min LATCH high time t26 5 ns min Data setup time t27 5 ns min Data hold time t28 40 ns min LATCH low time t29 35 ns max Serial output delay time (CL SDO4 = 15 pF) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = capacitive load on SDO output.

mA do not cause SCR latch-up. Table 6. (Continued)

1 Power dissipated on chip must be derated to keep the junction temperature

sourcing 24 mA into GND from IOUT with a 4 mA on-chip current.

2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with thermal vias. See JEDEC JESD51. ing conditions for extended periods may affect product reliability. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration Table 7. Pin Function Descriptions by leaving the DVCC SELECT pin floating. detected. Open drain output must be connected to a pull-up resistor. 4, 12 3, 15 GND These pins must be connected to 0 V. NC No Connection. Do not connect to these pins. Selects the voltage output clear value, either zero-scale or midscale code (see Table 22). voltage output to the user selected value (zero-scale or midscale). register, also updating the output. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. the rising edge of SCLK (see Figure 3 and Figure 4). 11 12, 13 GND Ground Reference Pin. temperature drift performance. See the AD5412/AD5422 Features section. 14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 5 mV. a 0.1 μF capacitor between DVCC and GND. See the AD5412/AD5422 Features section. capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 19 26 IOUT Current Output Pin.

Table 7. Pin Function Descriptions (Continued) AD5412/AD5422. See the AD5412/AD5422 Features section. N/A 28, 29 CAP1, CAP2 Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features section. 21 32 VOUT Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 1 kΩ, 2000 pF load. 22 33 +VSENSE Sense connection for the positive voltage output load connection. 23 34 −VSENSE Sense connection for the negative voltage output load connection. 24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V. plane for enhanced thermal performance.

analog.com Rev. P | 26 of 41 is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: TC = V REF ma x − V R EF mi n V R EF n om × Temp Ran g e × 10 6 (1) where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 5 V. TempRange is the specified temperature range, −40°C to +105°C. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA.

operation is shown in Figure 2. Table 8. Input Shift Register Format Table 9. Address Byte Functions

00000000 No operation (NOP)

00000001 Data register

01010101 Control register

01010110 Reset register

high, the input data is also invalid. Figure 68. Daisy Chaining the AD5412/AD5422 used to daisy-chain the devices together as shown in Figure 68. continuous or a gated clock. the data (see Figure 4 for a timing diagram). register as shown in Figure 3.

1. Write 0x020001 to the input register. This configures the part for

read mode with the data register selected.

1. Follow this with a second write: a NOP condition, which is

clocked out on the SDO line. Table 10. Read Address Decoding

00 Read status register

01 Read data register

10 Read control register

are read, and the data is applied to internal calibration circuitry.

2 N (2)

2 N −

D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. selected by the user as shown in Table 11. Table 11. Internal Gain Value

2 N × D (4)

2 N × D (5)

2 N × D + 4 mA (6)

D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Table 12. Input Shift Register Contents for a Read Operation Figure 69. Programming Sequence to Write/Enable the Output Correctly

entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 13 and Table 14. Table 13. Programming the AD5412 Data Register Table 14. Programming the AD5422 Data Register entered in the D15 to D0 positions, as shown in Table 15. The control register functions are shown in Table 16. Table 15. Programming the Control Register Table 16. Control Register Functions CLRSEL See Table 22 for a description of the CLRSEL operation. OVRRNG Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section). must be changed on the write in which the output is enabled. See Figure 69 for best practice. OUTEN Output enable. This bit must be set to enable the outputs. The range bits select which output is functional. SR clock Digital slew rate control (see the AD5412/AD5422 Features section). SR step Digital slew rate control (see the AD5412/AD5422 Features section). SREN Digital slew rate control enable. R2, R1, R0 Output range select (see Table 17). Table 17. Output Range Options entered in the D0 position as shown in Table 18. The reset register options are shown in Table 18 and Table 19.

Table 18. Programming the Reset Register Table 19. Reset Register Functions Reset Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state. The status register is a read-only register. The status register functionality is shown in Table 20 and Table 21. Table 20. Decoding the Status Register Table 21. Status Register Functions IOUT Fault This bit is set if a fault is detected on the IOUT pin. Slew Active This bit is set while the output value is slewing (slew rate control enabled). Over Temp This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C.

FAULT output becomes active. Under normal operation, the voltage output sinks/sources 10 mA. this is the short-circuit current. function is limited only by the available power supply headroom. minimum amount of time to complete the operation (see Figure 2). programmed until the CLEAR pin is returned low. Table 22. CLRSEL Options

1 Midscale Zero scale

default value as defined by CLRSEL and CLEAR SELECT. Figure 16 for a load regulation graph of the integrated reference. selected via the control register (see Table 15). supply is enabled by leaving the DVCC SELECT pin unconnected.

analog.com Rev. P | 38 of 41 INDUSTRIAL ANALOG OUTPUT MODULE Many industrial control applications have requirements for accu- rately controlled current and voltage output signals. The AD5412/ AD5422 are ideal for such applications. Figure 83 shows the AD5412/AD5422 in a circuit design for an output module, specifical- ly for use in an industrial control application. The design provides for a current or voltage output. The module is powered from a field supply of 24 V. This supplies AVDD directly. An inverting buck regulator generates the negative supply for AVSS. For transient overvoltage protection, transient voltage suppressors (TVS) are placed on all field accessible connections. A 24 V volt TVS is placed on each IOUT, VOUT, +VSENSE, and −VSENSE connection, and a 36 V TVS is placed on the field supply input. For added protection, clamping diodes are connected from the IOUT, VOUT, +VSENSE, and −VSENSE pins to the AVDD and AVSS power supply pins. If remote voltage load sensing is not required, the +VSENSE pin can be directly connected to the VOUT pin and the –VSENSE pin can be connected to GND. Isolation between the AD5412/AD5422 and the backplane circui- try is provided with ADuM1400 and ADuM1200 iCoupler digital isolators; further information on iCoupler products is available at www.analog.com/isolators. The internally generated digital power supply of the AD5412/AD5422 powers the field side of the digital isolaters, removing the need to generate a digital power supply on the field side of the isolation barrier. The AD5412/AD5422 digital supply output supplies up to 5 mA, which is more than enough to supply the 2.8 mA requirements of the ADuM1400 and ADuM1200 operating at a logic signal frequency of up to 1 MHz. To reduce the number of isolators required, nonessential signals such as CLEAR can be connected to GND. FAULT and SDO can be left unconnect- ed, reducing the isolation requirements to just three signals. See Circuit Note CN0321 for an example of a built and tested circuit of a fully isolated, single channel voltage and 4 mA to 20 mA output with HART. INDUSTRIAL HART CAPABLE ANALOG OUTPUT APPLICATION Many industrial control applications have requirements for accurate- ly controlled current output signals, and the AD5412/AD5422 are ideal for such applications. Figure 82 shows the AD5412/AD5422 in a circuit design for a HART-enabled output module, specifically for use in an industrial control application in which both the voltage output and current output are available—one at a time—on one pin, thus reducing the number of screw connections required. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time. For further information on this circuit, see Circuit Note CN0278, Complete 4 mA to 20 mA HART Solution with Additional Voltage Output Capability. The design provides for a HART-enabled current output, with the HART capability provided by the AD5700/AD5700-1 HART modem, the industry’s lowest power and smallest footprint HART-compliant IC modem. For additional space-savings, the AD5700-1 offers a 0.5% precision internal oscillator. The HART_OUT signal from the AD5700 is attenuated and ac-coupled into the RSET pin of the AD5412/AD5422. Because the RSET pin is used to couple the HART signal into the AD5412/AD5422, either the TSSOP or LFCSP package option can be used for this configuration. It should be noted however, that since the TSSOP package does not have a CAP1 pin, C1 (see Figure 82) cannot be inserted in this case. While the TSSOP equivalent circuit (as in Figure 82 but without C1 in place) still passes the HART Communication Foundation physical layer specs, the results with C1 in place are superior to those without C1 in place. Further information on an alternative configuration, whereby the HART signal is coupled into the CAP2 pin can be found in Application Note AN-1065. This is based on the AD5410/AD5420 but can also be applied to the AD5412/ AD5422. Use of either configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current. This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation. The module is powered from a field supply of ±10.8 V to ±26.4 V. This supplies AVDD/AVSS directly. For transient overvoltage protection, transient voltage suppressors (TVS) are placed on both the IOUT and field supply connections. A 24 V TVS is placed on the IOUT connection, and a 36 V TVS is placed on the field supply input(s). For added protection, clamping diodes are connected from the IOUT pin to the AVDD and GND power supply pins. A 10 kΩ current limiting resistor is also placed in series with the positive terminal of the +VSENSE buffer input. This is to limit the current to an acceptable level during a transient event.

6.40 BSC

0.10 COPLANARITY

1.20 MAX

Figure 84. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] Figure 85. 40-Lead Lead Frame Chip Scale Package [LFCSP]

©2009-2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. P | 41 of 41 RESOLUTION AND TUE OPTIONS Model1 Resolution (Bits) IOUT TUE (% FSR max) VOUT TUE (% FSR max) AD5412AREZ 12 0.5 0.3 AD5412AREZ-REEL7 12 0.5 0.3 AD5412ACPZ-REEL 12 0.5 0.3 AD5412ACPZ-REEL7 12 0.5 0.3 AD5422AREZ 16 0.5 0.3 AD5422AREZ-REEL 16 0.5 0.3 AD5422BREZ 16 0.3 0.1 AD5422BREZ-REEL 16 0.3 0.1 AD5422ACPZ-REEL 16 0.3 0.3 AD5422ACPZ-REEL7 16 0.3 0.3 AD5422BCPZ-REEL 16 0.3 0.1 AD5422BCPZ-REEL7 16 0.3 0.1 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Package Description EVAL-AD5422EBZ AD5422 Evaluation Board EVAL-AD5422LFEBZ AD5422 LFCSP Evaluation Board 1 Z = RoHS Compliant Part.