AD5305_06 AD | Alldatasheet
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2.5 V to 5.5 V, 500 μA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs AD5305/AD5315/AD5325 Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL Low power operation: 500 μA @ 3 V, 600 μA @ 5 V 2-wire (I2C®-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Three power-down modes Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Software clear facility Data readback facility On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control GENERAL DESCRIPTION The AD5305/AD5315/AD53251 are quad 8-, 10-, and 12-bit buffered voltage output DACs in a 10-lead MSOP that operate from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V . Their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-wire serial interface that operates at clock rates up to 400 kHz is used. This interface is SMBus compatible at V DD < 3.6 V . Multiple devices can be placed on the same bus. The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write takes place to the device. There is also a software clear function to reset all input and DAC registers to 0 V . The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited for portable battery-operated equip- ment. The power consumption is 3 mW at 5 V , 1.5 mW at 3 V , reducing to 1 μW in power-down mode. 1 Protected by U.S. Patent No. 5,969,657 and 5,684,481. FUNCTIONAL BLOCK DIAGRAM REF IN GND AD5305/AD5315/AD5325 SDA SCL BUFFER BUFFER BUFFER BUFFER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER VDD LDAC POWER-ON RESET INTERFACE LOGIC POWER-DOWN LOGIC STRING DAC A STRING DAC B STRING DAC C STRING DAC D DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER 00930-001 VOUTD VOUTC VOUTB VOUTA Figure 1.
Rev. G | Page 2 of 24 TABLE OF CONTENTS AD5305/AD5315/AD5325 as a Digitally Programmable Coarse and Fine Adjustment Using the
REVISION HISTORY
5/06—Rev. F to Rev. G 10/04—Rev. E to Rev. F 8/03—Rev. D to Rev. E 4/01—Rev. C to Rev. D Edits to Right/Left and Double Sections
Rev. G | Page 3 of 24 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 2 V , RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1. A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments DC PERFORMANCE3, 4 AD5305 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5315 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5325 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR Lower Deadband 20 60 20 60 mV Lower deadband exists only if offset error is negative Offset Error Drift5 −12 −12 ppm of FSR/°C Gain Error Drift5 −5 −5 ppm of FSR/°C Power Supply Rejection Ratio5 –60 –60 dB ∆VDD = ±10% DC Crosstalk5 200 200 μV RL = 2 kΩ to GND or VDD DAC REFERENCE INPUTS5 VREF Input Range 0.25 VDD 0.25 VDD V VREF Input Impedance 37 45 37 45 kΩ Normal operation >10 >10 MΩ Power-down mode Reference Feedthrough −90 −90 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 0.001 0.001 V A measure of the minimum and maximum drive capability of the output amplifier Maximum Output Voltage6 VDD − 0.001 VDD − 0.001 V DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 25 25 mA VDD = 5 V 16 16 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down mode VDD = 5 V 5 5 μs Coming out of power-down mode VDD = 3 V
Rev. G | Page 4 of 24 A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments LOGIC INPUTS (A0)5 Input Current ±1 ±1 μA Input Low Voltage, VIL 0.8 0.8 V VDD = 5 V ± 10% 0.6 0.6 V VDD = 3 V ± 10% 0.5 0.5 V VDD = 2.5 V Input High Voltage, VIH 2.4 2.4 V VDD = 5 V ± 10% 2.1 2.1 V VDD = 3 V ± 10% 2.0 2.0 V VDD = 2.5 V Pin Capacitance 3 3 pF LOGIC INPUTS (SCL, SDA)5 Input High Voltage, VIH 0.7 VDD VDD + 0.3 0.7 V DD VDD + 0.3 V SMBus compatible at VDD < 3.6 V Input Leakage Current, IIN ±1 ±1 μA Input Hysteresis, VHYST 0.05 VDD 0.05 V DD V Input Capacitance, CIN 8 8 pF Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of less than 50 ns LOGIC OUTPUT (SDA)5 Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Three-State Leakage Current ±1 ±1 μA Three-State Output Capacitance 8 8 pF POWER REQUIREMENTS VDD 2.5 5.5 2.5 5.5 V IDD (Normal Mode)7 VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 600 900 600 900 μA VDD = 2.5 V to 3.6 V 500 700 500 700 μA IDD (Power-Down Mode) VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA IDD = 4 μA (maximum) during 0 readback on SDA 0 readback on SDA 1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. G | Page 5 of 24 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V , RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 2. A, B Version1 Parameter2, 3 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = VDD = 5 V AD5305 6 8 μs ¼ scale to ¾ scale change (0×40 to 0×C0) AD5315 7 9 μs ¼ scale to ¾ scale change (0×100 to 0×300) AD5325 8 10 μs ¼ scale to ¾ scale change (0×400 to 0×C00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 1 nV-s Digital Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz 1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization, not production tested. 3 See the Terminology section. TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V , all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 Limit at TMIN, TMAX (A, B Version) Unit Conditions/Comments fSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD,STA, start/repeated start condition hold time t5 100 ns min tSU,DAT, data setup time t63 0.9 μs max tHD,DAT, data hold time 0 μs min tHD,DAT, data hold time t7 0.6 μs min tSU,STA, setup time for repeated start t8 0.6 μs min tSU,STO, stop condition setup time t9 1.3 μs min tBUF, bus-free time between a stop and a start condition t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 250 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1 CB4 ns min tF, fall time of SCL and SDA when transmitting CB4 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. G | Page 7 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter1 Rating VDD to GND –0.3 V to +7 V SCL, SDA to GND –0.3 V to VDD + 0.3 V A0 to GND –0.3 V to VDD + 0.3 V Reference Input Voltage to GND –0.3 V to VDD + 0.3 V VOUTA to VOUTD to GND –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C MSOP Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/W Reflow Soldering Peak Temperature 220°C Time at Peak Temperature 10 sec to 40 sec 1 Transient currents of up to 100 mA do not cause SCR latcth-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND. 2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. 6 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 7 GND Ground Reference Point for All Circuitry on the Part. register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface. 10 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
6 MSB are 000110 and the LSB is determined by the state of the
- The master initiates data transfer by establishing a start
read from or written to the slave device).
- Data is transmitted over the serial bus in sequences of nine
- When all data bits have been read or written, a stop
10th clock pulse to establish a stop condition. graphical explanation of the interface. Figure 31. Pointer Byte Table 6 explains the individual bits that make up the pointer byte. Table 6. Individual Bits of the Pointer Byte 0 Reserved bits. Must be set to 0. DACD [1] The following data bytes are for DAC D. DACC [1] The following data bytes are for DAC C. DACB [1] The following data bytes are for DAC B. DACA [1] The following data bytes are for DAC A. PD1 and PD0 bits that control the mode of operation of the device. Power-Down Modes section for a complete description. justified DAC data bits, starting with the MSB. See Figure 32. Figure 32. Data Formats for Write and Readback
Table 7. CLR and LDAC Bit Descriptions on completion of the write sequence. change in the contents of the DAC registers. readback bits are all 0, except for the CLR bit, which is a 1. control bits to 2, 3, or 4 DACs by setting the relevant bits to 1. conditions, that is, all 0s except for CLR, which is 1. to the DAC, as shown in Figure 33. A stop condition follows. are used and readback of data can commence immediately. Figure 33. Write Sequence
NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s. Figure 34. Readback Sequence register contains the digital code used by the resistor string. contents of the input register are transferred to it. was updated, thereby removing unnecessary digital crosstalk. (PD1 and PD0) of the data byte. the bits corresponds to the mode of operation of the DAC. Table 8. PD1/PD0 Operating Modes
Table 9. Overview of All AD53xx Serial Devices Table 10. Overview of AD53xx Parallel Devices
1.10 MAX
0.50 BSC
Figure 41. 10-Lead Mini Small Outline Package [MSOP] 1 Z = Pb-free part; # denotes lead-free product may be top or bottom marked.
Rev. G | Page 24 of 24 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00930-0-5/06(G)