AD5303BRU

AD5303 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5303/AD5313/AD5323* Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 +2.5 V to +5.5 V, 230 /H9262A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs FUNCTIONAL BLOCK DIAGRAM BUFFER POWER-DOWN LOGIC RESISTOR NETWORK STRING DAC AD5303/AD5313/AD5323 VOUTA VOUTB VDD VREFA VREFB DAC REGISTER DAC REGISTER SYNC SCLK DIN GND BUF A SDO CLR BUF B STRING DAC DCEN LDAC POWER-ON RESET PD BUFFER GAIN-SELECT LOGIC RESISTOR NETWORK INPUT REGISTER INPUT REGISTER INTERFACE LOGIC

FEATURES

AD5303: Two Buffered 8-Bit DACs in One Package AD5313: Two Buffered 10-Bit DACs in One Package AD5323: Two Buffered 12-Bit DACs in One Package 16-Lead TSSOP Package Micropower Operation: 300 /H9262A @ 5 V (Including Reference Current) Power-Down to 200 nA @ 5 V, 50 nA @ 3 V +2.5 V to +5.5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic By Design Over All Codes Buffered/Unbuffered Reference Input Options Output Range: 0–V REF or 0–2 V REF Power-On-Reset to Zero Volts SDO Daisy-Chaining Option Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS

Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single +2.5 V to +5.5 V supply consuming 230 µA at 3 V. Their on-chip output amplifiers allow the outp uts to swing rail-to-rail with a slew rate of 0.7 V/ µs. The AD5303/ AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI™, QSPI, MICROWIRE™ and DSP interface standards. The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a power- on-reset circuit that ensures that the DAC outputs power-up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisy-chaining applications using the SDO pin. The low power consumption of these parts in normal operation make them ideally suited to portable battery operated equip- ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V, reducing to 1 µW in power-down mode. *Protected by U.S. Patent No. 5684481; other patents pending. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0–2– AD5303/AD5313/AD5323–SPECIFICATIONS (VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k/H9024 to GND; CL = 200 pF to GND; all specifications T MIN to TMAX unless otherwise noted.) B Version 2 Parameter1 Min Typ Max Units Conditions/Comments DC PERFORMANCE 3, 4 AD5303 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic by Design Over All Codes AD5313 Resolution 10 Bits Relative Accuracy ±0.5 ±3 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic by Design Over All Codes AD5323 Resolution 12 Bits Relative Accuracy ±2 ±12 LSB Differential Nonlinearity ±0.2 ±1 LSB Guaranteed Monotonic by Design Over All Codes Offset Error ±0.4 ±3 % of FSR See Figures 3 and 4 Gain Error ±0.15 ±1 % of FSR See Figures 3 and 4 Lower Deadband 10 60 mV See Figures 3 and 4 Offset Error Drift 5 –12 ppm of FSR/ °C Gain Error Drift 5 –5 ppm of FSR/ °C Power Supply Rejection Ratio 5 –60 dB ∆VDD = ±10% DC Crosstalk5 30 µV DAC REFERENCE INPUTS 5 VREF Input Range 1 V DD V Buffered Reference Mode 0V DD V Unbuffered Reference Mode VREF Input Impedance >10 M Ω Buffered Reference Mode 180 k Ω Unbuffered Reference Mode. 0–V REF Output Range, Input Impedance = RDAC 90 k Ω Unbuffered Reference Mode. 0–2 VREF Output Range, Input Impedance = RDAC Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –80 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS 5 Minimum Output Voltage 6 0.001 V mi n This is a measure of the minimum and maximum Maximum Output Voltage 6 VDD – 0.001 V max drive capability of the output amplifier. DC Output Impedance 0.5 Ω Short Circuit Current 50 mA V DD = +5 V 20 mA V DD = +3 V Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V DD = +5 V 5 µs Coming Out of Power-Down Mode. V DD = +3 V LOGIC INPUTS 5 Input Current ±1 µA VIL, Input Low Voltage 0.8 V V DD = +5 V ± 10%

0.6 V V DD = +3 V ± 10%

0.5 V V DD = +2.5 V VIH, Input High Voltage 2.4 V V DD = +5 V ± 10%

2.1 V V DD = +3 V ± 10%

2.0 V V DD = +2.5 V Pin Capacitance 2 3.5 pF LOGIC OUTPUT (SDO) 5 VDD = +5 V ± 10% Output Low Voltage 0.4 V I SINK = 2 mA Output High Voltage 4.0 V I SOURCE = 2 mA VDD = +3 V ± 10% Output Low Voltage 0.4 V I SINK = 2 mA Output High Voltage 2.4 V I SOURCE = 2 mA Floating-State Leakage Current 1 µA DCEN = GND Floating State O/P Capacitance 3 pF DCEN = GND POWER REQUIREMENTS VDD 2.5 5.5 V I DD Specification Is Valid for All DAC Codes IDD (Normal Mode) Both DACs Active and Excluding Load Currents VDD = +4.5 V to +5.5 V 300 450 µA Both DACs in Unbuffered Mode. V IH = VDD and VDD = +2.5 V to +3.6 V 230 350 µAV IL = GND. In Buffered Mode, extra current is typically x µA per DAC where x = 5 µA + VREF/RDAC. IDD (Full Power-Down) VDD = +4.5 V to +5.5 V 0.2 1 µA VDD = +2.5 V to +3.6 V 0.05 1 µA

REV. 0 AD5303/AD5313/AD5323 –3– AC CHARACTERISTICS1 (VDD = +2.5 V to +5.5 V; RL = 2 k/H9024 to GND; CL = 200 pF to GND; all specifications T MIN to TMAX unless otherwise noted.) B Version3 Parameter2 Min Typ Max Units Conditions/Comments Output Voltage Settling Time V REF = VDD = +5 V AD5303 6 8 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) AD5313 7 9 µs 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) AD5323 8 10 µs 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) Slew Rate 0.7 V/ µs Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.10 nV-s Analog Crosstalk 0.01 nV-s DAC-to-DAC Crosstalk 0.01 nV-s Multiplying Bandwidth 200 kHz V REF = 2 V ± 0.1 V p-p. Unbuffered Mode Total Harmonic Distortion –70 dB V REF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz NOTES 1Guaranteed by design and characterization, not production tested. 2See Terminology. 3Temperature range: B Version: –40 °C to +105 °C. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2, 3 Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments t1 33 ns min SCLK Cycle Time t2 13 ns min SCLK High Time t3 13 ns min SCLK Low Time t4 0 ns min SYNC to SCLK Rising Edge Setup Time t5 5 ns min Data Setup Time t6 4.5 ns min Data Hold Time t7 0 ns min SCLK Falling Edge to SYNC Rising Edge t8 100 ns min Minimum SYNC High Time t9 20 ns min LDAC Pulsewidth t10 20 ns min SCLK Falling Edge to LDAC Rising Edge t11 20 ns min CLR Pulsewidth t12 4, 5 5 ns min SCLK Falling Edge to SDO Invalid t13 4, 5 20 ns max SCLK Falling Edge to SDO Valid t14 5 0 ns min SCLK Falling Edge to SYNC Rising Edge t15 5 10 ns min SYNC Rising Edge to SCLK Rising Edge NOTES 1Guaranteed by design and characterization, not production tested. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3See Figures 1 and 2. 4These are measured with the load circuit of Figure 1. 5Daisy-Chain Mode only (see Figure 45). Specifications subject to change without notice. (VDD = +2.5 V to +5.5 V; all specifications T MIN to TMAX unless otherwise noted.) NOTES 1See Terminology. 2Temperature range: B Version: –40 °C to +105 °C. 3DC specifications tested with the outputs unloaded. 4Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981). 5Guaranteed by design and characterization, not production tested. 6In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier outpu t to reach its maximum voltage, V REF = VDD and “Offset plus Gain” Error must be positive. Specifications subject to change without notice.

REV. 0 AD5303/AD5313/AD5323 –5– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = +25°C unless otherwise noted) Operating Temperature Range 16-Lead TSSOP Package Lead Temperature, Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. PIN CONFIGURATION TOP VIEW (Not to Scale) CLR LDAC VDD VREFB VREFA VOUTA BUF A BUF B SDO GND DIN SCLK SYNC V OUTB PD DCEN AD5303/ AD5313/ AD5323 ORDERING GUIDE Model Temperature Range Package Description Package Option AD5303BRU –40 °C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRU –40 °C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU –40 °C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16

REV. 0 AD5303/AD5313/AD5323 –6– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 CLR Active low control input that loads all zeroes to both input and DAC registers. 2 LDAC Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input regis- ters have new data. This allows simultaneous update of both DAC outputs 3V DD Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be decoupled to GND. 4V REFB Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buff- ered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from

0 V to V

DD in unbuffered mode and from 1 V to V DD in buffered mode. 5V REFA Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to V DD in buffered mode. 6V OUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 7 BUF A Control pin that controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 8 BUF B Control pin that controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy-chain. The pin should be tied low if it is being used in stand-alone mode. 10 PD Active low control input that acts as a hardware power-down option. This pin overrides any soft- ware power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). 11 V OUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers-on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered-down after each write cycle. 14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered-down after each write cycle. 15 GND Ground reference point for all circuitry on the part.

16 SDO Serial Data Output that can be used for daisy-chaining a number of these devices together or for

reading back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock. TERMINOLOGY RELATIVE ACCURACY For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 5. DIFFERENTIAL NONLINEARITY Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8. OFFSET ERROR This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. GAIN ERROR This is a measure of the span error of the DAC. It is the devia- tion in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. OFFSET ERROR DRIFT This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/ °C. GAIN ERROR DRIFT This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/ °C.

30 MHz and is compatible with SPI, QSPI, MICROWIRE and

8, 10 or 12 bits of DAC data, depending on the device type.

15 A/B 0: Data Written to DAC A N/A

14 GAIN 0: Output Range of 0–V REF 0

13 PD1 Mode Bit 0

12 PD0 Mode Bit 0

registers will not be updated. that clears the input and DAC registers of both DACs to all zeroes. the part, the SCLK and DIN input buffers are powered-down. They only power-up again following a falling edge of SYNC. relevant input register on completion of a valid write sequence. Access to the DAC register is controlled by the LDAC function. Figure 29. AD5303 Input Shift Register Contents Figure 30. AD5313 Input Shift Register Contents Figure 31. AD5323 Input Shift Register Contents

was updated thereby removing unnecessary digital crosstalk. VDD = 3 V. See Figure 22 for a plot. Figure 32. Output Stage During Power-Down *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 33. AD5303/AD5313/AD5323 to ADSP-2101/ADSP-

2103 Interface

*ADDITIONAL PINS OMITTED FOR CLARITY. Figure 34. AD5303/AD5313/AD5323 to 68HC11/68L11

80L51 outputs the serial data in a format that has the LSB first. should take this into account. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5303/AD5313/AD5323 to 80C51/80L51 into the AD5303/AD5313/AD5323 on the rising edge of the SK. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. AD5303/AD5313/AD5323 to MICROWIRE reference would be the REF191, a 2.048 V reference. Figure 37. AD5303/AD5313/AD5323 Using External at 8 bits and 0.011 LSB error at 12 bits. Figure 38. Using an REF195 as Power and Reference to the

Figure 45. Daisy-Chaining Timing Diagram

REV. 0 AD5303/AD5313/AD5323 –18– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) 16 9 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) C3448 –8–4/99 PRINTED IN U.S.A.