AD5302BRMZ-REEL7

AD5302_11 AD | Alldatasheet

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2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs AD5302/AD5312/AD5322 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006-2011 Analog Devices, Inc. All rights reserved.

FEATURES

AD5302: Two 8-bit buffered DACs in 1 package A version: ±1 LSB INL, B version: ±0.5 LSB INL AD5312: Two 10-bit buffered DACs in 1 package A version: ±4 LSB INL, B version: ±2 LSB INL AD5322: Two 12-bit buffered DACs in 1 package A version: ±16 LSB INL, B version: ±8 LSB INL 10-lead MSOP Micropower operation: 300 μA @ 5 V (including reference current) Power-down to 200 nA @ 5 V, 50 nA @ 3 V 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/Unbuffered reference input options

0 V to V

Simultaneous update of DAC outputs via LDAC Low power serial interface with Schmitt-triggered inputs On-chip rail-to-rail output buffer amplifiers Qualified for automotive applications

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit buffered voltage output DACs in a 10-lead MSOP that operate from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V . Their on-chip output amplifiers allow the outputs to swing rail- to-rail with a slew rate of 0.7 V/μs. The AD5302/AD5312/AD5322 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The references for the two DACs are derived from two reference pins (one per DAC). The reference inputs can be configured as buffered or unbuffered inputs. The outputs of both DACs can be updated simultaneously using the asynchronous LDAC input. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power-up to 0 V and remain there until a valid write takes place to the device. The parts contain a power- down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software- selectable output loads while in power-down mode. The low power consumption of these parts in normal operation makes them ideally suited for portable battery-operated equipment. The power consumption is 1.5 mW at 5 V , 0.7 mW at 3 V , reducing to 1 μW in power-down mode. FUNCTIONAL BLOCK DIAGRAM DAC REGISTER RESISTOR NETWORK POWER-DOWN LOGIC RESISTOR NETWORK BUFFER STRING DAC STRING DAC AD5302/AD5312/AD5322 INPUT REGISTER INPUT REGISTER DAC REGISTER INTERFACE LOGICSCLK POWER-ON RESET VDD VREFA VOUTA VOUTA VOUTB VOUTB GNDVREFBLDAC DIN 00928-001 SYNC BUFFER Figure 1.

Rev. D | Page 2 of 24 TABLE OF CONTENTS AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Opto-Isolated Interface for Process Control Applications ... 19 AD5302/AD5312/AD5322 as a Digitally Programmable Coarse and Fine Adjustment Using the

REVISION HISTORY

5/11—Rev. C to Rev. D 4/06—Rev. B to Rev. C 12/05—Rev. A to Rev. B 8/03—Rev. 0 to Rev. A

Rev. D | Page 3 of 24 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 2 V , RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1. A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE3 , 4 AD5302 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5312 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5322 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 3 and Figure 4 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 3 and Figure 4 Lower Deadband 10 60 10 60 mV See Figure 3 and Figure 4 Offset Error Drift5 −12 −12 ppm of FSR/°C Gain Error Drift5 −5 −5 ppm of FSR/°C Power Supply Rejection Ratio5 DC Crosstalk5 30 30 μV DAC REFERENCE INPUTS5 VREF Input Range 1 VDD 1 VDD V Buffered reference mode

0 VDD 0 VDD V Unbuffered reference mode

VREF Input Impedance >10 >10 MΩ Buffered reference mode 180 180 kΩ Unbuffered reference mode, input impedance = RDAC Reference Feedthrough −90 −90 dB Frequency = 10 kHz Channel-to-Channel Isolation −80 −80 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 0.001 0.001 V min A measure of the minimum drive capability of the output amplifier Maximum Output Voltage6 VDD − 0.001 VDD − 0.001 V max A measure of the maximum drive capability of the output amplifier DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 50 50 mA VDD = 5 V 20 20 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down mode, VDD = 5 V 5 5 μs Coming out of power-down mode, VDD = 3 V LOGIC INPUTS5 Input Current ±1 ±1 μA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10% 0.6 0.6 V VDD = 3 V ± 10% 0.5 0.5 V VDD = 2.5 V VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10% 2.1 2.1 V VDD = 3 V ± 10% 2.0 2.0 V VDD = 2.5 V Pin Capacitance 2 3.5 2 3.5 pF

Rev. D | Page 4 of 24 A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes IDD (Normal Mode) Both DACs active and excluding load currents VDD = 4.5 V to 5.5 V 300 450 300 450 μA Both DACs in unbuffered mode, VIH = VDD and VDD = 2.5 V to 3.6 V 230 350 230 350 μA VIL = GND; in buffered mode, extra current is typically × μA per DAC where x = 5 μA + VREF/RDAC IDD (Full Power-Down) VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 μA 1 Temperature range: A, B version: –40°C to +105°C. 2 See Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. AC SPECIFICATIONS VDD = 2.5 V to 5.5 V , RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1 Table 2. A, B Version2 Parameter3 Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time VREF = VDD = 5 V AD5302 6 8 μs ¼ Scale to ¾ Scale Change (0 × 40 to 0 × C0) AD5312 7 9 μs ¼ Scale to ¾ Scale Change (0 × 100 to 0 × C300) AD5322 8 10 μs ¼ Scale to ¾ Scale Change (0 × 400 to 0 × C00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry (011…11 to 100…00) Digital Feedthrough 0.10 nV-s Analog Crosstalk 0.01 nV-s DAC-to-DAC Crosstalk 0.01 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p, Unbuffered Mode Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, Frequency = 10 kHz 1 Guaranteed by design and characterization, not production tested. 2 Temperature range: A, B version: −40°C to +105°C. 3 See Terminology section.

1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 1SEE INPUT SHIFT REGISTER SECTION. Figure 2. Serial Interface Timing Diagram

Table 4. Stresses above those listed under Absolute Maximum Ratings 1 Transient currents of up to 100 mA do not cause SCR latch-up. degradation or loss of functionality.

Figure 5. Pin Configuration Table 5. Pin Function Descriptions 1 LDAC Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers. allows simultaneous updating of both DAC outputs. 2 VDD Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. unbuffered mode and 1 V to VDD in buffered mode. unbuffered mode and 1 V to VDD in buffered mode. 5 V OUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 6 V OUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. as an interrupt and the write sequence is ignored by the device. can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 10 GND Ground Reference Point for All Circuitry on the Part.

Rev. D | Page 9 of 24 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-sec and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high, then pulsing LDAC low, and monitoring the output of the DAC whose digital code is not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of the other DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC low and monitoring the output of the other DAC. The area of the glitch is expressed in nV-sec. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while monitoring the other DAC. It is expressed in μV . Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V OUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied ±10%. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in dB. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dB. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Channel-to-Channel Isolation Definition This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of the other DAC. It is measured in dB.

The input shift register is 16 bits wide (see Figure 30 to Figure 32). which determines whether the data is for DAC A or DAC B. Bit 14 determines if the reference input is buffered or unbuffered. Bit 13 and Bit 12 control the operating mode of the DAC. Table 6. Control Bits

15 A/B 0: Data Written to DAC A N/A

14 BUF 0: Reference Is Unbuffered 0

13 PD1 Mode Bit 0

12 PD0 Mode Bit 0

Figure 30. AD5302 Input Shift Register Contents Figure 31. AD5312 Input Shift Register Contents Figure 32. AD5322 Input Shift Register Contents corresponding to full-scale output (VREF – 1 LSB). transfers occur until SYNC is taken high and low again. to the part, the SCLK and DIN input buffers are powered down. register contains the digital code used by the resistor string. register are transferred to it. outputs update simultaneously.

Table 7. PD1/PD0 Operating Modes output of the amplifier to a resistor network of known values. of the DAC amplifier. There are three different options.

• The output is connected internally to GND through a 1 kΩ resistor,
• The output is connected internally to GND through a 100 kΩ resistor, or
• The output is left open-circuited (three-state). The output stage is illustrated in Figure 33. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for V DD = 5 V and 5 μs when VDD = 3 V . See Figure 23 for a plot. RESISTOR- STRING DAC AMPLIFIER VOUT 00928-033 POWER-DOWN CIRCUITRY RESISTOR NETWORK

Figure 33. Output Stage During Power-Down

2103 INTERFACE

clock. This corresponds to the falling edge of the DAC’s SCLK. Figure 34. AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface while the MOSI output drives the serial data line of the DAC. Figure 35. AD5302/AD5312/AD5322 to 68HC11/68L11 Interface Figure 36. AD5302/AD5312/AD5322 to 80C51/80L51 Interface into the AD5302/AD5312/AD5322 on the rising edge of the SK. Figure 37. AD5302/AD5312/AD5322 to MICROWIRE Interface

external reference would be the REF191, a 2.048 V reference. Figure 38. AD5302/AD5312/AD5322 Using External Reference the simplest solution is to connect the reference inputs to VDD. at eight bits and a 0.011 LSB error at 12 bits. Figure 39. Using a REF195 as Power and Reference to the or OP295 as the output amplifier. Figure 40. Bipolar Operation Using the AD5302/AD5312/AD5322 D is the decimal equivalent of the code loaded to the DAC. VREF is the reference voltage input.

Figure 44. Coarse/Fine Adjustment that handle transient currents due to internal logic switching. paths and reduce the effects of glitches on the power supply line. cated to ground while signal traces are placed on the solder side.

0.50 BSC

1.10 MAX

Figure 45. 10-Lead Mini Small Outline Package [MSOP]

Rev. D | Page 22 of 24 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding AD5302ARM −40°C to +105°C 10-Lead MSOP RM-10 D5A AD5302ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A AD5302ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302ARMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302BRM −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5302BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5302BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5312ARM −40°C to +105°C 10-Lead MSOP RM-10 D6A AD5312ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6A# AD5312ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A# AD5312BRM −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5312BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5312BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5322ARM −40°C to +105°C 10-Lead MSOP RM-10 D7A AD5322ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7A AD5322ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6T AD5322ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6T AD5322BRM −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5322BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5322BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5312WARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A# 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5312W ARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model.

Rev. D | Page 23 of 24 NOTES

Rev. D | Page 24 of 24 NOTES ©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00928-0-5/11(D)