AD5301BRM

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5301/AD5311/AD5321* Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 +2.5 V to +5.5 V, 120 mA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs FUNCTIONAL BLOCK DIAGRAM RESISTOR NETWORK BUFFER VOUT DAC REGISTER POWER-DOWN LOGIC AD5301/AD5311/AD5321 VDD SCL GND A1* REF POWER-ON RESET PD* SDA *AVAILABLE ON 8-LEAD VERSION ONLY 8-/10-/12-BIT DAC INTERFACE LOGIC

FEATURES

AD5301: Buffered Voltage Output 8-Bit DAC AD5311: Buffered Voltage Output 10-Bit DAC AD5321: Buffered Voltage Output 12-Bit DAC 6-Lead SOT-23 and 8-Lead mSOIC Packages Micropower Operation: 120 mA @ 3 V 2-Wire (I 2C® Compatible) Serial Interface Data Readback Capability +2.5 V to +5.5 V Power Supply Guaranteed Monotonic By Design Over All Codes Power-Down to 50 nA @ 3 V Reference Derived from Power Supply Power-On-Reset to Zero Volts On-Chip Rail-to-Rail Output Buffer Amplifier Three Power-Down Functions

APPLICATIONS

Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit buffered voltage-output DACs that operate from a single +2.5 V to +5.5 V supply consuming 120 mA at 3 V. The on-chip output amplifier allows rail-to-rail output swing with a slew rate of 0.7 V/ms. It uses a 2-wire (I 2C compatible) serial interface that operates at clock rates up to 400 kHz. Multiple devices can share the same bus. The reference for the DAC is derived from the power supply inputs and thus gives the widest dynamic output range. These parts incorporate a power-on-reset circuit, which ensures that the DAC output powers-up to zero volts and remains there until a valid write takes place. The parts contain a power-down feature which reduces the current consumption of the device to 50 nA at 3 V and provides software-selectable output loads while in power-down mode. The low power consumption in normal operation make these DACs ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V reducing to 1 mW in all power-down modes. I2C is a registered trademark of Philips Corporation. *Protected by U.S. Patent No. 5684481, other patent pending.

REV. 0–2– AD5301/AD5311/AD5321–SPECIFICATIONS(VDD = +2.5 V to +5.5 V; RL = 2 kV to GND; CL = 200 pF to GND; All specifications T MIN to TMAX unless otherwise noted.) B Version2 Parameter1 Min Typ Max Units Conditions/Comments DC PERFORMANCE3, 4 AD5301 Resolution 8 Bits Relative Accuracy – 0.15 – 1 LSB Differential Nonlinearity – 0.02 – 0.25 LSB Guaranteed Monotonic by Design Over All Codes AD5311 Resolution 10 Bits Relative Accuracy – 0.5 – 4 LSB Differential Nonlinearity – 0.05 – 0.5 LSB Guaranteed Monotonic by Design Over All Codes AD5321 Resolution 12 Bits Relative Accuracy – 2 – 16 LSB Differential Nonlinearity – 0.3 – 0.8 LSB Guaranteed Monotonic by Design Over All Codes Zero Code Error +5 +20 mV All Zeros Loaded to DAC, See Figure 9 Full-Scale Error – 0.15 – 1.25 % of FSR All Ones Loaded to DAC, See Figure 9 Gain Error – 0.15 – 1 % of FSR Zero Code Error Drift 5 –20 mV/°C Gain Error Drift 5 –5 ppm of FSR/ °C OUTPUT CHARACTERISTICS 5 Minimum Output Voltage 0.001 V min This is a measure of the minimum and maximum drive Maximum Output Voltage V DD – 0.001 V max capability of the output amplifier. DC Output Impedance 1 W Short Circuit Current 50 mA V DD = +5 V 20 mA V DD = +3 V Power-Up Time 2.5 ms Coming Out of Power-Down Mode. V DD = +5␣ V 6 ms Coming Out of Power-Down Mode. V DD = +3␣ V LOGIC INPUTS (A0, A1, PD)5 Input Current – 1 mA VIL, Input Low Voltage 0.8 V V DD = +5 V – 10%

0.6 V V DD = +3 V – 10%

0.5 V V DD = +2.5 V VIH, Input High Voltage 2.4 V V DD = +5 V – 10%

2.1 V V DD = +3 V – 10%

2.0 V V DD = +2.5 V Pin Capacitance 3 pF LOGIC INPUTS (SCL, SDA) 5 VIH, Input High Voltage 0.7 V DD VDD + 0.3 V VIL, Input Low Voltage –0.3 0.3 V DD V IIN, Input Leakage Current – 1 mAV IN = 0 V to VDD VHYST, Input Hysteresis 0.05 V DD V CIN, Input Capacitance 6 pF Glitch Rejection 6 50 ns Pulsewidth of Spike Suppressed LOGIC OUTPUT (SDA) 5 VOL, Output Low Voltage 0.4 V I SINK = 3 mA

0.6 V I SINK = 6 mA

Three-State Leakage Current – 1 mA Three-State Output Capacitance 6 pF POWER REQUIREMENTS VDD 2.5 5.5 V I DD Specification Is Valid for All DAC Codes IDD (Normal Mode) DAC Active and Excluding Load Current VDD = +4.5 V to +5.5 V 150 250 mAV IH = VDD and VIL = GND VDD = +2.5 V to +3.6 V 120 220 mAV IH = VDD and VIL = GND IDD (Power-Down Mode) VDD = +4.5 V to +5.5 V 0.2 1 mAV IH = VDD and VIL = GND VDD = +2.5 V to +3.6 V 0.05 1 mAV IH = VDD and VIL = GND NOTES 1See Terminology. 2Temperature ranges are as follows: B Version: –40 °C to +105°C. 3DC specifications tested with the outputs unloaded. 4Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000). 5Guaranteed by Design and Characterization, not production tested. 6Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. Specifications subject to change without notice.

REV. 0 AD5301/AD5311/AD5321 –3– AC CHARACTERISTICS1 B Version3 Parameter2 Min Typ Max Units Conditions/Comments Output Voltage Settling Time V DD = +5 V AD5301 6 8 ms 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) AD5311 7 9 ms 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) AD5321 8 10 ms 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) Slew Rate 0.7 V/ ms Major-Code Change Glitch Impulse 12 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.3 nV-s NOTES 1See Terminology 2Guaranteed by design and characterization, not production tested. 3Temperature ranges are as follows: B Version: –40 °C to +105 °C. Specifications subject to change without notice. TIMING CHARACTERISTICS1 Limit at TMIN, TMAX Parameter2 (B Version) Units Conditions/Comments fSCL 400 kHz max SCL Clock Frequency t1 2.5 ms min SCL Cycle Time t2 0.6 ms min t HIGH, SCL High Time t3 1.3 ms min t LOW, SCL Low Time t4 0.6 ms min t HD,STA, Start/Repeated Start Condition Hold Time t5 100 ns min t SU,DAT, Data Setup Time t63 0.9 ms max t HD,DAT, Data Hold Time 0 ms min t7 0.6 ms min t SU,STA, Setup Time for Repeated Start t8 0.6 ms min t SU,STO, Stop Condition Setup Time t9 1.3 ms min t BUF, Bus Free Time Between a STOP Condition and a START Condition t10 300 ns max t R, Rise Time of Both SCL and SDA when Receiving 0 ns min May be CMOS Driven t11 250 ns max t F, Fall Time of SDA when Receiving 300 ns max t F, Fall Time of Both SCL and SDA when Transmitting 20 + 0.1Cb4 ns min Cb 400 pF max Capacitive Load for Each Bus Line NOTES 1See Figure 1. 2Guaranteed by design and characterization, not production tested. 3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH MIN of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4Cb is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 V DD. Specifications subject to change without notice. (VDD = +2.5 V to +5.5 V; RL = 2 kW to GND; CL = 200 pF to GND; All specifications T MIN to TMAX unless otherwise noted.) (VDD = +2.5 V to +5.5 V. All specifications T MIN to TMAX unless otherwise noted.)

accumulate on the human body and test equipment and can discharge without detection. ESD precautions are recommended to avoid performance degradation or loss of functionality. tions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. Figure 1. 2-Wire Serial Interface Timing Diagram

REV. 0 AD5301/AD5311/AD5321 –5– PIN CONFIGURATIONS 6-Lead SOT-23 8-Lead mSOIC (RT-6) (RM-8) TOP VIEW (Not to Scale) GND SDA SCL VDD VOUT TOP VIEW (Not to Scale) PDVOUT GNDVDD SCL SDA AD5301/AD5311/AD5321 AD5301/AD5311/AD5321 PIN FUNCTION DESCRIPTION mSOIC SOT-23 Pin No. Pin No. Mnemonic Function 16 V DD Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be decoupled with a 10 mF in parallel with a 0.1 mF capacitor to GND. 2 5 A0 Address Input. Sets the Least Significant Bit of the 7-bit slave address. 3 N/A A1 Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address. 44 V OUT Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation. 5 N/A PD Active low control input that acts as a hardware power-down option. This pin overrides any software power-down option. The DAC output goes three-state and the current consumption of the part drops to 50 nA @ 3 V (200 nA @ 5 V). 6 3 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I 2C compat- ible interface. SCL may be CMOS/TTL driven. 7 2 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register during the write cycle and used to read back one or two bytes of data (one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven. 8 1 GND Ground reference point for all circuitry on the part.

REV. 0 AD5301/AD5311/AD5321 –6– TERMINOLOGY RELATIVE ACCURACY For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. Code plots can be seen in Figures 2 to 4. DIFFERENTIAL NONLINEARITY Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of – 1 LSB maximum ensures monotonicity. These DACs are guaranteed monotonic by design over all codes. Typical DNL vs. Code plots can be seen in Figures 5 to 7. ZERO CODE ERROR Zero Code Error is a measure of the output error when zero code (00H) is loaded to the DAC register. Ideally, the output should be 0 V. The Zero Code Error of the AD5301/AD5311/ AD5321 is always positive because the output of the DAC can- not go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. It is expressed in mV, see Figure 9. FULL-SCALE ERROR Full-Scale Error is a measure of the output error when full scale is loaded to the DAC register. Ideally, the output should be V DD – 1 LSB. Full-scale error is expressed in percent of FSR (full- scale range). A plot can be seen in Figure 9. GAIN ERROR This is a measure of the span error of the DAC. It is the devia- tion in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. ZERO CODE ERROR DRIFT This is a measure of the change in zero code error with a change in tem perature. It is expressed in mV/°C. GAIN ERROR DRIFT This is a measure of the change in gain error with changes in tem- perature. It is expressed in (ppm of full-scale range)/°C. MAJOR CODE TRANSITION GLITCH ENERGY Major Code Transition Glitch Energy is the energy of the im- pulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to DIGITAL FEEDTHROUGH Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to. It is specified in nV-secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa.

REV. 0 –15– 6-Lead SOT-23 (RT-6) 0.122 (3.10) 0.106 (2.70) PIN 1 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) BSC 0.037 (0.95) BSC 1 3 4 5 6 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10° 0°0.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) SEATING PLANE 0.057 (1.45) 0.035 (0.90) 8-Lead mSOIC (RM-8) 0.009 (0.23) 0.005 (0.13) 0.028 (0.70) 0.016 (0.40) 0.037 (0.95) 0.030 (0.75) 0.122 (3.10) 0.114 (2.90) PIN 1 0.0256 (0.65) BSC 0.122 (3.10) 0.114 (2.90) 0.193 (4.90) BSC SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.016 (0.40) 0.010 (0.25) 0.043 (1.10) MAX OUTLINE DIMENSIONS Dimensions shown in inches and (mm). AD5301/AD5311/AD5321 C3531–8–7/99PRINTED IN U.S.A.